Blame - tests/tcg/xtensa/test_break.S - qemu

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Max Filippov	a2e6707	2014-02-10 20:20:52 +0400	[diff] [blame]	1	#include "macros.inc"
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	2
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	3	test_suite break
				4
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	5	#if XCHAL_HAVE_DEBUG
				6
				7	#define debug_level XCHAL_DEBUGLEVEL
				8	#define debug_vector glue(level, XCHAL_DEBUGLEVEL)
				9	#define EPC_DEBUG glue(epc, XCHAL_DEBUGLEVEL)
				10
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	11	test break
				12	set_vector debug_vector, 0
				13	rsil a2, debug_level
				14	_break 0, 0
				15
				16	set_vector debug_vector, 2f
				17	rsil a2, debug_level - 1
				18	1:
				19	_break 0, 0
				20	test_fail
				21	2:
				22	rsr a2, ps
				23	movi a3, 0x1f
				24	and a2, a2, a3
				25	movi a3, 0x10 \| debug_level
				26	assert eq, a2, a3
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	27	rsr a2, EPC_DEBUG
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	28	movi a3, 1b
				29	assert eq, a2, a3
				30	rsr a2, debugcause
				31	movi a3, 0x8
				32	assert eq, a2, a3
				33	test_end
				34
				35	test breakn
				36	set_vector debug_vector, 0
				37	rsil a2, debug_level
				38	_break.n 0
				39
				40	set_vector debug_vector, 2f
				41	rsil a2, debug_level - 1
				42	1:
				43	_break.n 0
				44	test_fail
				45	2:
				46	rsr a2, ps
				47	movi a3, 0x1f
				48	and a2, a2, a3
				49	movi a3, 0x10 \| debug_level
				50	assert eq, a2, a3
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	51	rsr a2, EPC_DEBUG
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	52	movi a3, 1b
				53	assert eq, a2, a3
				54	rsr a2, debugcause
				55	movi a3, 0x10
				56	assert eq, a2, a3
				57	test_end
				58
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	59	#if XCHAL_NUM_IBREAK
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	60	test ibreak
				61	set_vector debug_vector, 0
				62	rsil a2, debug_level
				63	movi a2, 1f
				64	wsr a2, ibreaka0
				65	movi a2, 1
				66	wsr a2, ibreakenable
				67	isync
				68	1:
				69	rsil a2, debug_level - 1
				70	movi a2, 1f
				71	wsr a2, ibreaka0
				72	movi a2, 0
				73	wsr a2, ibreakenable
				74	isync
				75	1:
				76	set_vector debug_vector, 2f
				77	movi a2, 1f
				78	wsr a2, ibreaka0
				79	movi a2, 1
				80	wsr a2, ibreakenable
				81	isync
				82	1:
				83	test_fail
				84	2:
				85	rsr a2, ps
				86	movi a3, 0x1f
				87	and a2, a2, a3
				88	movi a3, 0x10 \| debug_level
				89	assert eq, a2, a3
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	90	rsr a2, EPC_DEBUG
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	91	movi a3, 1b
				92	assert eq, a2, a3
				93	rsr a2, debugcause
				94	movi a3, 0x2
				95	assert eq, a2, a3
				96	test_end
				97
Max Filippov	ad4ccc9	2012-04-10 02:48:20 +0400	[diff] [blame]	98	test ibreak_remove
				99	set_vector debug_vector, 3f
				100	rsil a2, debug_level - 1
				101	movi a2, 2f
				102	wsr a2, ibreaka0
				103	movi a3, 1
				104	1:
				105	wsr a3, ibreakenable
				106	isync
				107	2:
				108	beqz a3, 4f
				109	test_fail
				110	3:
				111	assert eqi, a3, 1
				112	rsr a2, ps
				113	movi a3, 0x1f
				114	and a2, a2, a3
				115	movi a3, 0x10 \| debug_level
				116	assert eq, a2, a3
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	117	rsr a2, EPC_DEBUG
Max Filippov	ad4ccc9	2012-04-10 02:48:20 +0400	[diff] [blame]	118	movi a3, 2b
				119	assert eq, a2, a3
				120	rsr a2, debugcause
				121	movi a3, 0x2
				122	assert eq, a2, a3
				123
				124	movi a2, 0x40000
				125	wsr a2, ps
				126	isync
				127	movi a3, 0
				128	j 1b
				129	4:
				130	test_end
				131
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	132	test ibreak_priority
				133	set_vector debug_vector, 2f
				134	rsil a2, debug_level - 1
				135	movi a2, 1f
				136	wsr a2, ibreaka0
				137	movi a2, 1
				138	wsr a2, ibreakenable
				139	isync
				140	1:
				141	break 0, 0
				142	test_fail
				143	2:
				144	rsr a2, debugcause
				145	movi a3, 0x2
				146	assert eq, a2, a3
				147	test_end
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	148	#endif
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	149
				150	test icount
				151	set_vector debug_vector, 2f
				152	rsil a2, debug_level - 1
				153	movi a2, -2
				154	wsr a2, icount
				155	movi a2, 1
				156	wsr a2, icountlevel
				157	isync
				158	rsil a2, 0
				159	nop
				160	1:
				161	break 0, 0
				162	test_fail
				163	2:
				164	movi a2, 0
				165	wsr a2, icountlevel
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	166	rsr a2, EPC_DEBUG
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	167	movi a3, 1b
				168	assert eq, a2, a3
				169	rsr a2, debugcause
				170	movi a3, 0x1
				171	assert eq, a2, a3
				172	test_end
				173
				174	.macro check_dbreak dr
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	175	rsr a2, EPC_DEBUG
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	176	movi a3, 1b
				177	assert eq, a2, a3
				178	rsr a2, debugcause
				179	movi a3, 0x4 \| (\dr << 8)
				180	assert eq, a2, a3
				181	movi a2, 0
				182	wsr a2, dbreakc\dr
				183	.endm
				184
				185	.macro dbreak_test dr, ctl, break, access, op
				186	set_vector debug_vector, 2f
				187	rsil a2, debug_level - 1
				188	movi a2, \ctl
				189	wsr a2, dbreakc\dr
				190	movi a2, \break
				191	wsr a2, dbreaka\dr
				192	movi a2, \access
				193	isync
				194	1:
				195	\op a3, a2, 0
				196	test_fail
				197	2:
				198	check_dbreak \dr
				199	reset_ps
				200	.endm
				201
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	202	#if XCHAL_NUM_DBREAK
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	203	#define DB0 0
				204	#if XCHAL_NUM_DBREAK > 1
				205	#define DB1 1
				206	#else
				207	#define DB1 0
				208	#endif
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	209	test dbreak_exact
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	210	dbreak_test DB0, 0x4000003f, 0xd000007f, 0xd000007f, l8ui
				211	dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007e, l16ui
				212	dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007c, l32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	213
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	214	dbreak_test DB1, 0x8000003f, 0xd000007f, 0xd000007f, s8i
				215	dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007e, s16i
				216	dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	217	test_end
				218
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	219	test DBdbreak_overlap
				220	dbreak_test DB0, 0x4000003f, 0xd000007d, 0xd000007c, l16ui
				221	dbreak_test DB1, 0x4000003f, 0xd000007d, 0xd000007c, l32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	222
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	223	dbreak_test DB0, 0x4000003e, 0xd000007e, 0xd000007f, l8ui
				224	dbreak_test DB1, 0x4000003e, 0xd000007e, 0xd000007c, l32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	225
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	226	dbreak_test DB0, 0x4000003c, 0xd000007c, 0xd000007d, l8ui
				227	dbreak_test DB1, 0x4000003c, 0xd000007c, 0xd000007c, l16ui
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	228
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	229	dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007b, l8ui
				230	dbreak_test DB1, 0x40000038, 0xd0000078, 0xd000007a, l16ui
				231	dbreak_test DB0, 0x40000038, 0xd0000078, 0xd000007c, l32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	232
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	233	dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000075, l8ui
				234	dbreak_test DB0, 0x40000030, 0xd0000070, 0xd0000076, l16ui
				235	dbreak_test DB1, 0x40000030, 0xd0000070, 0xd0000078, l32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	236
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	237	dbreak_test DB0, 0x40000020, 0xd0000060, 0xd000006f, l8ui
				238	dbreak_test DB1, 0x40000020, 0xd0000060, 0xd0000070, l16ui
				239	dbreak_test DB0, 0x40000020, 0xd0000060, 0xd0000074, l32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	240
				241
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	242	dbreak_test DB0, 0x8000003f, 0xd000007d, 0xd000007c, s16i
				243	dbreak_test DB1, 0x8000003f, 0xd000007d, 0xd000007c, s32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	244
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	245	dbreak_test DB0, 0x8000003e, 0xd000007e, 0xd000007f, s8i
				246	dbreak_test DB1, 0x8000003e, 0xd000007e, 0xd000007c, s32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	247
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	248	dbreak_test DB0, 0x8000003c, 0xd000007c, 0xd000007d, s8i
				249	dbreak_test DB1, 0x8000003c, 0xd000007c, 0xd000007c, s16i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	250
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	251	dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007b, s8i
				252	dbreak_test DB1, 0x80000038, 0xd0000078, 0xd000007a, s16i
				253	dbreak_test DB0, 0x80000038, 0xd0000078, 0xd000007c, s32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	254
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	255	dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000075, s8i
				256	dbreak_test DB0, 0x80000030, 0xd0000070, 0xd0000076, s16i
				257	dbreak_test DB1, 0x80000030, 0xd0000070, 0xd0000078, s32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	258
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	259	dbreak_test DB0, 0x80000020, 0xd0000060, 0xd000006f, s8i
				260	dbreak_test DB1, 0x80000020, 0xd0000060, 0xd0000070, s16i
				261	dbreak_test DB0, 0x80000020, 0xd0000060, 0xd0000074, s32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	262	test_end
				263
Max Filippov	64407f6	2022-04-25 17:16:01 -0700	[diff] [blame]	264	test DBdbreak_invalid
				265	dbreak_test DB0, 0x40000030, 0xd0000071, 0xd0000070, l16ui
				266	dbreak_test DB1, 0x40000035, 0xd0000072, 0xd0000070, l32i
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	267	test_end
Max Filippov	66c58ba	2019-02-18 06:24:38 -0800	[diff] [blame]	268	#endif
				269
				270	#endif
Max Filippov	e7dfa64	2012-01-13 09:22:07 +0400	[diff] [blame]	271
				272	test_suite_end