blob: 75bb55aeac912d9676c43a54cf7b1b7578227c21 [file] [log] [blame]
bellardc896fe22008-02-01 10:05:41 +00001/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Richard Henderson951c6302014-09-19 11:39:20 -070024
bellardc896fe22008-02-01 10:05:41 +000025#include "tcg.h"
Richard Henderson944eea92014-04-07 23:08:47 -070026#include "exec/helper-proto.h"
Richard Hendersonc0172302014-04-07 23:36:08 -070027#include "exec/helper-gen.h"
28
Richard Henderson951c6302014-09-19 11:39:20 -070029/* Basic output routines. Not for general consumption. */
bellardc896fe22008-02-01 10:05:41 +000030
Richard Hendersonb7e8b172017-10-15 11:50:16 -070031void tcg_gen_op1(TCGOpcode, TCGArg);
32void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
33void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
34void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
35void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
36void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
Richard Henderson951c6302014-09-19 11:39:20 -070037
Richard Hendersond2fd7452017-09-14 13:53:46 -070038void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
39void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
40void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
41
Richard Henderson951c6302014-09-19 11:39:20 -070042static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
Richard Henderson212c3282012-10-02 11:32:28 -070043{
Richard Hendersonae8b75d2017-10-15 13:27:56 -070044 tcg_gen_op1(opc, tcgv_i32_arg(a1));
Richard Henderson212c3282012-10-02 11:32:28 -070045}
46
Richard Henderson951c6302014-09-19 11:39:20 -070047static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
pbrookac56dd42008-02-03 19:56:33 +000048{
Richard Hendersonae8b75d2017-10-15 13:27:56 -070049 tcg_gen_op1(opc, tcgv_i64_arg(a1));
pbrooka7812ae2008-11-17 14:43:54 +000050}
51
Richard Henderson951c6302014-09-19 11:39:20 -070052static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
pbrooka7812ae2008-11-17 14:43:54 +000053{
Richard Hendersonb7e8b172017-10-15 11:50:16 -070054 tcg_gen_op1(opc, a1);
pbrookac56dd42008-02-03 19:56:33 +000055}
56
Richard Henderson951c6302014-09-19 11:39:20 -070057static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
bellardc896fe22008-02-01 10:05:41 +000058{
Richard Hendersonae8b75d2017-10-15 13:27:56 -070059 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
bellardc896fe22008-02-01 10:05:41 +000060}
61
Richard Henderson951c6302014-09-19 11:39:20 -070062static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
bellardc896fe22008-02-01 10:05:41 +000063{
Richard Hendersonae8b75d2017-10-15 13:27:56 -070064 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
pbrookac56dd42008-02-03 19:56:33 +000065}
66
Richard Henderson951c6302014-09-19 11:39:20 -070067static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
pbrookac56dd42008-02-03 19:56:33 +000068{
Richard Hendersonae8b75d2017-10-15 13:27:56 -070069 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
pbrooka7812ae2008-11-17 14:43:54 +000070}
71
Richard Henderson951c6302014-09-19 11:39:20 -070072static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
pbrooka7812ae2008-11-17 14:43:54 +000073{
Richard Hendersonae8b75d2017-10-15 13:27:56 -070074 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
pbrooka7812ae2008-11-17 14:43:54 +000075}
76
Richard Henderson951c6302014-09-19 11:39:20 -070077static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
pbrooka7812ae2008-11-17 14:43:54 +000078{
Richard Hendersonb7e8b172017-10-15 11:50:16 -070079 tcg_gen_op2(opc, a1, a2);
bellardc896fe22008-02-01 10:05:41 +000080}
81
Richard Henderson951c6302014-09-19 11:39:20 -070082static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
83 TCGv_i32 a2, TCGv_i32 a3)
pbrookbcb01262008-05-24 02:24:25 +000084{
Richard Hendersonae8b75d2017-10-15 13:27:56 -070085 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
pbrookbcb01262008-05-24 02:24:25 +000086}
87
Richard Henderson951c6302014-09-19 11:39:20 -070088static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
89 TCGv_i64 a2, TCGv_i64 a3)
bellardc896fe22008-02-01 10:05:41 +000090{
Richard Hendersonae8b75d2017-10-15 13:27:56 -070091 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
pbrookac56dd42008-02-03 19:56:33 +000092}
93
Richard Henderson951c6302014-09-19 11:39:20 -070094static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
95 TCGv_i32 a2, TCGArg a3)
pbrookac56dd42008-02-03 19:56:33 +000096{
Richard Hendersonae8b75d2017-10-15 13:27:56 -070097 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
pbrooka7812ae2008-11-17 14:43:54 +000098}
99
Richard Henderson951c6302014-09-19 11:39:20 -0700100static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
101 TCGv_i64 a2, TCGArg a3)
pbrooka7812ae2008-11-17 14:43:54 +0000102{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700103 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
pbrookac56dd42008-02-03 19:56:33 +0000104}
105
Richard Hendersona9751602010-03-19 11:12:29 -0700106static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
107 TCGv_ptr base, TCGArg offset)
pbrookac56dd42008-02-03 19:56:33 +0000108{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700109 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
pbrooka7812ae2008-11-17 14:43:54 +0000110}
111
Richard Hendersona9751602010-03-19 11:12:29 -0700112static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
113 TCGv_ptr base, TCGArg offset)
pbrooka7812ae2008-11-17 14:43:54 +0000114{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700115 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
pbrooka7812ae2008-11-17 14:43:54 +0000116}
117
Richard Henderson951c6302014-09-19 11:39:20 -0700118static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
119 TCGv_i32 a3, TCGv_i32 a4)
pbrooka7812ae2008-11-17 14:43:54 +0000120{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700121 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
122 tcgv_i32_arg(a3), tcgv_i32_arg(a4));
pbrooka7812ae2008-11-17 14:43:54 +0000123}
124
Richard Henderson951c6302014-09-19 11:39:20 -0700125static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
126 TCGv_i64 a3, TCGv_i64 a4)
pbrooka7812ae2008-11-17 14:43:54 +0000127{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700128 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
129 tcgv_i64_arg(a3), tcgv_i64_arg(a4));
pbrooka7812ae2008-11-17 14:43:54 +0000130}
131
Richard Henderson951c6302014-09-19 11:39:20 -0700132static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
133 TCGv_i32 a3, TCGArg a4)
pbrooka7812ae2008-11-17 14:43:54 +0000134{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700135 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
136 tcgv_i32_arg(a3), a4);
pbrookac56dd42008-02-03 19:56:33 +0000137}
138
Richard Henderson951c6302014-09-19 11:39:20 -0700139static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
140 TCGv_i64 a3, TCGArg a4)
pbrookac56dd42008-02-03 19:56:33 +0000141{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700142 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
143 tcgv_i64_arg(a3), a4);
pbrooka7812ae2008-11-17 14:43:54 +0000144}
145
Richard Henderson951c6302014-09-19 11:39:20 -0700146static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
147 TCGArg a3, TCGArg a4)
pbrooka7812ae2008-11-17 14:43:54 +0000148{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700149 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
bellardc896fe22008-02-01 10:05:41 +0000150}
151
Richard Henderson951c6302014-09-19 11:39:20 -0700152static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
153 TCGArg a3, TCGArg a4)
bellardc896fe22008-02-01 10:05:41 +0000154{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700155 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
pbrookac56dd42008-02-03 19:56:33 +0000156}
157
Richard Henderson951c6302014-09-19 11:39:20 -0700158static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
159 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
pbrookac56dd42008-02-03 19:56:33 +0000160{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700161 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
162 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
pbrooka7812ae2008-11-17 14:43:54 +0000163}
164
Richard Henderson951c6302014-09-19 11:39:20 -0700165static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
166 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
pbrooka7812ae2008-11-17 14:43:54 +0000167{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700168 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
169 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
pbrooka7812ae2008-11-17 14:43:54 +0000170}
171
Richard Henderson951c6302014-09-19 11:39:20 -0700172static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
173 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
pbrooka7812ae2008-11-17 14:43:54 +0000174{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700175 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
176 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
bellardc896fe22008-02-01 10:05:41 +0000177}
178
Richard Henderson951c6302014-09-19 11:39:20 -0700179static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
180 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
bellardc896fe22008-02-01 10:05:41 +0000181{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700182 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
183 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
pbrookac56dd42008-02-03 19:56:33 +0000184}
185
Richard Henderson951c6302014-09-19 11:39:20 -0700186static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
187 TCGv_i32 a3, TCGArg a4, TCGArg a5)
Richard Hendersonb7767f02011-01-10 19:23:42 -0800188{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700189 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
190 tcgv_i32_arg(a3), a4, a5);
Richard Hendersonb7767f02011-01-10 19:23:42 -0800191}
192
Richard Henderson951c6302014-09-19 11:39:20 -0700193static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
194 TCGv_i64 a3, TCGArg a4, TCGArg a5)
Richard Hendersonb7767f02011-01-10 19:23:42 -0800195{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700196 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
197 tcgv_i64_arg(a3), a4, a5);
Richard Hendersonb7767f02011-01-10 19:23:42 -0800198}
199
Richard Henderson951c6302014-09-19 11:39:20 -0700200static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
201 TCGv_i32 a3, TCGv_i32 a4,
202 TCGv_i32 a5, TCGv_i32 a6)
pbrookac56dd42008-02-03 19:56:33 +0000203{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700204 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
205 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
206 tcgv_i32_arg(a6));
pbrooka7812ae2008-11-17 14:43:54 +0000207}
208
Richard Henderson951c6302014-09-19 11:39:20 -0700209static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
210 TCGv_i64 a3, TCGv_i64 a4,
211 TCGv_i64 a5, TCGv_i64 a6)
pbrooka7812ae2008-11-17 14:43:54 +0000212{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700213 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
214 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
215 tcgv_i64_arg(a6));
pbrooka7812ae2008-11-17 14:43:54 +0000216}
217
Richard Henderson951c6302014-09-19 11:39:20 -0700218static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
219 TCGv_i32 a3, TCGv_i32 a4,
220 TCGv_i32 a5, TCGArg a6)
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800221{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700222 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
223 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800224}
225
Richard Henderson951c6302014-09-19 11:39:20 -0700226static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
227 TCGv_i64 a3, TCGv_i64 a4,
228 TCGv_i64 a5, TCGArg a6)
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800229{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700230 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
231 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800232}
233
Richard Henderson951c6302014-09-19 11:39:20 -0700234static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
235 TCGv_i32 a3, TCGv_i32 a4,
236 TCGArg a5, TCGArg a6)
pbrooka7812ae2008-11-17 14:43:54 +0000237{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700238 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
239 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
pbrooka7812ae2008-11-17 14:43:54 +0000240}
241
Richard Henderson951c6302014-09-19 11:39:20 -0700242static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
243 TCGv_i64 a3, TCGv_i64 a4,
244 TCGArg a5, TCGArg a6)
pbrooka7812ae2008-11-17 14:43:54 +0000245{
Richard Hendersonae8b75d2017-10-15 13:27:56 -0700246 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
247 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
bellardc896fe22008-02-01 10:05:41 +0000248}
249
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700250
Richard Henderson951c6302014-09-19 11:39:20 -0700251/* Generic ops. */
252
Richard Henderson42a268c2015-02-13 12:51:55 -0800253static inline void gen_set_label(TCGLabel *l)
bellardc896fe22008-02-01 10:05:41 +0000254{
Richard Hendersonb7e8b172017-10-15 11:50:16 -0700255 tcg_gen_op1(INDEX_op_set_label, label_arg(l));
bellardc896fe22008-02-01 10:05:41 +0000256}
257
Richard Henderson42a268c2015-02-13 12:51:55 -0800258static inline void tcg_gen_br(TCGLabel *l)
blueswir1fb50d412008-03-21 17:58:45 +0000259{
Richard Hendersonb7e8b172017-10-15 11:50:16 -0700260 tcg_gen_op1(INDEX_op_br, label_arg(l));
Richard Henderson951c6302014-09-19 11:39:20 -0700261}
262
Pranith Kumarf65e19b2016-07-14 16:20:13 -0400263void tcg_gen_mb(TCGBar);
264
Richard Henderson951c6302014-09-19 11:39:20 -0700265/* Helper calls. */
266
267/* 32 bit ops */
268
269void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
270void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
271void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
Richard Henderson474b2e82018-01-04 07:44:17 -0800272void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
Richard Henderson951c6302014-09-19 11:39:20 -0700273void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
274void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
Richard Henderson474b2e82018-01-04 07:44:17 -0800275void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
276void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
277void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
Richard Henderson951c6302014-09-19 11:39:20 -0700278void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
279void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
280void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
281void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
282void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
283void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
284void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
Richard Henderson0e28d002016-11-16 09:23:28 +0100288void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
291void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
Richard Henderson086920c2016-11-16 17:32:48 +0100292void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
Richard Hendersona768e4e2016-11-21 11:13:39 +0100293void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
Richard Henderson951c6302014-09-19 11:39:20 -0700294void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
295void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
296void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
297void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
298void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
299 unsigned int ofs, unsigned int len);
Richard Henderson07cc68d2016-10-17 13:21:31 -0700300void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
301 unsigned int ofs, unsigned int len);
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500302void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
303 unsigned int ofs, unsigned int len);
304void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
305 unsigned int ofs, unsigned int len);
Richard Henderson42a268c2015-02-13 12:51:55 -0800306void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
307void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
Richard Henderson951c6302014-09-19 11:39:20 -0700308void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
309 TCGv_i32 arg1, TCGv_i32 arg2);
310void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
311 TCGv_i32 arg1, int32_t arg2);
312void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
313 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
314void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
315 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
316void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
317 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
318void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
319void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
Richard Henderson5087abf2016-09-27 14:23:52 -0700320void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
Richard Henderson951c6302014-09-19 11:39:20 -0700321void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
322void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
323void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
324void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
325void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
326void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
327
328static inline void tcg_gen_discard_i32(TCGv_i32 arg)
329{
330 tcg_gen_op1_i32(INDEX_op_discard, arg);
blueswir1fb50d412008-03-21 17:58:45 +0000331}
332
pbrooka7812ae2008-11-17 14:43:54 +0000333static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +0000334{
Richard Henderson11f4e8f2017-10-19 20:27:27 -0700335 if (ret != arg) {
pbrooka7812ae2008-11-17 14:43:54 +0000336 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
Richard Henderson951c6302014-09-19 11:39:20 -0700337 }
bellardc896fe22008-02-01 10:05:41 +0000338}
339
pbrooka7812ae2008-11-17 14:43:54 +0000340static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
bellardc896fe22008-02-01 10:05:41 +0000341{
pbrooka7812ae2008-11-17 14:43:54 +0000342 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
bellardc896fe22008-02-01 10:05:41 +0000343}
344
Richard Henderson951c6302014-09-19 11:39:20 -0700345static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
346 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000347{
pbrooka7812ae2008-11-17 14:43:54 +0000348 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000349}
350
Richard Henderson951c6302014-09-19 11:39:20 -0700351static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
352 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000353{
pbrooka7812ae2008-11-17 14:43:54 +0000354 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000355}
356
Richard Henderson951c6302014-09-19 11:39:20 -0700357static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
358 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000359{
pbrooka7812ae2008-11-17 14:43:54 +0000360 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000361}
362
Richard Henderson951c6302014-09-19 11:39:20 -0700363static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
364 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000365{
pbrooka7812ae2008-11-17 14:43:54 +0000366 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000367}
368
Richard Henderson951c6302014-09-19 11:39:20 -0700369static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
370 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000371{
pbrooka7812ae2008-11-17 14:43:54 +0000372 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000373}
374
Richard Henderson951c6302014-09-19 11:39:20 -0700375static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
376 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000377{
pbrooka7812ae2008-11-17 14:43:54 +0000378 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000379}
380
Richard Henderson951c6302014-09-19 11:39:20 -0700381static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
382 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000383{
pbrooka7812ae2008-11-17 14:43:54 +0000384 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000385}
386
Richard Henderson951c6302014-09-19 11:39:20 -0700387static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
388 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000389{
pbrooka7812ae2008-11-17 14:43:54 +0000390 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000391}
392
pbrooka7812ae2008-11-17 14:43:54 +0000393static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000394{
pbrooka7812ae2008-11-17 14:43:54 +0000395 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000396}
397
pbrooka7812ae2008-11-17 14:43:54 +0000398static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000399{
pbrooka7812ae2008-11-17 14:43:54 +0000400 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000401}
402
pbrooka7812ae2008-11-17 14:43:54 +0000403static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000404{
Richard Henderson951c6302014-09-19 11:39:20 -0700405 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000406}
407
pbrooka7812ae2008-11-17 14:43:54 +0000408static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000409{
Richard Henderson951c6302014-09-19 11:39:20 -0700410 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000411}
412
pbrooka7812ae2008-11-17 14:43:54 +0000413static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000414{
Richard Henderson951c6302014-09-19 11:39:20 -0700415 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000416}
417
pbrooka7812ae2008-11-17 14:43:54 +0000418static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000419{
pbrooka7812ae2008-11-17 14:43:54 +0000420 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000421}
422
pbrooka7812ae2008-11-17 14:43:54 +0000423static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000424{
pbrooka7812ae2008-11-17 14:43:54 +0000425 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000426}
427
pbrooka7812ae2008-11-17 14:43:54 +0000428static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000429{
pbrooka7812ae2008-11-17 14:43:54 +0000430 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000431}
432
pbrooka7812ae2008-11-17 14:43:54 +0000433static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
bellardc896fe22008-02-01 10:05:41 +0000434{
pbrooka7812ae2008-11-17 14:43:54 +0000435 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000436}
437
Richard Henderson951c6302014-09-19 11:39:20 -0700438static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
thsf730fd22008-05-04 08:14:08 +0000439{
Richard Henderson951c6302014-09-19 11:39:20 -0700440 if (TCG_TARGET_HAS_neg_i32) {
441 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700442 } else {
Richard Henderson951c6302014-09-19 11:39:20 -0700443 tcg_gen_subfi_i32(ret, 0, arg);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700444 }
bellardc896fe22008-02-01 10:05:41 +0000445}
446
Richard Henderson951c6302014-09-19 11:39:20 -0700447static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
bellardc896fe22008-02-01 10:05:41 +0000448{
Richard Henderson951c6302014-09-19 11:39:20 -0700449 if (TCG_TARGET_HAS_not_i32) {
450 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700451 } else {
Richard Henderson951c6302014-09-19 11:39:20 -0700452 tcg_gen_xori_i32(ret, arg, -1);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700453 }
bellardc896fe22008-02-01 10:05:41 +0000454}
455
Richard Henderson951c6302014-09-19 11:39:20 -0700456/* 64 bit ops */
bellardc896fe22008-02-01 10:05:41 +0000457
Richard Henderson951c6302014-09-19 11:39:20 -0700458void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
459void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
460void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
Richard Henderson474b2e82018-01-04 07:44:17 -0800461void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
Richard Henderson951c6302014-09-19 11:39:20 -0700462void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
463void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
Richard Henderson474b2e82018-01-04 07:44:17 -0800464void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
465void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
466void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
Richard Henderson951c6302014-09-19 11:39:20 -0700467void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
468void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
469void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
470void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
471void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
472void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
473void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
474void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
475void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
476void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
Richard Henderson0e28d002016-11-16 09:23:28 +0100477void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
478void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
479void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
480void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
Richard Henderson086920c2016-11-16 17:32:48 +0100481void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
Richard Hendersona768e4e2016-11-21 11:13:39 +0100482void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
Richard Henderson951c6302014-09-19 11:39:20 -0700483void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
484void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
485void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
486void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
487void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
488 unsigned int ofs, unsigned int len);
Richard Henderson07cc68d2016-10-17 13:21:31 -0700489void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
490 unsigned int ofs, unsigned int len);
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500491void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
492 unsigned int ofs, unsigned int len);
493void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
494 unsigned int ofs, unsigned int len);
Richard Henderson42a268c2015-02-13 12:51:55 -0800495void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
496void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
Richard Henderson951c6302014-09-19 11:39:20 -0700497void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
498 TCGv_i64 arg1, TCGv_i64 arg2);
499void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
500 TCGv_i64 arg1, int64_t arg2);
501void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
502 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
503void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
504 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
505void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
506 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
507void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
508void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
Richard Henderson5087abf2016-09-27 14:23:52 -0700509void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
Richard Henderson951c6302014-09-19 11:39:20 -0700510void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
511void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
512void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
513void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
514void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
515void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
516void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
517void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
518void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
519void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
bellardc896fe22008-02-01 10:05:41 +0000520
Richard Henderson951c6302014-09-19 11:39:20 -0700521#if TCG_TARGET_REG_BITS == 64
522static inline void tcg_gen_discard_i64(TCGv_i64 arg)
523{
524 tcg_gen_op1_i64(INDEX_op_discard, arg);
525}
bellardc896fe22008-02-01 10:05:41 +0000526
pbrooka7812ae2008-11-17 14:43:54 +0000527static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
bellardc896fe22008-02-01 10:05:41 +0000528{
Richard Henderson11f4e8f2017-10-19 20:27:27 -0700529 if (ret != arg) {
pbrooka7812ae2008-11-17 14:43:54 +0000530 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
Richard Henderson951c6302014-09-19 11:39:20 -0700531 }
bellardc896fe22008-02-01 10:05:41 +0000532}
533
pbrooka7812ae2008-11-17 14:43:54 +0000534static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
bellardc896fe22008-02-01 10:05:41 +0000535{
pbrooka7812ae2008-11-17 14:43:54 +0000536 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
bellardc896fe22008-02-01 10:05:41 +0000537}
538
Peter Maydell6bd4b082011-05-27 13:12:12 +0100539static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000540 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000541{
pbrooka7812ae2008-11-17 14:43:54 +0000542 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000543}
544
Peter Maydell6bd4b082011-05-27 13:12:12 +0100545static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000546 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000547{
pbrooka7812ae2008-11-17 14:43:54 +0000548 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000549}
550
Peter Maydell6bd4b082011-05-27 13:12:12 +0100551static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000552 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000553{
pbrooka7812ae2008-11-17 14:43:54 +0000554 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000555}
556
Peter Maydell6bd4b082011-05-27 13:12:12 +0100557static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000558 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000559{
pbrooka7812ae2008-11-17 14:43:54 +0000560 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000561}
562
Peter Maydell6bd4b082011-05-27 13:12:12 +0100563static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000564 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000565{
pbrooka7812ae2008-11-17 14:43:54 +0000566 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000567}
568
Peter Maydell6bd4b082011-05-27 13:12:12 +0100569static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000570 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000571{
pbrooka7812ae2008-11-17 14:43:54 +0000572 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000573}
574
Richard Henderson951c6302014-09-19 11:39:20 -0700575static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
576 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000577{
pbrooka7812ae2008-11-17 14:43:54 +0000578 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000579}
580
Peter Maydell6bd4b082011-05-27 13:12:12 +0100581static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000582 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000583{
pbrooka7812ae2008-11-17 14:43:54 +0000584 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000585}
586
Peter Maydell6bd4b082011-05-27 13:12:12 +0100587static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000588 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000589{
pbrooka7812ae2008-11-17 14:43:54 +0000590 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000591}
592
Peter Maydell6bd4b082011-05-27 13:12:12 +0100593static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
pbrookac56dd42008-02-03 19:56:33 +0000594 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000595{
pbrooka7812ae2008-11-17 14:43:54 +0000596 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000597}
598
Richard Henderson951c6302014-09-19 11:39:20 -0700599static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
600 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000601{
pbrooka7812ae2008-11-17 14:43:54 +0000602 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000603}
604
pbrooka7812ae2008-11-17 14:43:54 +0000605static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000606{
pbrooka7812ae2008-11-17 14:43:54 +0000607 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000608}
609
pbrooka7812ae2008-11-17 14:43:54 +0000610static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000611{
pbrooka7812ae2008-11-17 14:43:54 +0000612 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000613}
614
pbrooka7812ae2008-11-17 14:43:54 +0000615static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000616{
Richard Henderson951c6302014-09-19 11:39:20 -0700617 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000618}
619
pbrooka7812ae2008-11-17 14:43:54 +0000620static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000621{
Richard Henderson951c6302014-09-19 11:39:20 -0700622 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000623}
624
pbrooka7812ae2008-11-17 14:43:54 +0000625static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000626{
Richard Henderson951c6302014-09-19 11:39:20 -0700627 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000628}
629
pbrooka7812ae2008-11-17 14:43:54 +0000630static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000631{
pbrooka7812ae2008-11-17 14:43:54 +0000632 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000633}
634
pbrooka7812ae2008-11-17 14:43:54 +0000635static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000636{
pbrooka7812ae2008-11-17 14:43:54 +0000637 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000638}
639
pbrooka7812ae2008-11-17 14:43:54 +0000640static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000641{
pbrooka7812ae2008-11-17 14:43:54 +0000642 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000643}
644
pbrooka7812ae2008-11-17 14:43:54 +0000645static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000646{
pbrooka7812ae2008-11-17 14:43:54 +0000647 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
bellardc896fe22008-02-01 10:05:41 +0000648}
Richard Henderson951c6302014-09-19 11:39:20 -0700649#else /* TCG_TARGET_REG_BITS == 32 */
650static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
651 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000652{
Richard Henderson951c6302014-09-19 11:39:20 -0700653 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000654}
655
Richard Henderson951c6302014-09-19 11:39:20 -0700656static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
657 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000658{
Richard Henderson951c6302014-09-19 11:39:20 -0700659 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000660}
661
Richard Henderson951c6302014-09-19 11:39:20 -0700662static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
663 tcg_target_long offset)
bellardc896fe22008-02-01 10:05:41 +0000664{
Richard Henderson951c6302014-09-19 11:39:20 -0700665 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
bellardc896fe22008-02-01 10:05:41 +0000666}
667
Richard Henderson951c6302014-09-19 11:39:20 -0700668static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
bellardc896fe22008-02-01 10:05:41 +0000669{
Richard Henderson951c6302014-09-19 11:39:20 -0700670 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
671 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
aurel3263597062008-11-02 08:22:54 +0000672}
673
Richard Henderson951c6302014-09-19 11:39:20 -0700674static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
aurel3200457342008-11-02 08:23:04 +0000675{
Richard Henderson951c6302014-09-19 11:39:20 -0700676 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
677 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
aurel3200457342008-11-02 08:23:04 +0000678}
679
Richard Henderson951c6302014-09-19 11:39:20 -0700680void tcg_gen_discard_i64(TCGv_i64 arg);
681void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
682void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
683void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
684void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
685void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
686void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
687void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
688void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
689void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
690void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
691void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
692void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
693void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
694void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
695void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
696void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
697void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
698#endif /* TCG_TARGET_REG_BITS */
pbrook390efc52008-05-11 14:35:37 +0000699
pbrooka7812ae2008-11-17 14:43:54 +0000700static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
pbrook390efc52008-05-11 14:35:37 +0000701{
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700702 if (TCG_TARGET_HAS_neg_i64) {
703 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
704 } else {
Richard Henderson951c6302014-09-19 11:39:20 -0700705 tcg_gen_subfi_i64(ret, 0, arg);
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700706 }
pbrook390efc52008-05-11 14:35:37 +0000707}
708
Richard Henderson951c6302014-09-19 11:39:20 -0700709/* Size changing operations. */
710
711void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
712void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
713void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
Richard Henderson609ad702015-07-24 07:16:00 -0700714void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
715void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
Richard Henderson951c6302014-09-19 11:39:20 -0700716void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
717void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
718
719static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
bellard0b6ce4c2008-05-17 12:40:44 +0000720{
Richard Henderson951c6302014-09-19 11:39:20 -0700721 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
Richard Henderson77276f62012-09-21 17:18:13 -0700722}
723
Richard Henderson951c6302014-09-19 11:39:20 -0700724/* QEMU specific operations. */
Richard Henderson3c51a982013-02-19 23:51:54 -0800725
bellardc896fe22008-02-01 10:05:41 +0000726#ifndef TARGET_LONG_BITS
727#error must include QEMU headers
728#endif
729
Richard Henderson9aef40e2015-08-30 09:21:33 -0700730#if TARGET_INSN_START_WORDS == 1
731# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
732static inline void tcg_gen_insn_start(target_ulong pc)
Richard Henderson951c6302014-09-19 11:39:20 -0700733{
Richard Hendersonb7e8b172017-10-15 11:50:16 -0700734 tcg_gen_op1(INDEX_op_insn_start, pc);
Richard Henderson951c6302014-09-19 11:39:20 -0700735}
Richard Henderson9aef40e2015-08-30 09:21:33 -0700736# else
737static inline void tcg_gen_insn_start(target_ulong pc)
738{
Richard Hendersonb7e8b172017-10-15 11:50:16 -0700739 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
Richard Henderson9aef40e2015-08-30 09:21:33 -0700740}
741# endif
742#elif TARGET_INSN_START_WORDS == 2
743# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
744static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
745{
Richard Hendersonb7e8b172017-10-15 11:50:16 -0700746 tcg_gen_op2(INDEX_op_insn_start, pc, a1);
Richard Henderson9aef40e2015-08-30 09:21:33 -0700747}
748# else
749static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
750{
Richard Hendersonb7e8b172017-10-15 11:50:16 -0700751 tcg_gen_op4(INDEX_op_insn_start,
Richard Henderson9aef40e2015-08-30 09:21:33 -0700752 (uint32_t)pc, (uint32_t)(pc >> 32),
753 (uint32_t)a1, (uint32_t)(a1 >> 32));
754}
755# endif
756#elif TARGET_INSN_START_WORDS == 3
757# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
758static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
759 target_ulong a2)
760{
Richard Hendersonb7e8b172017-10-15 11:50:16 -0700761 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
Richard Henderson9aef40e2015-08-30 09:21:33 -0700762}
763# else
764static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
765 target_ulong a2)
766{
Richard Hendersonb7e8b172017-10-15 11:50:16 -0700767 tcg_gen_op6(INDEX_op_insn_start,
Richard Henderson9aef40e2015-08-30 09:21:33 -0700768 (uint32_t)pc, (uint32_t)(pc >> 32),
769 (uint32_t)a1, (uint32_t)(a1 >> 32),
770 (uint32_t)a2, (uint32_t)(a2 >> 32));
771}
772# endif
773#else
774# error "Unhandled number of operands to insn_start"
775#endif
Richard Henderson951c6302014-09-19 11:39:20 -0700776
777static inline void tcg_gen_exit_tb(uintptr_t val)
778{
779 tcg_gen_op1i(INDEX_op_exit_tb, val);
780}
781
Sergey Fedorov5b053a42016-04-08 19:48:12 +0300782/**
783 * tcg_gen_goto_tb() - output goto_tb TCG operation
784 * @idx: Direct jump slot index (0 or 1)
785 *
786 * See tcg/README for more info about this TCG operation.
787 *
Sergey Fedorov90aa39a2016-04-09 01:00:23 +0300788 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
789 * the pages this TB resides in because we don't take care of direct jumps when
790 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
791 * static address translation, so the destination address is always valid, TBs
792 * are always invalidated properly, and direct jumps are reset when mapping
793 * changes.
Sergey Fedorov5b053a42016-04-08 19:48:12 +0300794 */
Richard Henderson951c6302014-09-19 11:39:20 -0700795void tcg_gen_goto_tb(unsigned idx);
796
Emilio G. Cotacedbcb02017-04-26 23:29:14 -0400797/**
Emilio G. Cota7f116362017-07-11 17:06:48 -0400798 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
Emilio G. Cotacedbcb02017-04-26 23:29:14 -0400799 * @addr: Guest address of the target TB
800 *
801 * If the TB is not valid, jump to the epilogue.
802 *
803 * This operation is optional. If the TCG backend does not implement goto_ptr,
804 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
805 */
Emilio G. Cota7f116362017-07-11 17:06:48 -0400806void tcg_gen_lookup_and_goto_ptr(void);
Emilio G. Cotacedbcb02017-04-26 23:29:14 -0400807
pbrooka7812ae2008-11-17 14:43:54 +0000808#if TARGET_LONG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +0000809#define tcg_temp_new() tcg_temp_new_i32()
810#define tcg_global_reg_new tcg_global_reg_new_i32
811#define tcg_global_mem_new tcg_global_mem_new_i32
aurel32df9247b2009-01-01 14:09:05 +0000812#define tcg_temp_local_new() tcg_temp_local_new_i32()
pbrooka7812ae2008-11-17 14:43:54 +0000813#define tcg_temp_free tcg_temp_free_i32
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700814#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
815#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
pbrooka7812ae2008-11-17 14:43:54 +0000816#else
pbrooka7812ae2008-11-17 14:43:54 +0000817#define tcg_temp_new() tcg_temp_new_i64()
818#define tcg_global_reg_new tcg_global_reg_new_i64
819#define tcg_global_mem_new tcg_global_mem_new_i64
aurel32df9247b2009-01-01 14:09:05 +0000820#define tcg_temp_local_new() tcg_temp_local_new_i64()
pbrooka7812ae2008-11-17 14:43:54 +0000821#define tcg_temp_free tcg_temp_free_i64
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700822#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
823#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
pbrooka7812ae2008-11-17 14:43:54 +0000824#endif
825
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700826void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
827void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
828void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
829void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
830
pbrookac56dd42008-02-03 19:56:33 +0000831static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000832{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700833 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
bellardc896fe22008-02-01 10:05:41 +0000834}
835
pbrookac56dd42008-02-03 19:56:33 +0000836static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000837{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700838 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
bellardc896fe22008-02-01 10:05:41 +0000839}
840
pbrookac56dd42008-02-03 19:56:33 +0000841static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000842{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700843 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
bellardc896fe22008-02-01 10:05:41 +0000844}
845
pbrookac56dd42008-02-03 19:56:33 +0000846static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000847{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700848 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
bellardc896fe22008-02-01 10:05:41 +0000849}
850
pbrookac56dd42008-02-03 19:56:33 +0000851static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000852{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700853 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
bellardc896fe22008-02-01 10:05:41 +0000854}
855
pbrookac56dd42008-02-03 19:56:33 +0000856static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000857{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700858 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
bellardc896fe22008-02-01 10:05:41 +0000859}
860
pbrooka7812ae2008-11-17 14:43:54 +0000861static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000862{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700863 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
bellardc896fe22008-02-01 10:05:41 +0000864}
865
pbrookac56dd42008-02-03 19:56:33 +0000866static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000867{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700868 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
bellardc896fe22008-02-01 10:05:41 +0000869}
870
pbrookac56dd42008-02-03 19:56:33 +0000871static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000872{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700873 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
bellardc896fe22008-02-01 10:05:41 +0000874}
875
pbrookac56dd42008-02-03 19:56:33 +0000876static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000877{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700878 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
bellardc896fe22008-02-01 10:05:41 +0000879}
880
pbrooka7812ae2008-11-17 14:43:54 +0000881static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
bellardc896fe22008-02-01 10:05:41 +0000882{
Richard Hendersonf713d6a2013-09-04 08:11:05 -0700883 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
bellardc896fe22008-02-01 10:05:41 +0000884}
885
Richard Hendersonc482cb12016-06-28 11:37:27 -0700886void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
887 TCGArg, TCGMemOp);
888void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
889 TCGArg, TCGMemOp);
890
891void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
892void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
893void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
894void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
895void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
896void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
897void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
898void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
899void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
900void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
901void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
902void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
903void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
904void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
905void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
906void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
907void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
908void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
909
Richard Hendersond2fd7452017-09-14 13:53:46 -0700910void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
911void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
912void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
913void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
914void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
915void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
916void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
Richard Hendersondb432672017-09-15 14:11:45 -0700917void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
Richard Hendersond2fd7452017-09-14 13:53:46 -0700918void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
919void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
Richard Henderson37740302017-11-21 10:11:14 +0100920void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
Richard Hendersond2fd7452017-09-14 13:53:46 -0700921void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
922void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
923void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
924void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
925void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
926void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
927void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
928
Richard Hendersond0ec9792017-11-17 14:35:11 +0100929void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
930void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
931void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
932
Richard Henderson212be172017-11-17 20:47:42 +0100933void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
934 TCGv_vec a, TCGv_vec b);
935
Richard Hendersond2fd7452017-09-14 13:53:46 -0700936void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
937void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
938void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
939
blueswir1f8422f52008-02-24 07:45:43 +0000940#if TARGET_LONG_BITS == 64
blueswir1f8422f52008-02-24 07:45:43 +0000941#define tcg_gen_movi_tl tcg_gen_movi_i64
942#define tcg_gen_mov_tl tcg_gen_mov_i64
943#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
944#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
945#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
946#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
947#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
948#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
949#define tcg_gen_ld_tl tcg_gen_ld_i64
950#define tcg_gen_st8_tl tcg_gen_st8_i64
951#define tcg_gen_st16_tl tcg_gen_st16_i64
952#define tcg_gen_st32_tl tcg_gen_st32_i64
953#define tcg_gen_st_tl tcg_gen_st_i64
954#define tcg_gen_add_tl tcg_gen_add_i64
955#define tcg_gen_addi_tl tcg_gen_addi_i64
956#define tcg_gen_sub_tl tcg_gen_sub_i64
pbrook390efc52008-05-11 14:35:37 +0000957#define tcg_gen_neg_tl tcg_gen_neg_i64
pbrook10460c82008-11-02 13:26:16 +0000958#define tcg_gen_subfi_tl tcg_gen_subfi_i64
blueswir1f8422f52008-02-24 07:45:43 +0000959#define tcg_gen_subi_tl tcg_gen_subi_i64
960#define tcg_gen_and_tl tcg_gen_and_i64
961#define tcg_gen_andi_tl tcg_gen_andi_i64
962#define tcg_gen_or_tl tcg_gen_or_i64
963#define tcg_gen_ori_tl tcg_gen_ori_i64
964#define tcg_gen_xor_tl tcg_gen_xor_i64
965#define tcg_gen_xori_tl tcg_gen_xori_i64
bellard0b6ce4c2008-05-17 12:40:44 +0000966#define tcg_gen_not_tl tcg_gen_not_i64
blueswir1f8422f52008-02-24 07:45:43 +0000967#define tcg_gen_shl_tl tcg_gen_shl_i64
968#define tcg_gen_shli_tl tcg_gen_shli_i64
969#define tcg_gen_shr_tl tcg_gen_shr_i64
970#define tcg_gen_shri_tl tcg_gen_shri_i64
971#define tcg_gen_sar_tl tcg_gen_sar_i64
972#define tcg_gen_sari_tl tcg_gen_sari_i64
blueswir10cf767d2008-03-02 18:20:59 +0000973#define tcg_gen_brcond_tl tcg_gen_brcond_i64
pbrookcb636692008-05-24 02:22:00 +0000974#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
Richard Hendersonbe210ac2010-01-07 10:13:31 -0800975#define tcg_gen_setcond_tl tcg_gen_setcond_i64
Aurelien Jarnoadd1e7e2010-02-08 12:06:05 +0100976#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
thsf730fd22008-05-04 08:14:08 +0000977#define tcg_gen_mul_tl tcg_gen_mul_i64
978#define tcg_gen_muli_tl tcg_gen_muli_i64
aurel32ab364212009-03-29 01:19:22 +0000979#define tcg_gen_div_tl tcg_gen_div_i64
980#define tcg_gen_rem_tl tcg_gen_rem_i64
aurel32864951a2009-03-29 14:08:54 +0000981#define tcg_gen_divu_tl tcg_gen_divu_i64
982#define tcg_gen_remu_tl tcg_gen_remu_i64
blueswir1a768e4b2008-03-16 19:16:37 +0000983#define tcg_gen_discard_tl tcg_gen_discard_i64
Richard Hendersonecc7b3a2015-07-24 11:49:53 -0700984#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
blueswir1e4290732008-03-22 08:39:04 +0000985#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
986#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
987#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
988#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
989#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
bellard0b6ce4c2008-05-17 12:40:44 +0000990#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
991#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
992#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
993#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
994#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
995#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
aurel32911d79b2009-03-13 09:35:19 +0000996#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
997#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
998#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
blueswir1945ca822008-09-21 18:32:28 +0000999#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
Richard Henderson3c51a982013-02-19 23:51:54 -08001000#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
aurel32f24cb332008-10-21 11:28:59 +00001001#define tcg_gen_andc_tl tcg_gen_andc_i64
1002#define tcg_gen_eqv_tl tcg_gen_eqv_i64
1003#define tcg_gen_nand_tl tcg_gen_nand_i64
1004#define tcg_gen_nor_tl tcg_gen_nor_i64
1005#define tcg_gen_orc_tl tcg_gen_orc_i64
Richard Henderson0e28d002016-11-16 09:23:28 +01001006#define tcg_gen_clz_tl tcg_gen_clz_i64
1007#define tcg_gen_ctz_tl tcg_gen_ctz_i64
1008#define tcg_gen_clzi_tl tcg_gen_clzi_i64
1009#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
Richard Henderson086920c2016-11-16 17:32:48 +01001010#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
Richard Hendersona768e4e2016-11-21 11:13:39 +01001011#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
aurel3215824572008-11-03 07:08:36 +00001012#define tcg_gen_rotl_tl tcg_gen_rotl_i64
1013#define tcg_gen_rotli_tl tcg_gen_rotli_i64
1014#define tcg_gen_rotr_tl tcg_gen_rotr_i64
1015#define tcg_gen_rotri_tl tcg_gen_rotri_i64
Richard Hendersonb7767f02011-01-10 19:23:42 -08001016#define tcg_gen_deposit_tl tcg_gen_deposit_i64
Richard Henderson07cc68d2016-10-17 13:21:31 -07001017#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
Richard Henderson7ec8bab2016-10-14 12:04:32 -05001018#define tcg_gen_extract_tl tcg_gen_extract_i64
1019#define tcg_gen_sextract_tl tcg_gen_sextract_i64
blueswir1a98824a2008-03-13 20:46:42 +00001020#define tcg_const_tl tcg_const_i64
aurel32bdffd4a2008-10-21 11:30:45 +00001021#define tcg_const_local_tl tcg_const_local_i64
Richard Hendersonffc5ea02012-09-21 10:13:34 -07001022#define tcg_gen_movcond_tl tcg_gen_movcond_i64
Richard Hendersonf6953a72013-02-19 23:51:56 -08001023#define tcg_gen_add2_tl tcg_gen_add2_i64
1024#define tcg_gen_sub2_tl tcg_gen_sub2_i64
Richard Henderson696a8be2013-02-19 23:51:55 -08001025#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1026#define tcg_gen_muls2_tl tcg_gen_muls2_i64
Richard Henderson5087abf2016-09-27 14:23:52 -07001027#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
Richard Hendersonc482cb12016-06-28 11:37:27 -07001028#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1029#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1030#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1031#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1032#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1033#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
1034#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1035#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1036#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1037#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
Richard Hendersond2fd7452017-09-14 13:53:46 -07001038#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
blueswir1f8422f52008-02-24 07:45:43 +00001039#else
blueswir1f8422f52008-02-24 07:45:43 +00001040#define tcg_gen_movi_tl tcg_gen_movi_i32
1041#define tcg_gen_mov_tl tcg_gen_mov_i32
1042#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1043#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1044#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1045#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1046#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1047#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1048#define tcg_gen_ld_tl tcg_gen_ld_i32
1049#define tcg_gen_st8_tl tcg_gen_st8_i32
1050#define tcg_gen_st16_tl tcg_gen_st16_i32
1051#define tcg_gen_st32_tl tcg_gen_st_i32
1052#define tcg_gen_st_tl tcg_gen_st_i32
1053#define tcg_gen_add_tl tcg_gen_add_i32
1054#define tcg_gen_addi_tl tcg_gen_addi_i32
1055#define tcg_gen_sub_tl tcg_gen_sub_i32
pbrook390efc52008-05-11 14:35:37 +00001056#define tcg_gen_neg_tl tcg_gen_neg_i32
aurel3200457342008-11-02 08:23:04 +00001057#define tcg_gen_subfi_tl tcg_gen_subfi_i32
blueswir1f8422f52008-02-24 07:45:43 +00001058#define tcg_gen_subi_tl tcg_gen_subi_i32
1059#define tcg_gen_and_tl tcg_gen_and_i32
1060#define tcg_gen_andi_tl tcg_gen_andi_i32
1061#define tcg_gen_or_tl tcg_gen_or_i32
1062#define tcg_gen_ori_tl tcg_gen_ori_i32
1063#define tcg_gen_xor_tl tcg_gen_xor_i32
1064#define tcg_gen_xori_tl tcg_gen_xori_i32
bellard0b6ce4c2008-05-17 12:40:44 +00001065#define tcg_gen_not_tl tcg_gen_not_i32
blueswir1f8422f52008-02-24 07:45:43 +00001066#define tcg_gen_shl_tl tcg_gen_shl_i32
1067#define tcg_gen_shli_tl tcg_gen_shli_i32
1068#define tcg_gen_shr_tl tcg_gen_shr_i32
1069#define tcg_gen_shri_tl tcg_gen_shri_i32
1070#define tcg_gen_sar_tl tcg_gen_sar_i32
1071#define tcg_gen_sari_tl tcg_gen_sari_i32
blueswir10cf767d2008-03-02 18:20:59 +00001072#define tcg_gen_brcond_tl tcg_gen_brcond_i32
pbrookcb636692008-05-24 02:22:00 +00001073#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
Richard Hendersonbe210ac2010-01-07 10:13:31 -08001074#define tcg_gen_setcond_tl tcg_gen_setcond_i32
Aurelien Jarnoadd1e7e2010-02-08 12:06:05 +01001075#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
thsf730fd22008-05-04 08:14:08 +00001076#define tcg_gen_mul_tl tcg_gen_mul_i32
1077#define tcg_gen_muli_tl tcg_gen_muli_i32
aurel32ab364212009-03-29 01:19:22 +00001078#define tcg_gen_div_tl tcg_gen_div_i32
1079#define tcg_gen_rem_tl tcg_gen_rem_i32
aurel32864951a2009-03-29 14:08:54 +00001080#define tcg_gen_divu_tl tcg_gen_divu_i32
1081#define tcg_gen_remu_tl tcg_gen_remu_i32
blueswir1a768e4b2008-03-16 19:16:37 +00001082#define tcg_gen_discard_tl tcg_gen_discard_i32
blueswir1e4290732008-03-22 08:39:04 +00001083#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
Richard Hendersonecc7b3a2015-07-24 11:49:53 -07001084#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
blueswir1e4290732008-03-22 08:39:04 +00001085#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1086#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1087#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1088#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
bellard0b6ce4c2008-05-17 12:40:44 +00001089#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1090#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1091#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1092#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1093#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1094#define tcg_gen_ext32s_tl tcg_gen_mov_i32
aurel32911d79b2009-03-13 09:35:19 +00001095#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1096#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
blueswir1945ca822008-09-21 18:32:28 +00001097#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
Alexander Grafe3eb9802014-06-04 23:09:11 +02001098#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
aurel32f24cb332008-10-21 11:28:59 +00001099#define tcg_gen_andc_tl tcg_gen_andc_i32
1100#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1101#define tcg_gen_nand_tl tcg_gen_nand_i32
1102#define tcg_gen_nor_tl tcg_gen_nor_i32
1103#define tcg_gen_orc_tl tcg_gen_orc_i32
Richard Henderson0e28d002016-11-16 09:23:28 +01001104#define tcg_gen_clz_tl tcg_gen_clz_i32
1105#define tcg_gen_ctz_tl tcg_gen_ctz_i32
1106#define tcg_gen_clzi_tl tcg_gen_clzi_i32
1107#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
Richard Henderson086920c2016-11-16 17:32:48 +01001108#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
Richard Hendersona768e4e2016-11-21 11:13:39 +01001109#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
aurel3215824572008-11-03 07:08:36 +00001110#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1111#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1112#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1113#define tcg_gen_rotri_tl tcg_gen_rotri_i32
Richard Hendersonb7767f02011-01-10 19:23:42 -08001114#define tcg_gen_deposit_tl tcg_gen_deposit_i32
Richard Henderson07cc68d2016-10-17 13:21:31 -07001115#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
Richard Henderson7ec8bab2016-10-14 12:04:32 -05001116#define tcg_gen_extract_tl tcg_gen_extract_i32
1117#define tcg_gen_sextract_tl tcg_gen_sextract_i32
blueswir1a98824a2008-03-13 20:46:42 +00001118#define tcg_const_tl tcg_const_i32
aurel32bdffd4a2008-10-21 11:30:45 +00001119#define tcg_const_local_tl tcg_const_local_i32
Richard Hendersonffc5ea02012-09-21 10:13:34 -07001120#define tcg_gen_movcond_tl tcg_gen_movcond_i32
Richard Hendersonf6953a72013-02-19 23:51:56 -08001121#define tcg_gen_add2_tl tcg_gen_add2_i32
1122#define tcg_gen_sub2_tl tcg_gen_sub2_i32
Richard Henderson696a8be2013-02-19 23:51:55 -08001123#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1124#define tcg_gen_muls2_tl tcg_gen_muls2_i32
Richard Henderson5087abf2016-09-27 14:23:52 -07001125#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
Richard Hendersonc482cb12016-06-28 11:37:27 -07001126#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1127#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1128#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1129#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1130#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1131#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
1132#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1133#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1134#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1135#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
Richard Hendersond2fd7452017-09-14 13:53:46 -07001136#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
blueswir1f8422f52008-02-24 07:45:43 +00001137#endif
pbrook6ddbc6e2008-03-31 03:46:33 +00001138
Richard Henderson71b92692013-09-09 08:26:49 -07001139#if UINTPTR_MAX == UINT32_MAX
Richard Hendersonf713d6a2013-09-04 08:11:05 -07001140# define tcg_gen_ld_ptr(R, A, O) \
1141 tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
1142# define tcg_gen_discard_ptr(A) \
1143 tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
1144# define tcg_gen_add_ptr(R, A, B) \
1145 tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
1146# define tcg_gen_addi_ptr(R, A, B) \
1147 tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
1148# define tcg_gen_ext_i32_ptr(R, A) \
1149 tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
1150#else
1151# define tcg_gen_ld_ptr(R, A, O) \
1152 tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
1153# define tcg_gen_discard_ptr(A) \
1154 tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
1155# define tcg_gen_add_ptr(R, A, B) \
1156 tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
1157# define tcg_gen_addi_ptr(R, A, B) \
1158 tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
1159# define tcg_gen_ext_i32_ptr(R, A) \
1160 tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
Richard Henderson71b92692013-09-09 08:26:49 -07001161#endif /* UINTPTR_MAX == UINT32_MAX */