bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2008 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 24 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 25 | #include "tcg.h" |
Richard Henderson | 944eea9 | 2014-04-07 23:08:47 -0700 | [diff] [blame] | 26 | #include "exec/helper-proto.h" |
Richard Henderson | c017230 | 2014-04-07 23:36:08 -0700 | [diff] [blame] | 27 | #include "exec/helper-gen.h" |
| 28 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 29 | /* Basic output routines. Not for general consumption. */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 30 | |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 31 | void tcg_gen_op1(TCGOpcode, TCGArg); |
| 32 | void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); |
| 33 | void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); |
| 34 | void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); |
| 35 | void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); |
| 36 | void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 37 | |
Richard Henderson | d2fd745 | 2017-09-14 13:53:46 -0700 | [diff] [blame] | 38 | void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); |
| 39 | void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); |
| 40 | void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg); |
| 41 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 42 | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) |
Richard Henderson | 212c328 | 2012-10-02 11:32:28 -0700 | [diff] [blame] | 43 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 44 | tcg_gen_op1(opc, tcgv_i32_arg(a1)); |
Richard Henderson | 212c328 | 2012-10-02 11:32:28 -0700 | [diff] [blame] | 45 | } |
| 46 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 47 | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 48 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 49 | tcg_gen_op1(opc, tcgv_i64_arg(a1)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 50 | } |
| 51 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 52 | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 53 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 54 | tcg_gen_op1(opc, a1); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 55 | } |
| 56 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 57 | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 58 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 59 | tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 60 | } |
| 61 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 62 | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 63 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 64 | tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 65 | } |
| 66 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 67 | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 68 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 69 | tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 70 | } |
| 71 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 72 | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 73 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 74 | tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 75 | } |
| 76 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 77 | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 78 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 79 | tcg_gen_op2(opc, a1, a2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 80 | } |
| 81 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 82 | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, |
| 83 | TCGv_i32 a2, TCGv_i32 a3) |
pbrook | bcb0126 | 2008-05-24 02:24:25 +0000 | [diff] [blame] | 84 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 85 | tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); |
pbrook | bcb0126 | 2008-05-24 02:24:25 +0000 | [diff] [blame] | 86 | } |
| 87 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 88 | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, |
| 89 | TCGv_i64 a2, TCGv_i64 a3) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 90 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 91 | tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 92 | } |
| 93 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 94 | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, |
| 95 | TCGv_i32 a2, TCGArg a3) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 96 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 97 | tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 98 | } |
| 99 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 100 | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, |
| 101 | TCGv_i64 a2, TCGArg a3) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 102 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 103 | tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 104 | } |
| 105 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 106 | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
| 107 | TCGv_ptr base, TCGArg offset) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 108 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 109 | tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 110 | } |
| 111 | |
Richard Henderson | a975160 | 2010-03-19 11:12:29 -0700 | [diff] [blame] | 112 | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
| 113 | TCGv_ptr base, TCGArg offset) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 114 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 115 | tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 116 | } |
| 117 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 118 | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 119 | TCGv_i32 a3, TCGv_i32 a4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 120 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 121 | tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
| 122 | tcgv_i32_arg(a3), tcgv_i32_arg(a4)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 123 | } |
| 124 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 125 | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 126 | TCGv_i64 a3, TCGv_i64 a4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 127 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 128 | tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
| 129 | tcgv_i64_arg(a3), tcgv_i64_arg(a4)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 130 | } |
| 131 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 132 | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 133 | TCGv_i32 a3, TCGArg a4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 134 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 135 | tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
| 136 | tcgv_i32_arg(a3), a4); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 137 | } |
| 138 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 139 | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 140 | TCGv_i64 a3, TCGArg a4) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 141 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 142 | tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
| 143 | tcgv_i64_arg(a3), a4); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 144 | } |
| 145 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 146 | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 147 | TCGArg a3, TCGArg a4) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 148 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 149 | tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 150 | } |
| 151 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 152 | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 153 | TCGArg a3, TCGArg a4) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 154 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 155 | tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 156 | } |
| 157 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 158 | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 159 | TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 160 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 161 | tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
| 162 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 163 | } |
| 164 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 165 | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 166 | TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 167 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 168 | tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
| 169 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 170 | } |
| 171 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 172 | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 173 | TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 174 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 175 | tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
| 176 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 177 | } |
| 178 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 179 | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 180 | TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 181 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 182 | tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
| 183 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 184 | } |
| 185 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 186 | static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 187 | TCGv_i32 a3, TCGArg a4, TCGArg a5) |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 188 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 189 | tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
| 190 | tcgv_i32_arg(a3), a4, a5); |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 191 | } |
| 192 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 193 | static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 194 | TCGv_i64 a3, TCGArg a4, TCGArg a5) |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 195 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 196 | tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
| 197 | tcgv_i64_arg(a3), a4, a5); |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 198 | } |
| 199 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 200 | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 201 | TCGv_i32 a3, TCGv_i32 a4, |
| 202 | TCGv_i32 a5, TCGv_i32 a6) |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 203 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 204 | tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
| 205 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), |
| 206 | tcgv_i32_arg(a6)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 207 | } |
| 208 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 209 | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 210 | TCGv_i64 a3, TCGv_i64 a4, |
| 211 | TCGv_i64 a5, TCGv_i64 a6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 212 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 213 | tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
| 214 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), |
| 215 | tcgv_i64_arg(a6)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 216 | } |
| 217 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 218 | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 219 | TCGv_i32 a3, TCGv_i32 a4, |
| 220 | TCGv_i32 a5, TCGArg a6) |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 221 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 222 | tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
| 223 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 224 | } |
| 225 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 226 | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 227 | TCGv_i64 a3, TCGv_i64 a4, |
| 228 | TCGv_i64 a5, TCGArg a6) |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 229 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 230 | tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
| 231 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 232 | } |
| 233 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 234 | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
| 235 | TCGv_i32 a3, TCGv_i32 a4, |
| 236 | TCGArg a5, TCGArg a6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 237 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 238 | tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
| 239 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 240 | } |
| 241 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 242 | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
| 243 | TCGv_i64 a3, TCGv_i64 a4, |
| 244 | TCGArg a5, TCGArg a6) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 245 | { |
Richard Henderson | ae8b75d | 2017-10-15 13:27:56 -0700 | [diff] [blame] | 246 | tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
| 247 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 248 | } |
| 249 | |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 250 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 251 | /* Generic ops. */ |
| 252 | |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 253 | static inline void gen_set_label(TCGLabel *l) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 254 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 255 | tcg_gen_op1(INDEX_op_set_label, label_arg(l)); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 256 | } |
| 257 | |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 258 | static inline void tcg_gen_br(TCGLabel *l) |
blueswir1 | fb50d41 | 2008-03-21 17:58:45 +0000 | [diff] [blame] | 259 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 260 | tcg_gen_op1(INDEX_op_br, label_arg(l)); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 261 | } |
| 262 | |
Pranith Kumar | f65e19b | 2016-07-14 16:20:13 -0400 | [diff] [blame] | 263 | void tcg_gen_mb(TCGBar); |
| 264 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 265 | /* Helper calls. */ |
| 266 | |
| 267 | /* 32 bit ops */ |
| 268 | |
| 269 | void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 270 | void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); |
| 271 | void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
Richard Henderson | 474b2e8 | 2018-01-04 07:44:17 -0800 | [diff] [blame] | 272 | void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 273 | void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 274 | void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
Richard Henderson | 474b2e8 | 2018-01-04 07:44:17 -0800 | [diff] [blame] | 275 | void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 276 | void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 277 | void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 278 | void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
| 279 | void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 280 | void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 281 | void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 282 | void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 283 | void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 284 | void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 285 | void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 286 | void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 287 | void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
Richard Henderson | 0e28d00 | 2016-11-16 09:23:28 +0100 | [diff] [blame] | 288 | void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 289 | void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 290 | void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); |
| 291 | void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); |
Richard Henderson | 086920c | 2016-11-16 17:32:48 +0100 | [diff] [blame] | 292 | void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); |
Richard Henderson | a768e4e | 2016-11-21 11:13:39 +0100 | [diff] [blame] | 293 | void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 294 | void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 295 | void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); |
| 296 | void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
| 297 | void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); |
| 298 | void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, |
| 299 | unsigned int ofs, unsigned int len); |
Richard Henderson | 07cc68d | 2016-10-17 13:21:31 -0700 | [diff] [blame] | 300 | void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, |
| 301 | unsigned int ofs, unsigned int len); |
Richard Henderson | 7ec8bab | 2016-10-14 12:04:32 -0500 | [diff] [blame] | 302 | void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, |
| 303 | unsigned int ofs, unsigned int len); |
| 304 | void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, |
| 305 | unsigned int ofs, unsigned int len); |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 306 | void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); |
| 307 | void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 308 | void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
| 309 | TCGv_i32 arg1, TCGv_i32 arg2); |
| 310 | void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
| 311 | TCGv_i32 arg1, int32_t arg2); |
| 312 | void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, |
| 313 | TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); |
| 314 | void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, |
| 315 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); |
| 316 | void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, |
| 317 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); |
| 318 | void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
| 319 | void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
Richard Henderson | 5087abf | 2016-09-27 14:23:52 -0700 | [diff] [blame] | 320 | void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 321 | void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 322 | void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 323 | void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 324 | void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 325 | void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 326 | void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); |
| 327 | |
| 328 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
| 329 | { |
| 330 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
blueswir1 | fb50d41 | 2008-03-21 17:58:45 +0000 | [diff] [blame] | 331 | } |
| 332 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 333 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 334 | { |
Richard Henderson | 11f4e8f | 2017-10-19 20:27:27 -0700 | [diff] [blame] | 335 | if (ret != arg) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 336 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 337 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 338 | } |
| 339 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 340 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 341 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 342 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 343 | } |
| 344 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 345 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 346 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 347 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 348 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 349 | } |
| 350 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 351 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 352 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 353 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 354 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 355 | } |
| 356 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 357 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 358 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 359 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 360 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 361 | } |
| 362 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 363 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 364 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 365 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 366 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 367 | } |
| 368 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 369 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, |
| 370 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 371 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 372 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 373 | } |
| 374 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 375 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
| 376 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 377 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 378 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 379 | } |
| 380 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 381 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
| 382 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 383 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 384 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 385 | } |
| 386 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 387 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
| 388 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 389 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 390 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 391 | } |
| 392 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 393 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 394 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 395 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 396 | } |
| 397 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 398 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 399 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 400 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 401 | } |
| 402 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 403 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 404 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 405 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 406 | } |
| 407 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 408 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 409 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 410 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 411 | } |
| 412 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 413 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 414 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 415 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 416 | } |
| 417 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 418 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 419 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 420 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 421 | } |
| 422 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 423 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 424 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 425 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 426 | } |
| 427 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 428 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 429 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 430 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 431 | } |
| 432 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 433 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 434 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 435 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 436 | } |
| 437 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 438 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 439 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 440 | if (TCG_TARGET_HAS_neg_i32) { |
| 441 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 442 | } else { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 443 | tcg_gen_subfi_i32(ret, 0, arg); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 444 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 445 | } |
| 446 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 447 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 448 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 449 | if (TCG_TARGET_HAS_not_i32) { |
| 450 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 451 | } else { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 452 | tcg_gen_xori_i32(ret, arg, -1); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 453 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 454 | } |
| 455 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 456 | /* 64 bit ops */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 457 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 458 | void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 459 | void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); |
| 460 | void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
Richard Henderson | 474b2e8 | 2018-01-04 07:44:17 -0800 | [diff] [blame] | 461 | void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 462 | void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 463 | void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
Richard Henderson | 474b2e8 | 2018-01-04 07:44:17 -0800 | [diff] [blame] | 464 | void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 465 | void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 466 | void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 467 | void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
| 468 | void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 469 | void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 470 | void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 471 | void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 472 | void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 473 | void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 474 | void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 475 | void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 476 | void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
Richard Henderson | 0e28d00 | 2016-11-16 09:23:28 +0100 | [diff] [blame] | 477 | void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 478 | void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 479 | void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); |
| 480 | void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); |
Richard Henderson | 086920c | 2016-11-16 17:32:48 +0100 | [diff] [blame] | 481 | void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); |
Richard Henderson | a768e4e | 2016-11-21 11:13:39 +0100 | [diff] [blame] | 482 | void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 483 | void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 484 | void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); |
| 485 | void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 486 | void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); |
| 487 | void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, |
| 488 | unsigned int ofs, unsigned int len); |
Richard Henderson | 07cc68d | 2016-10-17 13:21:31 -0700 | [diff] [blame] | 489 | void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, |
| 490 | unsigned int ofs, unsigned int len); |
Richard Henderson | 7ec8bab | 2016-10-14 12:04:32 -0500 | [diff] [blame] | 491 | void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, |
| 492 | unsigned int ofs, unsigned int len); |
| 493 | void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, |
| 494 | unsigned int ofs, unsigned int len); |
Richard Henderson | 42a268c | 2015-02-13 12:51:55 -0800 | [diff] [blame] | 495 | void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); |
| 496 | void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 497 | void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
| 498 | TCGv_i64 arg1, TCGv_i64 arg2); |
| 499 | void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
| 500 | TCGv_i64 arg1, int64_t arg2); |
| 501 | void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, |
| 502 | TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); |
| 503 | void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, |
| 504 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); |
| 505 | void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, |
| 506 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); |
| 507 | void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
| 508 | void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
Richard Henderson | 5087abf | 2016-09-27 14:23:52 -0700 | [diff] [blame] | 509 | void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 510 | void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 511 | void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 512 | void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 513 | void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 514 | void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 515 | void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 516 | void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 517 | void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 518 | void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 519 | void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 520 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 521 | #if TCG_TARGET_REG_BITS == 64 |
| 522 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
| 523 | { |
| 524 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
| 525 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 526 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 527 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 528 | { |
Richard Henderson | 11f4e8f | 2017-10-19 20:27:27 -0700 | [diff] [blame] | 529 | if (ret != arg) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 530 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 531 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 532 | } |
| 533 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 534 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 535 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 536 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 537 | } |
| 538 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 539 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 540 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 541 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 542 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 543 | } |
| 544 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 545 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 546 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 547 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 548 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 549 | } |
| 550 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 551 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 552 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 553 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 554 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 555 | } |
| 556 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 557 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 558 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 559 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 560 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 561 | } |
| 562 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 563 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 564 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 565 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 566 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 567 | } |
| 568 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 569 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 570 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 571 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 572 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 573 | } |
| 574 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 575 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
| 576 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 577 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 578 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 579 | } |
| 580 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 581 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 582 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 583 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 584 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 585 | } |
| 586 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 587 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 588 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 589 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 590 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 591 | } |
| 592 | |
Peter Maydell | 6bd4b08 | 2011-05-27 13:12:12 +0100 | [diff] [blame] | 593 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 594 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 595 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 596 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 597 | } |
| 598 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 599 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 600 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 601 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 602 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 603 | } |
| 604 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 605 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 606 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 607 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 608 | } |
| 609 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 610 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 611 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 612 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 613 | } |
| 614 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 615 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 616 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 617 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 618 | } |
| 619 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 620 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 621 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 622 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 623 | } |
| 624 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 625 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 626 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 627 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 628 | } |
| 629 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 630 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 631 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 632 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 633 | } |
| 634 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 635 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 636 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 637 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 638 | } |
| 639 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 640 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 641 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 642 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 643 | } |
| 644 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 645 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 646 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 647 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 648 | } |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 649 | #else /* TCG_TARGET_REG_BITS == 32 */ |
| 650 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 651 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 652 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 653 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 654 | } |
| 655 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 656 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 657 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 658 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 659 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 660 | } |
| 661 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 662 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
| 663 | tcg_target_long offset) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 664 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 665 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 666 | } |
| 667 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 668 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 669 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 670 | tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
| 671 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); |
aurel32 | 6359706 | 2008-11-02 08:22:54 +0000 | [diff] [blame] | 672 | } |
| 673 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 674 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 675 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 676 | tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
| 677 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 678 | } |
| 679 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 680 | void tcg_gen_discard_i64(TCGv_i64 arg); |
| 681 | void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); |
| 682 | void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); |
| 683 | void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 684 | void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 685 | void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 686 | void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 687 | void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 688 | void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 689 | void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
| 690 | void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); |
| 691 | void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 692 | void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 693 | void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 694 | void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 695 | void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 696 | void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 697 | void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
| 698 | #endif /* TCG_TARGET_REG_BITS */ |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 699 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 700 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 701 | { |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 702 | if (TCG_TARGET_HAS_neg_i64) { |
| 703 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
| 704 | } else { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 705 | tcg_gen_subfi_i64(ret, 0, arg); |
Richard Henderson | 25c4d9c | 2011-08-17 14:11:46 -0700 | [diff] [blame] | 706 | } |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 707 | } |
| 708 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 709 | /* Size changing operations. */ |
| 710 | |
| 711 | void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); |
| 712 | void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); |
| 713 | void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); |
Richard Henderson | 609ad70 | 2015-07-24 07:16:00 -0700 | [diff] [blame] | 714 | void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); |
| 715 | void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 716 | void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); |
| 717 | void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); |
| 718 | |
| 719 | static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 720 | { |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 721 | tcg_gen_deposit_i64(ret, lo, hi, 32, 32); |
Richard Henderson | 77276f6 | 2012-09-21 17:18:13 -0700 | [diff] [blame] | 722 | } |
| 723 | |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 724 | /* QEMU specific operations. */ |
Richard Henderson | 3c51a98 | 2013-02-19 23:51:54 -0800 | [diff] [blame] | 725 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 726 | #ifndef TARGET_LONG_BITS |
| 727 | #error must include QEMU headers |
| 728 | #endif |
| 729 | |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 730 | #if TARGET_INSN_START_WORDS == 1 |
| 731 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
| 732 | static inline void tcg_gen_insn_start(target_ulong pc) |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 733 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 734 | tcg_gen_op1(INDEX_op_insn_start, pc); |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 735 | } |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 736 | # else |
| 737 | static inline void tcg_gen_insn_start(target_ulong pc) |
| 738 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 739 | tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 740 | } |
| 741 | # endif |
| 742 | #elif TARGET_INSN_START_WORDS == 2 |
| 743 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
| 744 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) |
| 745 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 746 | tcg_gen_op2(INDEX_op_insn_start, pc, a1); |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 747 | } |
| 748 | # else |
| 749 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) |
| 750 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 751 | tcg_gen_op4(INDEX_op_insn_start, |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 752 | (uint32_t)pc, (uint32_t)(pc >> 32), |
| 753 | (uint32_t)a1, (uint32_t)(a1 >> 32)); |
| 754 | } |
| 755 | # endif |
| 756 | #elif TARGET_INSN_START_WORDS == 3 |
| 757 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
| 758 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, |
| 759 | target_ulong a2) |
| 760 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 761 | tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2); |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 762 | } |
| 763 | # else |
| 764 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, |
| 765 | target_ulong a2) |
| 766 | { |
Richard Henderson | b7e8b17 | 2017-10-15 11:50:16 -0700 | [diff] [blame] | 767 | tcg_gen_op6(INDEX_op_insn_start, |
Richard Henderson | 9aef40e | 2015-08-30 09:21:33 -0700 | [diff] [blame] | 768 | (uint32_t)pc, (uint32_t)(pc >> 32), |
| 769 | (uint32_t)a1, (uint32_t)(a1 >> 32), |
| 770 | (uint32_t)a2, (uint32_t)(a2 >> 32)); |
| 771 | } |
| 772 | # endif |
| 773 | #else |
| 774 | # error "Unhandled number of operands to insn_start" |
| 775 | #endif |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 776 | |
| 777 | static inline void tcg_gen_exit_tb(uintptr_t val) |
| 778 | { |
| 779 | tcg_gen_op1i(INDEX_op_exit_tb, val); |
| 780 | } |
| 781 | |
Sergey Fedorov | 5b053a4 | 2016-04-08 19:48:12 +0300 | [diff] [blame] | 782 | /** |
| 783 | * tcg_gen_goto_tb() - output goto_tb TCG operation |
| 784 | * @idx: Direct jump slot index (0 or 1) |
| 785 | * |
| 786 | * See tcg/README for more info about this TCG operation. |
| 787 | * |
Sergey Fedorov | 90aa39a | 2016-04-09 01:00:23 +0300 | [diff] [blame] | 788 | * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within |
| 789 | * the pages this TB resides in because we don't take care of direct jumps when |
| 790 | * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a |
| 791 | * static address translation, so the destination address is always valid, TBs |
| 792 | * are always invalidated properly, and direct jumps are reset when mapping |
| 793 | * changes. |
Sergey Fedorov | 5b053a4 | 2016-04-08 19:48:12 +0300 | [diff] [blame] | 794 | */ |
Richard Henderson | 951c630 | 2014-09-19 11:39:20 -0700 | [diff] [blame] | 795 | void tcg_gen_goto_tb(unsigned idx); |
| 796 | |
Emilio G. Cota | cedbcb0 | 2017-04-26 23:29:14 -0400 | [diff] [blame] | 797 | /** |
Emilio G. Cota | 7f11636 | 2017-07-11 17:06:48 -0400 | [diff] [blame] | 798 | * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid |
Emilio G. Cota | cedbcb0 | 2017-04-26 23:29:14 -0400 | [diff] [blame] | 799 | * @addr: Guest address of the target TB |
| 800 | * |
| 801 | * If the TB is not valid, jump to the epilogue. |
| 802 | * |
| 803 | * This operation is optional. If the TCG backend does not implement goto_ptr, |
| 804 | * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument. |
| 805 | */ |
Emilio G. Cota | 7f11636 | 2017-07-11 17:06:48 -0400 | [diff] [blame] | 806 | void tcg_gen_lookup_and_goto_ptr(void); |
Emilio G. Cota | cedbcb0 | 2017-04-26 23:29:14 -0400 | [diff] [blame] | 807 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 808 | #if TARGET_LONG_BITS == 32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 809 | #define tcg_temp_new() tcg_temp_new_i32() |
| 810 | #define tcg_global_reg_new tcg_global_reg_new_i32 |
| 811 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
aurel32 | df9247b | 2009-01-01 14:09:05 +0000 | [diff] [blame] | 812 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 813 | #define tcg_temp_free tcg_temp_free_i32 |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 814 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 |
| 815 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 816 | #else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 817 | #define tcg_temp_new() tcg_temp_new_i64() |
| 818 | #define tcg_global_reg_new tcg_global_reg_new_i64 |
| 819 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
aurel32 | df9247b | 2009-01-01 14:09:05 +0000 | [diff] [blame] | 820 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 821 | #define tcg_temp_free tcg_temp_free_i64 |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 822 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 |
| 823 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 824 | #endif |
| 825 | |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 826 | void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); |
| 827 | void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); |
| 828 | void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); |
| 829 | void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); |
| 830 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 831 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 832 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 833 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 834 | } |
| 835 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 836 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 837 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 838 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 839 | } |
| 840 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 841 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 842 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 843 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 844 | } |
| 845 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 846 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 847 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 848 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 849 | } |
| 850 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 851 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 852 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 853 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 854 | } |
| 855 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 856 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 857 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 858 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 859 | } |
| 860 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 861 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 862 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 863 | tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 864 | } |
| 865 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 866 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 867 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 868 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 869 | } |
| 870 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 871 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 872 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 873 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 874 | } |
| 875 | |
pbrook | ac56dd4 | 2008-02-03 19:56:33 +0000 | [diff] [blame] | 876 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 877 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 878 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 879 | } |
| 880 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 881 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 882 | { |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 883 | tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 884 | } |
| 885 | |
Richard Henderson | c482cb1 | 2016-06-28 11:37:27 -0700 | [diff] [blame] | 886 | void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, |
| 887 | TCGArg, TCGMemOp); |
| 888 | void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, |
| 889 | TCGArg, TCGMemOp); |
| 890 | |
| 891 | void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 892 | void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 893 | void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 894 | void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 895 | void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 896 | void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 897 | void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 898 | void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 899 | void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 900 | void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 901 | void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 902 | void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 903 | void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 904 | void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 905 | void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 906 | void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 907 | void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); |
| 908 | void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); |
| 909 | |
Richard Henderson | d2fd745 | 2017-09-14 13:53:46 -0700 | [diff] [blame] | 910 | void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); |
| 911 | void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); |
| 912 | void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); |
| 913 | void tcg_gen_dup8i_vec(TCGv_vec, uint32_t); |
| 914 | void tcg_gen_dup16i_vec(TCGv_vec, uint32_t); |
| 915 | void tcg_gen_dup32i_vec(TCGv_vec, uint32_t); |
| 916 | void tcg_gen_dup64i_vec(TCGv_vec, uint64_t); |
Richard Henderson | db43267 | 2017-09-15 14:11:45 -0700 | [diff] [blame] | 917 | void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); |
Richard Henderson | d2fd745 | 2017-09-14 13:53:46 -0700 | [diff] [blame] | 918 | void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
| 919 | void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
Richard Henderson | 3774030 | 2017-11-21 10:11:14 +0100 | [diff] [blame] | 920 | void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
Richard Henderson | d2fd745 | 2017-09-14 13:53:46 -0700 | [diff] [blame] | 921 | void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
| 922 | void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
| 923 | void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
| 924 | void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
| 925 | void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
| 926 | void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); |
| 927 | void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); |
| 928 | |
Richard Henderson | d0ec979 | 2017-11-17 14:35:11 +0100 | [diff] [blame] | 929 | void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); |
| 930 | void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); |
| 931 | void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); |
| 932 | |
Richard Henderson | 212be17 | 2017-11-17 20:47:42 +0100 | [diff] [blame] | 933 | void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, |
| 934 | TCGv_vec a, TCGv_vec b); |
| 935 | |
Richard Henderson | d2fd745 | 2017-09-14 13:53:46 -0700 | [diff] [blame] | 936 | void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); |
| 937 | void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); |
| 938 | void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); |
| 939 | |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 940 | #if TARGET_LONG_BITS == 64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 941 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
| 942 | #define tcg_gen_mov_tl tcg_gen_mov_i64 |
| 943 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 |
| 944 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 |
| 945 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 |
| 946 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 |
| 947 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 |
| 948 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 |
| 949 | #define tcg_gen_ld_tl tcg_gen_ld_i64 |
| 950 | #define tcg_gen_st8_tl tcg_gen_st8_i64 |
| 951 | #define tcg_gen_st16_tl tcg_gen_st16_i64 |
| 952 | #define tcg_gen_st32_tl tcg_gen_st32_i64 |
| 953 | #define tcg_gen_st_tl tcg_gen_st_i64 |
| 954 | #define tcg_gen_add_tl tcg_gen_add_i64 |
| 955 | #define tcg_gen_addi_tl tcg_gen_addi_i64 |
| 956 | #define tcg_gen_sub_tl tcg_gen_sub_i64 |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 957 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
pbrook | 10460c8 | 2008-11-02 13:26:16 +0000 | [diff] [blame] | 958 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 959 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
| 960 | #define tcg_gen_and_tl tcg_gen_and_i64 |
| 961 | #define tcg_gen_andi_tl tcg_gen_andi_i64 |
| 962 | #define tcg_gen_or_tl tcg_gen_or_i64 |
| 963 | #define tcg_gen_ori_tl tcg_gen_ori_i64 |
| 964 | #define tcg_gen_xor_tl tcg_gen_xor_i64 |
| 965 | #define tcg_gen_xori_tl tcg_gen_xori_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 966 | #define tcg_gen_not_tl tcg_gen_not_i64 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 967 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
| 968 | #define tcg_gen_shli_tl tcg_gen_shli_i64 |
| 969 | #define tcg_gen_shr_tl tcg_gen_shr_i64 |
| 970 | #define tcg_gen_shri_tl tcg_gen_shri_i64 |
| 971 | #define tcg_gen_sar_tl tcg_gen_sar_i64 |
| 972 | #define tcg_gen_sari_tl tcg_gen_sari_i64 |
blueswir1 | 0cf767d | 2008-03-02 18:20:59 +0000 | [diff] [blame] | 973 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 974 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 975 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
Aurelien Jarno | add1e7e | 2010-02-08 12:06:05 +0100 | [diff] [blame] | 976 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 977 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
| 978 | #define tcg_gen_muli_tl tcg_gen_muli_i64 |
aurel32 | ab36421 | 2009-03-29 01:19:22 +0000 | [diff] [blame] | 979 | #define tcg_gen_div_tl tcg_gen_div_i64 |
| 980 | #define tcg_gen_rem_tl tcg_gen_rem_i64 |
aurel32 | 864951a | 2009-03-29 14:08:54 +0000 | [diff] [blame] | 981 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
| 982 | #define tcg_gen_remu_tl tcg_gen_remu_i64 |
blueswir1 | a768e4b | 2008-03-16 19:16:37 +0000 | [diff] [blame] | 983 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
Richard Henderson | ecc7b3a | 2015-07-24 11:49:53 -0700 | [diff] [blame] | 984 | #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 985 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 |
| 986 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 |
| 987 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 |
| 988 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 |
| 989 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 990 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
| 991 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 |
| 992 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 |
| 993 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 |
| 994 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 |
| 995 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 |
aurel32 | 911d79b | 2009-03-13 09:35:19 +0000 | [diff] [blame] | 996 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
| 997 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 |
| 998 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 999 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
Richard Henderson | 3c51a98 | 2013-02-19 23:51:54 -0800 | [diff] [blame] | 1000 | #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1001 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
| 1002 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 |
| 1003 | #define tcg_gen_nand_tl tcg_gen_nand_i64 |
| 1004 | #define tcg_gen_nor_tl tcg_gen_nor_i64 |
| 1005 | #define tcg_gen_orc_tl tcg_gen_orc_i64 |
Richard Henderson | 0e28d00 | 2016-11-16 09:23:28 +0100 | [diff] [blame] | 1006 | #define tcg_gen_clz_tl tcg_gen_clz_i64 |
| 1007 | #define tcg_gen_ctz_tl tcg_gen_ctz_i64 |
| 1008 | #define tcg_gen_clzi_tl tcg_gen_clzi_i64 |
| 1009 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 |
Richard Henderson | 086920c | 2016-11-16 17:32:48 +0100 | [diff] [blame] | 1010 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64 |
Richard Henderson | a768e4e | 2016-11-21 11:13:39 +0100 | [diff] [blame] | 1011 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64 |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1012 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
| 1013 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 |
| 1014 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 |
| 1015 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 1016 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
Richard Henderson | 07cc68d | 2016-10-17 13:21:31 -0700 | [diff] [blame] | 1017 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 |
Richard Henderson | 7ec8bab | 2016-10-14 12:04:32 -0500 | [diff] [blame] | 1018 | #define tcg_gen_extract_tl tcg_gen_extract_i64 |
| 1019 | #define tcg_gen_sextract_tl tcg_gen_sextract_i64 |
blueswir1 | a98824a | 2008-03-13 20:46:42 +0000 | [diff] [blame] | 1020 | #define tcg_const_tl tcg_const_i64 |
aurel32 | bdffd4a | 2008-10-21 11:30:45 +0000 | [diff] [blame] | 1021 | #define tcg_const_local_tl tcg_const_local_i64 |
Richard Henderson | ffc5ea0 | 2012-09-21 10:13:34 -0700 | [diff] [blame] | 1022 | #define tcg_gen_movcond_tl tcg_gen_movcond_i64 |
Richard Henderson | f6953a7 | 2013-02-19 23:51:56 -0800 | [diff] [blame] | 1023 | #define tcg_gen_add2_tl tcg_gen_add2_i64 |
| 1024 | #define tcg_gen_sub2_tl tcg_gen_sub2_i64 |
Richard Henderson | 696a8be | 2013-02-19 23:51:55 -0800 | [diff] [blame] | 1025 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 |
| 1026 | #define tcg_gen_muls2_tl tcg_gen_muls2_i64 |
Richard Henderson | 5087abf | 2016-09-27 14:23:52 -0700 | [diff] [blame] | 1027 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 |
Richard Henderson | c482cb1 | 2016-06-28 11:37:27 -0700 | [diff] [blame] | 1028 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 |
| 1029 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 |
| 1030 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 |
| 1031 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64 |
| 1032 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64 |
| 1033 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64 |
| 1034 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64 |
| 1035 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64 |
| 1036 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64 |
| 1037 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64 |
Richard Henderson | d2fd745 | 2017-09-14 13:53:46 -0700 | [diff] [blame] | 1038 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1039 | #else |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1040 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
| 1041 | #define tcg_gen_mov_tl tcg_gen_mov_i32 |
| 1042 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 |
| 1043 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 |
| 1044 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 |
| 1045 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 |
| 1046 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 |
| 1047 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 |
| 1048 | #define tcg_gen_ld_tl tcg_gen_ld_i32 |
| 1049 | #define tcg_gen_st8_tl tcg_gen_st8_i32 |
| 1050 | #define tcg_gen_st16_tl tcg_gen_st16_i32 |
| 1051 | #define tcg_gen_st32_tl tcg_gen_st_i32 |
| 1052 | #define tcg_gen_st_tl tcg_gen_st_i32 |
| 1053 | #define tcg_gen_add_tl tcg_gen_add_i32 |
| 1054 | #define tcg_gen_addi_tl tcg_gen_addi_i32 |
| 1055 | #define tcg_gen_sub_tl tcg_gen_sub_i32 |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1056 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
aurel32 | 0045734 | 2008-11-02 08:23:04 +0000 | [diff] [blame] | 1057 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1058 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
| 1059 | #define tcg_gen_and_tl tcg_gen_and_i32 |
| 1060 | #define tcg_gen_andi_tl tcg_gen_andi_i32 |
| 1061 | #define tcg_gen_or_tl tcg_gen_or_i32 |
| 1062 | #define tcg_gen_ori_tl tcg_gen_ori_i32 |
| 1063 | #define tcg_gen_xor_tl tcg_gen_xor_i32 |
| 1064 | #define tcg_gen_xori_tl tcg_gen_xori_i32 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1065 | #define tcg_gen_not_tl tcg_gen_not_i32 |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1066 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
| 1067 | #define tcg_gen_shli_tl tcg_gen_shli_i32 |
| 1068 | #define tcg_gen_shr_tl tcg_gen_shr_i32 |
| 1069 | #define tcg_gen_shri_tl tcg_gen_shri_i32 |
| 1070 | #define tcg_gen_sar_tl tcg_gen_sar_i32 |
| 1071 | #define tcg_gen_sari_tl tcg_gen_sari_i32 |
blueswir1 | 0cf767d | 2008-03-02 18:20:59 +0000 | [diff] [blame] | 1072 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 1073 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
Richard Henderson | be210ac | 2010-01-07 10:13:31 -0800 | [diff] [blame] | 1074 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
Aurelien Jarno | add1e7e | 2010-02-08 12:06:05 +0100 | [diff] [blame] | 1075 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
ths | f730fd2 | 2008-05-04 08:14:08 +0000 | [diff] [blame] | 1076 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
| 1077 | #define tcg_gen_muli_tl tcg_gen_muli_i32 |
aurel32 | ab36421 | 2009-03-29 01:19:22 +0000 | [diff] [blame] | 1078 | #define tcg_gen_div_tl tcg_gen_div_i32 |
| 1079 | #define tcg_gen_rem_tl tcg_gen_rem_i32 |
aurel32 | 864951a | 2009-03-29 14:08:54 +0000 | [diff] [blame] | 1080 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
| 1081 | #define tcg_gen_remu_tl tcg_gen_remu_i32 |
blueswir1 | a768e4b | 2008-03-16 19:16:37 +0000 | [diff] [blame] | 1082 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 1083 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
Richard Henderson | ecc7b3a | 2015-07-24 11:49:53 -0700 | [diff] [blame] | 1084 | #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 |
blueswir1 | e429073 | 2008-03-22 08:39:04 +0000 | [diff] [blame] | 1085 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 |
| 1086 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 |
| 1087 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 |
| 1088 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 |
bellard | 0b6ce4c | 2008-05-17 12:40:44 +0000 | [diff] [blame] | 1089 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
| 1090 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 |
| 1091 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 |
| 1092 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 |
| 1093 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 |
| 1094 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 |
aurel32 | 911d79b | 2009-03-13 09:35:19 +0000 | [diff] [blame] | 1095 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
| 1096 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 |
blueswir1 | 945ca82 | 2008-09-21 18:32:28 +0000 | [diff] [blame] | 1097 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
Alexander Graf | e3eb980 | 2014-06-04 23:09:11 +0200 | [diff] [blame] | 1098 | #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 |
aurel32 | f24cb33 | 2008-10-21 11:28:59 +0000 | [diff] [blame] | 1099 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
| 1100 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 |
| 1101 | #define tcg_gen_nand_tl tcg_gen_nand_i32 |
| 1102 | #define tcg_gen_nor_tl tcg_gen_nor_i32 |
| 1103 | #define tcg_gen_orc_tl tcg_gen_orc_i32 |
Richard Henderson | 0e28d00 | 2016-11-16 09:23:28 +0100 | [diff] [blame] | 1104 | #define tcg_gen_clz_tl tcg_gen_clz_i32 |
| 1105 | #define tcg_gen_ctz_tl tcg_gen_ctz_i32 |
| 1106 | #define tcg_gen_clzi_tl tcg_gen_clzi_i32 |
| 1107 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 |
Richard Henderson | 086920c | 2016-11-16 17:32:48 +0100 | [diff] [blame] | 1108 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32 |
Richard Henderson | a768e4e | 2016-11-21 11:13:39 +0100 | [diff] [blame] | 1109 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32 |
aurel32 | 1582457 | 2008-11-03 07:08:36 +0000 | [diff] [blame] | 1110 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
| 1111 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 |
| 1112 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 |
| 1113 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 |
Richard Henderson | b7767f0 | 2011-01-10 19:23:42 -0800 | [diff] [blame] | 1114 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
Richard Henderson | 07cc68d | 2016-10-17 13:21:31 -0700 | [diff] [blame] | 1115 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 |
Richard Henderson | 7ec8bab | 2016-10-14 12:04:32 -0500 | [diff] [blame] | 1116 | #define tcg_gen_extract_tl tcg_gen_extract_i32 |
| 1117 | #define tcg_gen_sextract_tl tcg_gen_sextract_i32 |
blueswir1 | a98824a | 2008-03-13 20:46:42 +0000 | [diff] [blame] | 1118 | #define tcg_const_tl tcg_const_i32 |
aurel32 | bdffd4a | 2008-10-21 11:30:45 +0000 | [diff] [blame] | 1119 | #define tcg_const_local_tl tcg_const_local_i32 |
Richard Henderson | ffc5ea0 | 2012-09-21 10:13:34 -0700 | [diff] [blame] | 1120 | #define tcg_gen_movcond_tl tcg_gen_movcond_i32 |
Richard Henderson | f6953a7 | 2013-02-19 23:51:56 -0800 | [diff] [blame] | 1121 | #define tcg_gen_add2_tl tcg_gen_add2_i32 |
| 1122 | #define tcg_gen_sub2_tl tcg_gen_sub2_i32 |
Richard Henderson | 696a8be | 2013-02-19 23:51:55 -0800 | [diff] [blame] | 1123 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 |
| 1124 | #define tcg_gen_muls2_tl tcg_gen_muls2_i32 |
Richard Henderson | 5087abf | 2016-09-27 14:23:52 -0700 | [diff] [blame] | 1125 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 |
Richard Henderson | c482cb1 | 2016-06-28 11:37:27 -0700 | [diff] [blame] | 1126 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 |
| 1127 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 |
| 1128 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 |
| 1129 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32 |
| 1130 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32 |
| 1131 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32 |
| 1132 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32 |
| 1133 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32 |
| 1134 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32 |
| 1135 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32 |
Richard Henderson | d2fd745 | 2017-09-14 13:53:46 -0700 | [diff] [blame] | 1136 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec |
blueswir1 | f8422f5 | 2008-02-24 07:45:43 +0000 | [diff] [blame] | 1137 | #endif |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 1138 | |
Richard Henderson | 71b9269 | 2013-09-09 08:26:49 -0700 | [diff] [blame] | 1139 | #if UINTPTR_MAX == UINT32_MAX |
Richard Henderson | f713d6a | 2013-09-04 08:11:05 -0700 | [diff] [blame] | 1140 | # define tcg_gen_ld_ptr(R, A, O) \ |
| 1141 | tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O)) |
| 1142 | # define tcg_gen_discard_ptr(A) \ |
| 1143 | tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A)) |
| 1144 | # define tcg_gen_add_ptr(R, A, B) \ |
| 1145 | tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) |
| 1146 | # define tcg_gen_addi_ptr(R, A, B) \ |
| 1147 | tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) |
| 1148 | # define tcg_gen_ext_i32_ptr(R, A) \ |
| 1149 | tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A)) |
| 1150 | #else |
| 1151 | # define tcg_gen_ld_ptr(R, A, O) \ |
| 1152 | tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O)) |
| 1153 | # define tcg_gen_discard_ptr(A) \ |
| 1154 | tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A)) |
| 1155 | # define tcg_gen_add_ptr(R, A, B) \ |
| 1156 | tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B)) |
| 1157 | # define tcg_gen_addi_ptr(R, A, B) \ |
| 1158 | tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B)) |
| 1159 | # define tcg_gen_ext_i32_ptr(R, A) \ |
| 1160 | tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A)) |
Richard Henderson | 71b9269 | 2013-09-09 08:26:49 -0700 | [diff] [blame] | 1161 | #endif /* UINTPTR_MAX == UINT32_MAX */ |