Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM GIC support - internal interfaces |
| 3 | * |
| 4 | * Copyright (c) 2012 Linaro Limited |
| 5 | * Written by Peter Maydell |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation, either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef QEMU_ARM_GIC_INTERNAL_H |
| 22 | #define QEMU_ARM_GIC_INTERNAL_H |
| 23 | |
Luc Michel | 7c2fffd | 2018-08-14 17:17:20 +0100 | [diff] [blame] | 24 | #include "hw/registerfields.h" |
Andreas Färber | 8372879 | 2013-07-23 03:37:49 +0200 | [diff] [blame] | 25 | #include "hw/intc/arm_gic.h" |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 26 | |
Andreas Färber | 8372879 | 2013-07-23 03:37:49 +0200 | [diff] [blame] | 27 | #define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1))) |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 28 | |
Luc Michel | 67ce697 | 2018-08-14 17:17:19 +0100 | [diff] [blame] | 29 | #define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm)) |
| 30 | #define GIC_DIST_CLEAR_ENABLED(irq, cm) (s->irq_state[irq].enabled &= ~(cm)) |
| 31 | #define GIC_DIST_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0) |
| 32 | #define GIC_DIST_SET_PENDING(irq, cm) (s->irq_state[irq].pending |= (cm)) |
| 33 | #define GIC_DIST_CLEAR_PENDING(irq, cm) (s->irq_state[irq].pending &= ~(cm)) |
| 34 | #define GIC_DIST_SET_ACTIVE(irq, cm) (s->irq_state[irq].active |= (cm)) |
| 35 | #define GIC_DIST_CLEAR_ACTIVE(irq, cm) (s->irq_state[irq].active &= ~(cm)) |
| 36 | #define GIC_DIST_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) |
| 37 | #define GIC_DIST_SET_MODEL(irq) (s->irq_state[irq].model = true) |
| 38 | #define GIC_DIST_CLEAR_MODEL(irq) (s->irq_state[irq].model = false) |
| 39 | #define GIC_DIST_TEST_MODEL(irq) (s->irq_state[irq].model) |
| 40 | #define GIC_DIST_SET_LEVEL(irq, cm) (s->irq_state[irq].level |= (cm)) |
| 41 | #define GIC_DIST_CLEAR_LEVEL(irq, cm) (s->irq_state[irq].level &= ~(cm)) |
| 42 | #define GIC_DIST_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) |
| 43 | #define GIC_DIST_SET_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger = true) |
| 44 | #define GIC_DIST_CLEAR_EDGE_TRIGGER(irq) \ |
| 45 | (s->irq_state[irq].edge_trigger = false) |
| 46 | #define GIC_DIST_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger) |
| 47 | #define GIC_DIST_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 48 | s->priority1[irq][cpu] : \ |
| 49 | s->priority2[(irq) - GIC_INTERNAL]) |
Luc Michel | 67ce697 | 2018-08-14 17:17:19 +0100 | [diff] [blame] | 50 | #define GIC_DIST_TARGET(irq) (s->irq_target[irq]) |
| 51 | #define GIC_DIST_CLEAR_GROUP(irq, cm) (s->irq_state[irq].group &= ~(cm)) |
| 52 | #define GIC_DIST_SET_GROUP(irq, cm) (s->irq_state[irq].group |= (cm)) |
| 53 | #define GIC_DIST_TEST_GROUP(irq, cm) ((s->irq_state[irq].group & (cm)) != 0) |
Fabian Aggeler | c27a5ba | 2015-05-12 11:57:17 +0100 | [diff] [blame] | 54 | |
Fabian Aggeler | 679aa17 | 2015-05-12 11:57:17 +0100 | [diff] [blame] | 55 | #define GICD_CTLR_EN_GRP0 (1U << 0) |
| 56 | #define GICD_CTLR_EN_GRP1 (1U << 1) |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 57 | |
Fabian Aggeler | 3295186 | 2015-05-12 11:57:17 +0100 | [diff] [blame] | 58 | #define GICC_CTLR_EN_GRP0 (1U << 0) |
| 59 | #define GICC_CTLR_EN_GRP1 (1U << 1) |
| 60 | #define GICC_CTLR_ACK_CTL (1U << 2) |
| 61 | #define GICC_CTLR_FIQ_EN (1U << 3) |
| 62 | #define GICC_CTLR_CBPR (1U << 4) /* GICv1: SBPR */ |
| 63 | #define GICC_CTLR_EOIMODE (1U << 9) |
| 64 | #define GICC_CTLR_EOIMODE_NS (1U << 10) |
| 65 | |
Luc Michel | 7c2fffd | 2018-08-14 17:17:20 +0100 | [diff] [blame] | 66 | REG32(GICH_HCR, 0x0) |
| 67 | FIELD(GICH_HCR, EN, 0, 1) |
| 68 | FIELD(GICH_HCR, UIE, 1, 1) |
| 69 | FIELD(GICH_HCR, LRENPIE, 2, 1) |
| 70 | FIELD(GICH_HCR, NPIE, 3, 1) |
| 71 | FIELD(GICH_HCR, VGRP0EIE, 4, 1) |
| 72 | FIELD(GICH_HCR, VGRP0DIE, 5, 1) |
| 73 | FIELD(GICH_HCR, VGRP1EIE, 6, 1) |
| 74 | FIELD(GICH_HCR, VGRP1DIE, 7, 1) |
| 75 | FIELD(GICH_HCR, EOICount, 27, 5) |
| 76 | |
| 77 | #define GICH_HCR_MASK \ |
| 78 | (R_GICH_HCR_EN_MASK | R_GICH_HCR_UIE_MASK | \ |
| 79 | R_GICH_HCR_LRENPIE_MASK | R_GICH_HCR_NPIE_MASK | \ |
| 80 | R_GICH_HCR_VGRP0EIE_MASK | R_GICH_HCR_VGRP0DIE_MASK | \ |
| 81 | R_GICH_HCR_VGRP1EIE_MASK | R_GICH_HCR_VGRP1DIE_MASK | \ |
| 82 | R_GICH_HCR_EOICount_MASK) |
| 83 | |
| 84 | REG32(GICH_VTR, 0x4) |
| 85 | FIELD(GICH_VTR, ListRegs, 0, 6) |
| 86 | FIELD(GICH_VTR, PREbits, 26, 3) |
| 87 | FIELD(GICH_VTR, PRIbits, 29, 3) |
| 88 | |
| 89 | REG32(GICH_VMCR, 0x8) |
| 90 | FIELD(GICH_VMCR, VMCCtlr, 0, 10) |
| 91 | FIELD(GICH_VMCR, VMABP, 18, 3) |
| 92 | FIELD(GICH_VMCR, VMBP, 21, 3) |
| 93 | FIELD(GICH_VMCR, VMPriMask, 27, 5) |
| 94 | |
| 95 | REG32(GICH_MISR, 0x10) |
| 96 | FIELD(GICH_MISR, EOI, 0, 1) |
| 97 | FIELD(GICH_MISR, U, 1, 1) |
| 98 | FIELD(GICH_MISR, LRENP, 2, 1) |
| 99 | FIELD(GICH_MISR, NP, 3, 1) |
| 100 | FIELD(GICH_MISR, VGrp0E, 4, 1) |
| 101 | FIELD(GICH_MISR, VGrp0D, 5, 1) |
| 102 | FIELD(GICH_MISR, VGrp1E, 6, 1) |
| 103 | FIELD(GICH_MISR, VGrp1D, 7, 1) |
| 104 | |
| 105 | REG32(GICH_EISR0, 0x20) |
| 106 | REG32(GICH_EISR1, 0x24) |
| 107 | REG32(GICH_ELRSR0, 0x30) |
| 108 | REG32(GICH_ELRSR1, 0x34) |
| 109 | REG32(GICH_APR, 0xf0) |
| 110 | |
| 111 | REG32(GICH_LR0, 0x100) |
| 112 | FIELD(GICH_LR0, VirtualID, 0, 10) |
| 113 | FIELD(GICH_LR0, PhysicalID, 10, 10) |
| 114 | FIELD(GICH_LR0, CPUID, 10, 3) |
| 115 | FIELD(GICH_LR0, EOI, 19, 1) |
| 116 | FIELD(GICH_LR0, Priority, 23, 5) |
| 117 | FIELD(GICH_LR0, State, 28, 2) |
| 118 | FIELD(GICH_LR0, Grp1, 30, 1) |
| 119 | FIELD(GICH_LR0, HW, 31, 1) |
| 120 | |
| 121 | /* Last LR register */ |
| 122 | REG32(GICH_LR63, 0x1fc) |
| 123 | |
| 124 | #define GICH_LR_MASK \ |
| 125 | (R_GICH_LR0_VirtualID_MASK | R_GICH_LR0_PhysicalID_MASK | \ |
| 126 | R_GICH_LR0_CPUID_MASK | R_GICH_LR0_EOI_MASK | \ |
| 127 | R_GICH_LR0_Priority_MASK | R_GICH_LR0_State_MASK | \ |
| 128 | R_GICH_LR0_Grp1_MASK | R_GICH_LR0_HW_MASK) |
| 129 | |
Luc Michel | 4a37e0e | 2018-08-14 17:17:20 +0100 | [diff] [blame] | 130 | #define GICH_LR_STATE_INVALID 0 |
| 131 | #define GICH_LR_STATE_PENDING 1 |
| 132 | #define GICH_LR_STATE_ACTIVE 2 |
| 133 | #define GICH_LR_STATE_ACTIVE_PENDING 3 |
| 134 | |
| 135 | #define GICH_LR_VIRT_ID(entry) (FIELD_EX32(entry, GICH_LR0, VirtualID)) |
| 136 | #define GICH_LR_PHYS_ID(entry) (FIELD_EX32(entry, GICH_LR0, PhysicalID)) |
| 137 | #define GICH_LR_CPUID(entry) (FIELD_EX32(entry, GICH_LR0, CPUID)) |
| 138 | #define GICH_LR_EOI(entry) (FIELD_EX32(entry, GICH_LR0, EOI)) |
| 139 | #define GICH_LR_PRIORITY(entry) (FIELD_EX32(entry, GICH_LR0, Priority) << 3) |
| 140 | #define GICH_LR_STATE(entry) (FIELD_EX32(entry, GICH_LR0, State)) |
| 141 | #define GICH_LR_GROUP(entry) (FIELD_EX32(entry, GICH_LR0, Grp1)) |
| 142 | #define GICH_LR_HW(entry) (FIELD_EX32(entry, GICH_LR0, HW)) |
| 143 | |
Luc Michel | 86b350f | 2018-08-14 17:17:20 +0100 | [diff] [blame] | 144 | #define GICH_LR_CLEAR_PENDING(entry) \ |
| 145 | ((entry) &= ~(GICH_LR_STATE_PENDING << R_GICH_LR0_State_SHIFT)) |
| 146 | #define GICH_LR_SET_ACTIVE(entry) \ |
| 147 | ((entry) |= (GICH_LR_STATE_ACTIVE << R_GICH_LR0_State_SHIFT)) |
| 148 | #define GICH_LR_CLEAR_ACTIVE(entry) \ |
| 149 | ((entry) &= ~(GICH_LR_STATE_ACTIVE << R_GICH_LR0_State_SHIFT)) |
| 150 | |
Fabian Aggeler | 3295186 | 2015-05-12 11:57:17 +0100 | [diff] [blame] | 151 | /* Valid bits for GICC_CTLR for GICv1, v1 with security extensions, |
| 152 | * GICv2 and GICv2 with security extensions: |
| 153 | */ |
| 154 | #define GICC_CTLR_V1_MASK 0x1 |
| 155 | #define GICC_CTLR_V1_S_MASK 0x1f |
| 156 | #define GICC_CTLR_V2_MASK 0x21f |
| 157 | #define GICC_CTLR_V2_S_MASK 0x61f |
| 158 | |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 159 | /* The special cases for the revision property: */ |
| 160 | #define REV_11MPCORE 0 |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 161 | |
Fabian Aggeler | c5619bf | 2015-05-12 11:57:18 +0100 | [diff] [blame] | 162 | uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs); |
Luc Michel | 67ce697 | 2018-08-14 17:17:19 +0100 | [diff] [blame] | 163 | void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, |
| 164 | MemTxAttrs attrs); |
Peter Maydell | 1e8cae4 | 2012-05-02 16:49:42 +0000 | [diff] [blame] | 165 | |
Christoffer Dall | 8d99999 | 2013-11-18 20:32:00 -0800 | [diff] [blame] | 166 | static inline bool gic_test_pending(GICState *s, int irq, int cm) |
| 167 | { |
Michael Davidsaver | 7c14b3a | 2017-02-28 12:08:17 +0000 | [diff] [blame] | 168 | if (s->revision == REV_11MPCORE) { |
Christoffer Dall | 8d99999 | 2013-11-18 20:32:00 -0800 | [diff] [blame] | 169 | return s->irq_state[irq].pending & cm; |
| 170 | } else { |
| 171 | /* Edge-triggered interrupts are marked pending on a rising edge, but |
| 172 | * level-triggered interrupts are either considered pending when the |
| 173 | * level is active or if software has explicitly written to |
| 174 | * GICD_ISPENDR to set the state pending. |
| 175 | */ |
| 176 | return (s->irq_state[irq].pending & cm) || |
Luc Michel | 67ce697 | 2018-08-14 17:17:19 +0100 | [diff] [blame] | 177 | (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_LEVEL(irq, cm)); |
Christoffer Dall | 8d99999 | 2013-11-18 20:32:00 -0800 | [diff] [blame] | 178 | } |
| 179 | } |
| 180 | |
Luc Michel | 5773c04 | 2018-08-14 17:17:20 +0100 | [diff] [blame] | 181 | static inline bool gic_is_vcpu(int cpu) |
| 182 | { |
| 183 | return cpu >= GIC_NCPU; |
| 184 | } |
| 185 | |
Luc Michel | 4a37e0e | 2018-08-14 17:17:20 +0100 | [diff] [blame] | 186 | static inline int gic_get_vcpu_real_id(int cpu) |
| 187 | { |
| 188 | return (cpu >= GIC_NCPU) ? (cpu - GIC_NCPU) : cpu; |
| 189 | } |
| 190 | |
| 191 | /* Return true if the given vIRQ state exists in a LR and is either active or |
| 192 | * pending and active. |
| 193 | * |
| 194 | * This function is used to check that a guest's `end of interrupt' or |
| 195 | * `interrupts deactivation' request is valid, and matches with a LR of an |
| 196 | * already acknowledged vIRQ (i.e. has the active bit set in its state). |
| 197 | */ |
| 198 | static inline bool gic_virq_is_valid(GICState *s, int irq, int vcpu) |
| 199 | { |
| 200 | int cpu = gic_get_vcpu_real_id(vcpu); |
| 201 | int lr_idx; |
| 202 | |
| 203 | for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) { |
| 204 | uint32_t *entry = &s->h_lr[lr_idx][cpu]; |
| 205 | |
| 206 | if ((GICH_LR_VIRT_ID(*entry) == irq) && |
| 207 | (GICH_LR_STATE(*entry) & GICH_LR_STATE_ACTIVE)) { |
| 208 | return true; |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | return false; |
| 213 | } |
| 214 | |
| 215 | /* Return a pointer on the LR entry matching the given vIRQ. |
| 216 | * |
| 217 | * This function is used to retrieve an LR for which we know for sure that the |
| 218 | * corresponding vIRQ exists in the current context (i.e. its current state is |
| 219 | * not `invalid'): |
| 220 | * - Either the corresponding vIRQ has been validated with gic_virq_is_valid() |
| 221 | * so it is `active' or `active and pending', |
| 222 | * - Or it was pending and has been selected by gic_get_best_virq(). It is now |
| 223 | * `pending', `active' or `active and pending', depending on what the guest |
| 224 | * already did with this vIRQ. |
| 225 | * |
| 226 | * Having multiple LRs with the same VirtualID leads to UNPREDICTABLE |
| 227 | * behaviour in the GIC. We choose to return the first one that matches. |
| 228 | */ |
| 229 | static inline uint32_t *gic_get_lr_entry(GICState *s, int irq, int vcpu) |
| 230 | { |
| 231 | int cpu = gic_get_vcpu_real_id(vcpu); |
| 232 | int lr_idx; |
| 233 | |
| 234 | for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) { |
| 235 | uint32_t *entry = &s->h_lr[lr_idx][cpu]; |
| 236 | |
| 237 | if ((GICH_LR_VIRT_ID(*entry) == irq) && |
| 238 | (GICH_LR_STATE(*entry) != GICH_LR_STATE_INVALID)) { |
| 239 | return entry; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | g_assert_not_reached(); |
| 244 | } |
| 245 | |
Luc Michel | 86b350f | 2018-08-14 17:17:20 +0100 | [diff] [blame] | 246 | static inline bool gic_test_group(GICState *s, int irq, int cpu) |
| 247 | { |
| 248 | if (gic_is_vcpu(cpu)) { |
| 249 | uint32_t *entry = gic_get_lr_entry(s, irq, cpu); |
| 250 | return GICH_LR_GROUP(*entry); |
| 251 | } else { |
| 252 | return GIC_DIST_TEST_GROUP(irq, 1 << cpu); |
| 253 | } |
| 254 | } |
| 255 | |
| 256 | static inline void gic_clear_pending(GICState *s, int irq, int cpu) |
| 257 | { |
| 258 | if (gic_is_vcpu(cpu)) { |
| 259 | uint32_t *entry = gic_get_lr_entry(s, irq, cpu); |
| 260 | GICH_LR_CLEAR_PENDING(*entry); |
| 261 | } else { |
| 262 | /* Clear pending state for both level and edge triggered |
| 263 | * interrupts. (level triggered interrupts with an active line |
| 264 | * remain pending, see gic_test_pending) |
| 265 | */ |
| 266 | GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK |
| 267 | : (1 << cpu)); |
| 268 | } |
| 269 | } |
| 270 | |
| 271 | static inline void gic_set_active(GICState *s, int irq, int cpu) |
| 272 | { |
| 273 | if (gic_is_vcpu(cpu)) { |
| 274 | uint32_t *entry = gic_get_lr_entry(s, irq, cpu); |
| 275 | GICH_LR_SET_ACTIVE(*entry); |
| 276 | } else { |
| 277 | GIC_DIST_SET_ACTIVE(irq, 1 << cpu); |
| 278 | } |
| 279 | } |
| 280 | |
| 281 | static inline void gic_clear_active(GICState *s, int irq, int cpu) |
| 282 | { |
| 283 | if (gic_is_vcpu(cpu)) { |
| 284 | uint32_t *entry = gic_get_lr_entry(s, irq, cpu); |
| 285 | GICH_LR_CLEAR_ACTIVE(*entry); |
| 286 | |
| 287 | if (GICH_LR_HW(*entry)) { |
| 288 | /* Hardware interrupt. We must forward the deactivation request to |
| 289 | * the distributor. |
| 290 | */ |
| 291 | int phys_irq = GICH_LR_PHYS_ID(*entry); |
| 292 | int rcpu = gic_get_vcpu_real_id(cpu); |
| 293 | |
| 294 | if (phys_irq < GIC_NR_SGIS || phys_irq >= GIC_MAXIRQ) { |
| 295 | /* UNPREDICTABLE behaviour, we choose to ignore the request */ |
| 296 | return; |
| 297 | } |
| 298 | |
| 299 | /* This is equivalent to a NS write to DIR on the physical CPU |
| 300 | * interface. Hence group0 interrupt deactivation is ignored if |
| 301 | * the GIC is secure. |
| 302 | */ |
| 303 | if (!s->security_extn || GIC_DIST_TEST_GROUP(phys_irq, 1 << rcpu)) { |
| 304 | GIC_DIST_CLEAR_ACTIVE(phys_irq, 1 << rcpu); |
| 305 | } |
| 306 | } |
| 307 | } else { |
| 308 | GIC_DIST_CLEAR_ACTIVE(irq, 1 << cpu); |
| 309 | } |
| 310 | } |
| 311 | |
| 312 | static inline int gic_get_priority(GICState *s, int irq, int cpu) |
| 313 | { |
| 314 | if (gic_is_vcpu(cpu)) { |
| 315 | uint32_t *entry = gic_get_lr_entry(s, irq, cpu); |
| 316 | return GICH_LR_PRIORITY(*entry); |
| 317 | } else { |
| 318 | return GIC_DIST_GET_PRIORITY(irq, cpu); |
| 319 | } |
| 320 | } |
| 321 | |
Markus Armbruster | 175de52 | 2016-06-29 15:29:06 +0200 | [diff] [blame] | 322 | #endif /* QEMU_ARM_GIC_INTERNAL_H */ |