bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Tiny Code Generator for QEMU |
| 3 | * |
| 4 | * Copyright (c) 2008 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 24 | |
| 25 | #ifndef NDEBUG |
| 26 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 27 | "%rax", |
| 28 | "%rcx", |
| 29 | "%rdx", |
| 30 | "%rbx", |
| 31 | "%rsp", |
| 32 | "%rbp", |
| 33 | "%rsi", |
| 34 | "%rdi", |
| 35 | "%r8", |
| 36 | "%r9", |
| 37 | "%r10", |
| 38 | "%r11", |
| 39 | "%r12", |
| 40 | "%r13", |
| 41 | "%r14", |
| 42 | "%r15", |
| 43 | }; |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 44 | #endif |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 45 | |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 46 | static const int tcg_target_reg_alloc_order[] = { |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 47 | TCG_REG_RBP, |
| 48 | TCG_REG_RBX, |
| 49 | TCG_REG_R12, |
| 50 | TCG_REG_R13, |
| 51 | TCG_REG_R14, |
| 52 | TCG_REG_R15, |
aurel32 | 79d342d | 2009-04-05 20:08:50 +0000 | [diff] [blame] | 53 | TCG_REG_R10, |
| 54 | TCG_REG_R11, |
| 55 | TCG_REG_R9, |
| 56 | TCG_REG_R8, |
| 57 | TCG_REG_RCX, |
| 58 | TCG_REG_RDX, |
| 59 | TCG_REG_RSI, |
| 60 | TCG_REG_RDI, |
| 61 | TCG_REG_RAX, |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 62 | }; |
| 63 | |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 64 | static const int tcg_target_call_iarg_regs[6] = { |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 65 | TCG_REG_RDI, |
| 66 | TCG_REG_RSI, |
| 67 | TCG_REG_RDX, |
| 68 | TCG_REG_RCX, |
| 69 | TCG_REG_R8, |
| 70 | TCG_REG_R9, |
| 71 | }; |
| 72 | |
blueswir1 | d4a9eb1 | 2008-10-05 09:59:14 +0000 | [diff] [blame] | 73 | static const int tcg_target_call_oarg_regs[2] = { |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 74 | TCG_REG_RAX, |
| 75 | TCG_REG_RDX |
| 76 | }; |
| 77 | |
bellard | b03cce8 | 2008-05-10 10:52:05 +0000 | [diff] [blame] | 78 | static uint8_t *tb_ret_addr; |
| 79 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 80 | static void patch_reloc(uint8_t *code_ptr, int type, |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 81 | tcg_target_long value, tcg_target_long addend) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 82 | { |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 83 | value += addend; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 84 | switch(type) { |
| 85 | case R_X86_64_32: |
| 86 | if (value != (uint32_t)value) |
| 87 | tcg_abort(); |
| 88 | *(uint32_t *)code_ptr = value; |
| 89 | break; |
| 90 | case R_X86_64_32S: |
| 91 | if (value != (int32_t)value) |
| 92 | tcg_abort(); |
| 93 | *(uint32_t *)code_ptr = value; |
| 94 | break; |
| 95 | case R_386_PC32: |
| 96 | value -= (long)code_ptr; |
| 97 | if (value != (int32_t)value) |
| 98 | tcg_abort(); |
| 99 | *(uint32_t *)code_ptr = value; |
| 100 | break; |
| 101 | default: |
| 102 | tcg_abort(); |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | /* maximum number of register used for input function arguments */ |
| 107 | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
| 108 | { |
| 109 | return 6; |
| 110 | } |
| 111 | |
| 112 | /* parse target specific constraints */ |
blueswir1 | 8fcd369 | 2008-08-17 20:26:25 +0000 | [diff] [blame] | 113 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 114 | { |
| 115 | const char *ct_str; |
| 116 | |
| 117 | ct_str = *pct_str; |
| 118 | switch(ct_str[0]) { |
| 119 | case 'a': |
| 120 | ct->ct |= TCG_CT_REG; |
| 121 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX); |
| 122 | break; |
| 123 | case 'b': |
| 124 | ct->ct |= TCG_CT_REG; |
| 125 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX); |
| 126 | break; |
| 127 | case 'c': |
| 128 | ct->ct |= TCG_CT_REG; |
| 129 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX); |
| 130 | break; |
| 131 | case 'd': |
| 132 | ct->ct |= TCG_CT_REG; |
| 133 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX); |
| 134 | break; |
| 135 | case 'S': |
| 136 | ct->ct |= TCG_CT_REG; |
| 137 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI); |
| 138 | break; |
| 139 | case 'D': |
| 140 | ct->ct |= TCG_CT_REG; |
| 141 | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI); |
| 142 | break; |
| 143 | case 'q': |
| 144 | ct->ct |= TCG_CT_REG; |
| 145 | tcg_regset_set32(ct->u.regs, 0, 0xf); |
| 146 | break; |
| 147 | case 'r': |
| 148 | ct->ct |= TCG_CT_REG; |
| 149 | tcg_regset_set32(ct->u.regs, 0, 0xffff); |
| 150 | break; |
| 151 | case 'L': /* qemu_ld/st constraint */ |
| 152 | ct->ct |= TCG_CT_REG; |
| 153 | tcg_regset_set32(ct->u.regs, 0, 0xffff); |
| 154 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI); |
| 155 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI); |
| 156 | break; |
| 157 | case 'e': |
| 158 | ct->ct |= TCG_CT_CONST_S32; |
| 159 | break; |
| 160 | case 'Z': |
| 161 | ct->ct |= TCG_CT_CONST_U32; |
| 162 | break; |
| 163 | default: |
| 164 | return -1; |
| 165 | } |
| 166 | ct_str++; |
| 167 | *pct_str = ct_str; |
| 168 | return 0; |
| 169 | } |
| 170 | |
| 171 | /* test if a constant matches the constraint */ |
| 172 | static inline int tcg_target_const_match(tcg_target_long val, |
| 173 | const TCGArgConstraint *arg_ct) |
| 174 | { |
| 175 | int ct; |
| 176 | ct = arg_ct->ct; |
| 177 | if (ct & TCG_CT_CONST) |
| 178 | return 1; |
| 179 | else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) |
| 180 | return 1; |
| 181 | else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) |
| 182 | return 1; |
| 183 | else |
| 184 | return 0; |
| 185 | } |
| 186 | |
| 187 | #define ARITH_ADD 0 |
| 188 | #define ARITH_OR 1 |
| 189 | #define ARITH_ADC 2 |
| 190 | #define ARITH_SBB 3 |
| 191 | #define ARITH_AND 4 |
| 192 | #define ARITH_SUB 5 |
| 193 | #define ARITH_XOR 6 |
| 194 | #define ARITH_CMP 7 |
| 195 | |
aurel32 | d42f183 | 2009-03-09 18:50:53 +0000 | [diff] [blame] | 196 | #define SHIFT_ROL 0 |
| 197 | #define SHIFT_ROR 1 |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 198 | #define SHIFT_SHL 4 |
| 199 | #define SHIFT_SHR 5 |
| 200 | #define SHIFT_SAR 7 |
| 201 | |
| 202 | #define JCC_JMP (-1) |
| 203 | #define JCC_JO 0x0 |
| 204 | #define JCC_JNO 0x1 |
| 205 | #define JCC_JB 0x2 |
| 206 | #define JCC_JAE 0x3 |
| 207 | #define JCC_JE 0x4 |
| 208 | #define JCC_JNE 0x5 |
| 209 | #define JCC_JBE 0x6 |
| 210 | #define JCC_JA 0x7 |
| 211 | #define JCC_JS 0x8 |
| 212 | #define JCC_JNS 0x9 |
| 213 | #define JCC_JP 0xa |
| 214 | #define JCC_JNP 0xb |
| 215 | #define JCC_JL 0xc |
| 216 | #define JCC_JGE 0xd |
| 217 | #define JCC_JLE 0xe |
| 218 | #define JCC_JG 0xf |
| 219 | |
| 220 | #define P_EXT 0x100 /* 0x0f opcode prefix */ |
| 221 | #define P_REXW 0x200 /* set rex.w = 1 */ |
bellard | 3c3a1d2 | 2008-05-10 21:42:05 +0000 | [diff] [blame] | 222 | #define P_REXB 0x400 /* force rex use for byte registers */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 223 | |
| 224 | static const uint8_t tcg_cond_to_jcc[10] = { |
| 225 | [TCG_COND_EQ] = JCC_JE, |
| 226 | [TCG_COND_NE] = JCC_JNE, |
| 227 | [TCG_COND_LT] = JCC_JL, |
| 228 | [TCG_COND_GE] = JCC_JGE, |
| 229 | [TCG_COND_LE] = JCC_JLE, |
| 230 | [TCG_COND_GT] = JCC_JG, |
| 231 | [TCG_COND_LTU] = JCC_JB, |
| 232 | [TCG_COND_GEU] = JCC_JAE, |
| 233 | [TCG_COND_LEU] = JCC_JBE, |
| 234 | [TCG_COND_GTU] = JCC_JA, |
| 235 | }; |
| 236 | |
| 237 | static inline void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) |
| 238 | { |
| 239 | int rex; |
| 240 | rex = ((opc >> 6) & 0x8) | ((r >> 1) & 0x4) | |
| 241 | ((x >> 2) & 2) | ((rm >> 3) & 1); |
bellard | 3375984 | 2008-05-10 21:58:28 +0000 | [diff] [blame] | 242 | if (rex || (opc & P_REXB)) { |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 243 | tcg_out8(s, rex | 0x40); |
| 244 | } |
| 245 | if (opc & P_EXT) |
| 246 | tcg_out8(s, 0x0f); |
blueswir1 | 9e622b1 | 2009-03-07 15:46:23 +0000 | [diff] [blame] | 247 | tcg_out8(s, opc & 0xff); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) |
| 251 | { |
| 252 | tcg_out_opc(s, opc, r, rm, 0); |
| 253 | tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7)); |
| 254 | } |
| 255 | |
| 256 | /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */ |
| 257 | static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, |
| 258 | tcg_target_long offset) |
| 259 | { |
| 260 | if (rm < 0) { |
| 261 | tcg_target_long val; |
| 262 | tcg_out_opc(s, opc, r, 0, 0); |
| 263 | val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1)); |
| 264 | if (val == (int32_t)val) { |
| 265 | /* eip relative */ |
| 266 | tcg_out8(s, 0x05 | ((r & 7) << 3)); |
| 267 | tcg_out32(s, val); |
| 268 | } else if (offset == (int32_t)offset) { |
| 269 | tcg_out8(s, 0x04 | ((r & 7) << 3)); |
| 270 | tcg_out8(s, 0x25); /* sib */ |
| 271 | tcg_out32(s, offset); |
| 272 | } else { |
| 273 | tcg_abort(); |
| 274 | } |
| 275 | } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
| 276 | tcg_out_opc(s, opc, r, rm, 0); |
| 277 | if ((rm & 7) == TCG_REG_RSP) { |
| 278 | tcg_out8(s, 0x04 | ((r & 7) << 3)); |
| 279 | tcg_out8(s, 0x24); |
| 280 | } else { |
| 281 | tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7)); |
| 282 | } |
| 283 | } else if ((int8_t)offset == offset) { |
| 284 | tcg_out_opc(s, opc, r, rm, 0); |
| 285 | if ((rm & 7) == TCG_REG_RSP) { |
| 286 | tcg_out8(s, 0x44 | ((r & 7) << 3)); |
| 287 | tcg_out8(s, 0x24); |
| 288 | } else { |
| 289 | tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7)); |
| 290 | } |
| 291 | tcg_out8(s, offset); |
| 292 | } else { |
| 293 | tcg_out_opc(s, opc, r, rm, 0); |
| 294 | if ((rm & 7) == TCG_REG_RSP) { |
| 295 | tcg_out8(s, 0x84 | ((r & 7) << 3)); |
| 296 | tcg_out8(s, 0x24); |
| 297 | } else { |
| 298 | tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7)); |
| 299 | } |
| 300 | tcg_out32(s, offset); |
| 301 | } |
| 302 | } |
| 303 | |
blueswir1 | bffd92f | 2008-02-29 19:36:08 +0000 | [diff] [blame] | 304 | #if defined(CONFIG_SOFTMMU) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 305 | /* XXX: incomplete. index must be different from ESP */ |
| 306 | static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm, |
| 307 | int index, int shift, |
| 308 | tcg_target_long offset) |
| 309 | { |
| 310 | int mod; |
| 311 | if (rm == -1) |
| 312 | tcg_abort(); |
| 313 | if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
| 314 | mod = 0; |
| 315 | } else if (offset == (int8_t)offset) { |
| 316 | mod = 0x40; |
| 317 | } else if (offset == (int32_t)offset) { |
| 318 | mod = 0x80; |
| 319 | } else { |
| 320 | tcg_abort(); |
| 321 | } |
| 322 | if (index == -1) { |
| 323 | tcg_out_opc(s, opc, r, rm, 0); |
| 324 | if ((rm & 7) == TCG_REG_RSP) { |
| 325 | tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
| 326 | tcg_out8(s, 0x04 | (rm & 7)); |
| 327 | } else { |
| 328 | tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7)); |
| 329 | } |
| 330 | } else { |
| 331 | tcg_out_opc(s, opc, r, rm, index); |
| 332 | tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
| 333 | tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7)); |
| 334 | } |
| 335 | if (mod == 0x40) { |
| 336 | tcg_out8(s, offset); |
| 337 | } else if (mod == 0x80) { |
| 338 | tcg_out32(s, offset); |
| 339 | } |
| 340 | } |
blueswir1 | bffd92f | 2008-02-29 19:36:08 +0000 | [diff] [blame] | 341 | #endif |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 342 | |
| 343 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
| 344 | { |
| 345 | tcg_out_modrm(s, 0x8b | P_REXW, ret, arg); |
| 346 | } |
| 347 | |
| 348 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
| 349 | int ret, tcg_target_long arg) |
| 350 | { |
| 351 | if (arg == 0) { |
| 352 | tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */ |
| 353 | } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { |
| 354 | tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0); |
| 355 | tcg_out32(s, arg); |
| 356 | } else if (arg == (int32_t)arg) { |
| 357 | tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret); |
| 358 | tcg_out32(s, arg); |
| 359 | } else { |
| 360 | tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0); |
| 361 | tcg_out32(s, arg); |
| 362 | tcg_out32(s, arg >> 32); |
| 363 | } |
| 364 | } |
| 365 | |
malc | abb6ae2 | 2009-09-03 04:20:01 +0400 | [diff] [blame] | 366 | static void tcg_out_goto(TCGContext *s, int call, uint8_t *target) |
| 367 | { |
| 368 | int32_t disp; |
| 369 | |
| 370 | disp = target - s->code_ptr - 5; |
| 371 | if (disp == (target - s->code_ptr - 5)) { |
| 372 | tcg_out8(s, call ? 0xe8 : 0xe9); |
| 373 | tcg_out32(s, disp); |
| 374 | } else { |
| 375 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (tcg_target_long) target); |
| 376 | tcg_out_modrm(s, 0xff, call ? 2 : 4, TCG_REG_R10); |
| 377 | } |
| 378 | } |
| 379 | |
blueswir1 | e4d5434 | 2008-03-13 17:34:19 +0000 | [diff] [blame] | 380 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 381 | int arg1, tcg_target_long arg2) |
| 382 | { |
blueswir1 | e4d5434 | 2008-03-13 17:34:19 +0000 | [diff] [blame] | 383 | if (type == TCG_TYPE_I32) |
| 384 | tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */ |
| 385 | else |
| 386 | tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 387 | } |
| 388 | |
blueswir1 | e4d5434 | 2008-03-13 17:34:19 +0000 | [diff] [blame] | 389 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 390 | int arg1, tcg_target_long arg2) |
| 391 | { |
blueswir1 | e4d5434 | 2008-03-13 17:34:19 +0000 | [diff] [blame] | 392 | if (type == TCG_TYPE_I32) |
| 393 | tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */ |
| 394 | else |
| 395 | tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */ |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 396 | } |
| 397 | |
| 398 | static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val) |
| 399 | { |
| 400 | if (val == (int8_t)val) { |
| 401 | tcg_out_modrm(s, 0x83, c, r0); |
| 402 | tcg_out8(s, val); |
pbrook | 733fef0 | 2008-09-07 18:07:39 +0000 | [diff] [blame] | 403 | } else if (c == ARITH_AND && val == 0xffu) { |
| 404 | /* movzbl */ |
| 405 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, r0, r0); |
| 406 | } else if (c == ARITH_AND && val == 0xffffu) { |
| 407 | /* movzwl */ |
| 408 | tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 409 | } else { |
| 410 | tcg_out_modrm(s, 0x81, c, r0); |
| 411 | tcg_out32(s, val); |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) |
| 416 | { |
| 417 | if (val == (int8_t)val) { |
| 418 | tcg_out_modrm(s, 0x83 | P_REXW, c, r0); |
| 419 | tcg_out8(s, val); |
pbrook | 733fef0 | 2008-09-07 18:07:39 +0000 | [diff] [blame] | 420 | } else if (c == ARITH_AND && val == 0xffu) { |
| 421 | /* movzbl */ |
| 422 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, r0, r0); |
| 423 | } else if (c == ARITH_AND && val == 0xffffu) { |
| 424 | /* movzwl */ |
| 425 | tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, r0, r0); |
| 426 | } else if (c == ARITH_AND && val == 0xffffffffu) { |
| 427 | /* 32-bit mov zero extends */ |
| 428 | tcg_out_modrm(s, 0x8b, r0, r0); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 429 | } else if (val == (int32_t)val) { |
| 430 | tcg_out_modrm(s, 0x81 | P_REXW, c, r0); |
| 431 | tcg_out32(s, val); |
| 432 | } else if (c == ARITH_AND && val == (uint32_t)val) { |
| 433 | tcg_out_modrm(s, 0x81, c, r0); |
| 434 | tcg_out32(s, val); |
| 435 | } else { |
| 436 | tcg_abort(); |
| 437 | } |
| 438 | } |
| 439 | |
blueswir1 | 8fcd369 | 2008-08-17 20:26:25 +0000 | [diff] [blame] | 440 | static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 441 | { |
| 442 | if (val != 0) |
| 443 | tgen_arithi64(s, ARITH_ADD, reg, val); |
| 444 | } |
| 445 | |
| 446 | static void tcg_out_jxx(TCGContext *s, int opc, int label_index) |
| 447 | { |
| 448 | int32_t val, val1; |
| 449 | TCGLabel *l = &s->labels[label_index]; |
| 450 | |
| 451 | if (l->has_value) { |
| 452 | val = l->u.value - (tcg_target_long)s->code_ptr; |
| 453 | val1 = val - 2; |
| 454 | if ((int8_t)val1 == val1) { |
| 455 | if (opc == -1) |
| 456 | tcg_out8(s, 0xeb); |
| 457 | else |
| 458 | tcg_out8(s, 0x70 + opc); |
| 459 | tcg_out8(s, val1); |
| 460 | } else { |
| 461 | if (opc == -1) { |
| 462 | tcg_out8(s, 0xe9); |
| 463 | tcg_out32(s, val - 5); |
| 464 | } else { |
| 465 | tcg_out8(s, 0x0f); |
| 466 | tcg_out8(s, 0x80 + opc); |
| 467 | tcg_out32(s, val - 6); |
| 468 | } |
| 469 | } |
| 470 | } else { |
| 471 | if (opc == -1) { |
| 472 | tcg_out8(s, 0xe9); |
| 473 | } else { |
| 474 | tcg_out8(s, 0x0f); |
| 475 | tcg_out8(s, 0x80 + opc); |
| 476 | } |
| 477 | tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4); |
pbrook | 623e265 | 2008-02-10 14:09:09 +0000 | [diff] [blame] | 478 | s->code_ptr += 4; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 479 | } |
| 480 | } |
| 481 | |
| 482 | static void tcg_out_brcond(TCGContext *s, int cond, |
| 483 | TCGArg arg1, TCGArg arg2, int const_arg2, |
| 484 | int label_index, int rexw) |
| 485 | { |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 486 | if (const_arg2) { |
| 487 | if (arg2 == 0) { |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 488 | /* test r, r */ |
| 489 | tcg_out_modrm(s, 0x85 | rexw, arg1, arg1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 490 | } else { |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 491 | if (rexw) |
| 492 | tgen_arithi64(s, ARITH_CMP, arg1, arg2); |
| 493 | else |
| 494 | tgen_arithi32(s, ARITH_CMP, arg1, arg2); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 495 | } |
| 496 | } else { |
bellard | bb210e7 | 2008-02-03 21:06:23 +0000 | [diff] [blame] | 497 | tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 498 | } |
bellard | 560f92c | 2008-05-25 18:49:06 +0000 | [diff] [blame] | 499 | tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 500 | } |
| 501 | |
| 502 | #if defined(CONFIG_SOFTMMU) |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 503 | |
blueswir1 | 79383c9 | 2008-08-30 09:51:20 +0000 | [diff] [blame] | 504 | #include "../../softmmu_defs.h" |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 505 | |
| 506 | static void *qemu_ld_helpers[4] = { |
| 507 | __ldb_mmu, |
| 508 | __ldw_mmu, |
| 509 | __ldl_mmu, |
| 510 | __ldq_mmu, |
| 511 | }; |
| 512 | |
| 513 | static void *qemu_st_helpers[4] = { |
| 514 | __stb_mmu, |
| 515 | __stw_mmu, |
| 516 | __stl_mmu, |
| 517 | __stq_mmu, |
| 518 | }; |
| 519 | #endif |
| 520 | |
| 521 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
| 522 | int opc) |
| 523 | { |
| 524 | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw; |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 525 | int32_t offset; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 526 | #if defined(CONFIG_SOFTMMU) |
| 527 | uint8_t *label1_ptr, *label2_ptr; |
| 528 | #endif |
| 529 | |
| 530 | data_reg = *args++; |
| 531 | addr_reg = *args++; |
| 532 | mem_index = *args; |
| 533 | s_bits = opc & 3; |
| 534 | |
| 535 | r0 = TCG_REG_RDI; |
| 536 | r1 = TCG_REG_RSI; |
| 537 | |
| 538 | #if TARGET_LONG_BITS == 32 |
| 539 | rexw = 0; |
| 540 | #else |
| 541 | rexw = P_REXW; |
| 542 | #endif |
| 543 | #if defined(CONFIG_SOFTMMU) |
| 544 | /* mov */ |
| 545 | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg); |
| 546 | |
| 547 | /* mov */ |
| 548 | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg); |
| 549 | |
| 550 | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
| 551 | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
| 552 | |
| 553 | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
| 554 | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
| 555 | |
| 556 | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
| 557 | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); |
| 558 | |
| 559 | /* lea offset(r1, env), r1 */ |
| 560 | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
| 561 | offsetof(CPUState, tlb_table[mem_index][0].addr_read)); |
| 562 | |
| 563 | /* cmp 0(r1), r0 */ |
| 564 | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
| 565 | |
| 566 | /* mov */ |
| 567 | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg); |
| 568 | |
| 569 | /* je label1 */ |
| 570 | tcg_out8(s, 0x70 + JCC_JE); |
| 571 | label1_ptr = s->code_ptr; |
| 572 | s->code_ptr++; |
| 573 | |
| 574 | /* XXX: move that code at the end of the TB */ |
| 575 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index); |
malc | abb6ae2 | 2009-09-03 04:20:01 +0400 | [diff] [blame] | 576 | tcg_out_goto(s, 1, qemu_ld_helpers[s_bits]); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 577 | |
| 578 | switch(opc) { |
| 579 | case 0 | 4: |
| 580 | /* movsbq */ |
| 581 | tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX); |
| 582 | break; |
| 583 | case 1 | 4: |
| 584 | /* movswq */ |
| 585 | tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX); |
| 586 | break; |
| 587 | case 2 | 4: |
| 588 | /* movslq */ |
| 589 | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX); |
| 590 | break; |
| 591 | case 0: |
aurel32 | 9db3ba4 | 2008-12-13 18:57:21 +0000 | [diff] [blame] | 592 | /* movzbq */ |
| 593 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX); |
| 594 | break; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 595 | case 1: |
aurel32 | 9db3ba4 | 2008-12-13 18:57:21 +0000 | [diff] [blame] | 596 | /* movzwq */ |
| 597 | tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX); |
| 598 | break; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 599 | case 2: |
| 600 | default: |
| 601 | /* movl */ |
| 602 | tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX); |
| 603 | break; |
| 604 | case 3: |
| 605 | tcg_out_mov(s, data_reg, TCG_REG_RAX); |
| 606 | break; |
| 607 | } |
| 608 | |
| 609 | /* jmp label2 */ |
| 610 | tcg_out8(s, 0xeb); |
| 611 | label2_ptr = s->code_ptr; |
| 612 | s->code_ptr++; |
| 613 | |
| 614 | /* label1: */ |
| 615 | *label1_ptr = s->code_ptr - label1_ptr - 1; |
| 616 | |
| 617 | /* add x(r1), r0 */ |
| 618 | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) - |
| 619 | offsetof(CPUTLBEntry, addr_read)); |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 620 | offset = 0; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 621 | #else |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 622 | if (GUEST_BASE == (int32_t)GUEST_BASE) { |
| 623 | r0 = addr_reg; |
| 624 | offset = GUEST_BASE; |
| 625 | } else { |
| 626 | offset = 0; |
| 627 | /* movq $GUEST_BASE, r0 */ |
| 628 | tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
| 629 | tcg_out32(s, GUEST_BASE); |
| 630 | tcg_out32(s, GUEST_BASE >> 32); |
| 631 | /* addq addr_reg, r0 */ |
| 632 | tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0); |
| 633 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 634 | #endif |
| 635 | |
| 636 | #ifdef TARGET_WORDS_BIGENDIAN |
| 637 | bswap = 1; |
| 638 | #else |
| 639 | bswap = 0; |
| 640 | #endif |
| 641 | switch(opc) { |
| 642 | case 0: |
| 643 | /* movzbl */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 644 | tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 645 | break; |
| 646 | case 0 | 4: |
| 647 | /* movsbX */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 648 | tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 649 | break; |
| 650 | case 1: |
| 651 | /* movzwl */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 652 | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 653 | if (bswap) { |
| 654 | /* rolw $8, data_reg */ |
| 655 | tcg_out8(s, 0x66); |
| 656 | tcg_out_modrm(s, 0xc1, 0, data_reg); |
| 657 | tcg_out8(s, 8); |
| 658 | } |
| 659 | break; |
| 660 | case 1 | 4: |
| 661 | if (bswap) { |
| 662 | /* movzwl */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 663 | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 664 | /* rolw $8, data_reg */ |
| 665 | tcg_out8(s, 0x66); |
| 666 | tcg_out_modrm(s, 0xc1, 0, data_reg); |
| 667 | tcg_out8(s, 8); |
| 668 | |
| 669 | /* movswX data_reg, data_reg */ |
| 670 | tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg); |
| 671 | } else { |
| 672 | /* movswX */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 673 | tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 674 | } |
| 675 | break; |
| 676 | case 2: |
| 677 | /* movl (r0), data_reg */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 678 | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 679 | if (bswap) { |
| 680 | /* bswap */ |
| 681 | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
| 682 | } |
| 683 | break; |
| 684 | case 2 | 4: |
| 685 | if (bswap) { |
| 686 | /* movl (r0), data_reg */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 687 | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 688 | /* bswap */ |
| 689 | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
| 690 | /* movslq */ |
| 691 | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg); |
| 692 | } else { |
| 693 | /* movslq */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 694 | tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 695 | } |
| 696 | break; |
| 697 | case 3: |
| 698 | /* movq (r0), data_reg */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 699 | tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 700 | if (bswap) { |
| 701 | /* bswap */ |
| 702 | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0); |
| 703 | } |
| 704 | break; |
| 705 | default: |
| 706 | tcg_abort(); |
| 707 | } |
| 708 | |
| 709 | #if defined(CONFIG_SOFTMMU) |
| 710 | /* label2: */ |
| 711 | *label2_ptr = s->code_ptr - label2_ptr - 1; |
| 712 | #endif |
| 713 | } |
| 714 | |
| 715 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
| 716 | int opc) |
| 717 | { |
| 718 | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw; |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 719 | int32_t offset; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 720 | #if defined(CONFIG_SOFTMMU) |
| 721 | uint8_t *label1_ptr, *label2_ptr; |
| 722 | #endif |
| 723 | |
| 724 | data_reg = *args++; |
| 725 | addr_reg = *args++; |
| 726 | mem_index = *args; |
| 727 | |
| 728 | s_bits = opc; |
| 729 | |
| 730 | r0 = TCG_REG_RDI; |
| 731 | r1 = TCG_REG_RSI; |
| 732 | |
| 733 | #if TARGET_LONG_BITS == 32 |
| 734 | rexw = 0; |
| 735 | #else |
| 736 | rexw = P_REXW; |
| 737 | #endif |
| 738 | #if defined(CONFIG_SOFTMMU) |
| 739 | /* mov */ |
| 740 | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg); |
| 741 | |
| 742 | /* mov */ |
| 743 | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg); |
| 744 | |
| 745 | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
| 746 | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
| 747 | |
| 748 | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
| 749 | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
| 750 | |
| 751 | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
| 752 | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); |
| 753 | |
| 754 | /* lea offset(r1, env), r1 */ |
| 755 | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
| 756 | offsetof(CPUState, tlb_table[mem_index][0].addr_write)); |
| 757 | |
| 758 | /* cmp 0(r1), r0 */ |
| 759 | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
| 760 | |
| 761 | /* mov */ |
| 762 | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg); |
| 763 | |
| 764 | /* je label1 */ |
| 765 | tcg_out8(s, 0x70 + JCC_JE); |
| 766 | label1_ptr = s->code_ptr; |
| 767 | s->code_ptr++; |
| 768 | |
| 769 | /* XXX: move that code at the end of the TB */ |
| 770 | switch(opc) { |
| 771 | case 0: |
| 772 | /* movzbl */ |
bellard | 3c3a1d2 | 2008-05-10 21:42:05 +0000 | [diff] [blame] | 773 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB, TCG_REG_RSI, data_reg); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 774 | break; |
| 775 | case 1: |
| 776 | /* movzwl */ |
| 777 | tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg); |
| 778 | break; |
| 779 | case 2: |
| 780 | /* movl */ |
| 781 | tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg); |
| 782 | break; |
| 783 | default: |
| 784 | case 3: |
| 785 | tcg_out_mov(s, TCG_REG_RSI, data_reg); |
| 786 | break; |
| 787 | } |
| 788 | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index); |
malc | abb6ae2 | 2009-09-03 04:20:01 +0400 | [diff] [blame] | 789 | tcg_out_goto(s, 1, qemu_st_helpers[s_bits]); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 790 | |
| 791 | /* jmp label2 */ |
| 792 | tcg_out8(s, 0xeb); |
| 793 | label2_ptr = s->code_ptr; |
| 794 | s->code_ptr++; |
| 795 | |
| 796 | /* label1: */ |
| 797 | *label1_ptr = s->code_ptr - label1_ptr - 1; |
| 798 | |
| 799 | /* add x(r1), r0 */ |
| 800 | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) - |
| 801 | offsetof(CPUTLBEntry, addr_write)); |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 802 | offset = 0; |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 803 | #else |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 804 | if (GUEST_BASE == (int32_t)GUEST_BASE) { |
| 805 | r0 = addr_reg; |
| 806 | offset = GUEST_BASE; |
| 807 | } else { |
| 808 | offset = 0; |
| 809 | /* movq $GUEST_BASE, r0 */ |
| 810 | tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
| 811 | tcg_out32(s, GUEST_BASE); |
| 812 | tcg_out32(s, GUEST_BASE >> 32); |
| 813 | /* addq addr_reg, r0 */ |
| 814 | tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0); |
| 815 | } |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 816 | #endif |
| 817 | |
| 818 | #ifdef TARGET_WORDS_BIGENDIAN |
| 819 | bswap = 1; |
| 820 | #else |
| 821 | bswap = 0; |
| 822 | #endif |
| 823 | switch(opc) { |
| 824 | case 0: |
| 825 | /* movb */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 826 | tcg_out_modrm_offset(s, 0x88 | P_REXB, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 827 | break; |
| 828 | case 1: |
| 829 | if (bswap) { |
| 830 | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
| 831 | tcg_out8(s, 0x66); /* rolw $8, %ecx */ |
| 832 | tcg_out_modrm(s, 0xc1, 0, r1); |
| 833 | tcg_out8(s, 8); |
| 834 | data_reg = r1; |
| 835 | } |
| 836 | /* movw */ |
| 837 | tcg_out8(s, 0x66); |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 838 | tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 839 | break; |
| 840 | case 2: |
| 841 | if (bswap) { |
| 842 | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
| 843 | /* bswap data_reg */ |
| 844 | tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0); |
| 845 | data_reg = r1; |
| 846 | } |
| 847 | /* movl */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 848 | tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 849 | break; |
| 850 | case 3: |
| 851 | if (bswap) { |
| 852 | tcg_out_mov(s, r1, data_reg); |
| 853 | /* bswap data_reg */ |
| 854 | tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0); |
| 855 | data_reg = r1; |
| 856 | } |
| 857 | /* movq */ |
Paul Brook | 379f669 | 2009-07-17 12:48:08 +0100 | [diff] [blame] | 858 | tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 859 | break; |
| 860 | default: |
| 861 | tcg_abort(); |
| 862 | } |
| 863 | |
| 864 | #if defined(CONFIG_SOFTMMU) |
| 865 | /* label2: */ |
| 866 | *label2_ptr = s->code_ptr - label2_ptr - 1; |
| 867 | #endif |
| 868 | } |
| 869 | |
| 870 | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
| 871 | const int *const_args) |
| 872 | { |
| 873 | int c; |
| 874 | |
| 875 | switch(opc) { |
| 876 | case INDEX_op_exit_tb: |
| 877 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]); |
malc | abb6ae2 | 2009-09-03 04:20:01 +0400 | [diff] [blame] | 878 | tcg_out_goto(s, 0, tb_ret_addr); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 879 | break; |
| 880 | case INDEX_op_goto_tb: |
| 881 | if (s->tb_jmp_offset) { |
| 882 | /* direct jump method */ |
| 883 | tcg_out8(s, 0xe9); /* jmp im */ |
| 884 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; |
| 885 | tcg_out32(s, 0); |
| 886 | } else { |
| 887 | /* indirect jump method */ |
| 888 | /* jmp Ev */ |
| 889 | tcg_out_modrm_offset(s, 0xff, 4, -1, |
| 890 | (tcg_target_long)(s->tb_next + |
| 891 | args[0])); |
| 892 | } |
| 893 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; |
| 894 | break; |
| 895 | case INDEX_op_call: |
| 896 | if (const_args[0]) { |
malc | abb6ae2 | 2009-09-03 04:20:01 +0400 | [diff] [blame] | 897 | tcg_out_goto(s, 1, (void *) args[0]); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 898 | } else { |
| 899 | tcg_out_modrm(s, 0xff, 2, args[0]); |
| 900 | } |
| 901 | break; |
| 902 | case INDEX_op_jmp: |
| 903 | if (const_args[0]) { |
malc | abb6ae2 | 2009-09-03 04:20:01 +0400 | [diff] [blame] | 904 | tcg_out_goto(s, 0, (void *) args[0]); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 905 | } else { |
| 906 | tcg_out_modrm(s, 0xff, 4, args[0]); |
| 907 | } |
| 908 | break; |
| 909 | case INDEX_op_br: |
| 910 | tcg_out_jxx(s, JCC_JMP, args[0]); |
| 911 | break; |
| 912 | case INDEX_op_movi_i32: |
| 913 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
| 914 | break; |
| 915 | case INDEX_op_movi_i64: |
| 916 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
| 917 | break; |
| 918 | case INDEX_op_ld8u_i32: |
| 919 | case INDEX_op_ld8u_i64: |
| 920 | /* movzbl */ |
| 921 | tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]); |
| 922 | break; |
| 923 | case INDEX_op_ld8s_i32: |
| 924 | /* movsbl */ |
| 925 | tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]); |
| 926 | break; |
| 927 | case INDEX_op_ld8s_i64: |
| 928 | /* movsbq */ |
| 929 | tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]); |
| 930 | break; |
| 931 | case INDEX_op_ld16u_i32: |
| 932 | case INDEX_op_ld16u_i64: |
| 933 | /* movzwl */ |
| 934 | tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]); |
| 935 | break; |
| 936 | case INDEX_op_ld16s_i32: |
| 937 | /* movswl */ |
| 938 | tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]); |
| 939 | break; |
| 940 | case INDEX_op_ld16s_i64: |
| 941 | /* movswq */ |
| 942 | tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]); |
| 943 | break; |
| 944 | case INDEX_op_ld_i32: |
| 945 | case INDEX_op_ld32u_i64: |
| 946 | /* movl */ |
| 947 | tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]); |
| 948 | break; |
| 949 | case INDEX_op_ld32s_i64: |
| 950 | /* movslq */ |
| 951 | tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]); |
| 952 | break; |
| 953 | case INDEX_op_ld_i64: |
| 954 | /* movq */ |
| 955 | tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]); |
| 956 | break; |
| 957 | |
| 958 | case INDEX_op_st8_i32: |
| 959 | case INDEX_op_st8_i64: |
| 960 | /* movb */ |
bellard | 3c3a1d2 | 2008-05-10 21:42:05 +0000 | [diff] [blame] | 961 | tcg_out_modrm_offset(s, 0x88 | P_REXB, args[0], args[1], args[2]); |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 962 | break; |
| 963 | case INDEX_op_st16_i32: |
| 964 | case INDEX_op_st16_i64: |
| 965 | /* movw */ |
| 966 | tcg_out8(s, 0x66); |
| 967 | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
| 968 | break; |
| 969 | case INDEX_op_st_i32: |
| 970 | case INDEX_op_st32_i64: |
| 971 | /* movl */ |
| 972 | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
| 973 | break; |
| 974 | case INDEX_op_st_i64: |
| 975 | /* movq */ |
| 976 | tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]); |
| 977 | break; |
| 978 | |
| 979 | case INDEX_op_sub_i32: |
| 980 | c = ARITH_SUB; |
| 981 | goto gen_arith32; |
| 982 | case INDEX_op_and_i32: |
| 983 | c = ARITH_AND; |
| 984 | goto gen_arith32; |
| 985 | case INDEX_op_or_i32: |
| 986 | c = ARITH_OR; |
| 987 | goto gen_arith32; |
| 988 | case INDEX_op_xor_i32: |
| 989 | c = ARITH_XOR; |
| 990 | goto gen_arith32; |
| 991 | case INDEX_op_add_i32: |
| 992 | c = ARITH_ADD; |
| 993 | gen_arith32: |
| 994 | if (const_args[2]) { |
| 995 | tgen_arithi32(s, c, args[0], args[2]); |
| 996 | } else { |
| 997 | tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]); |
| 998 | } |
| 999 | break; |
| 1000 | |
| 1001 | case INDEX_op_sub_i64: |
| 1002 | c = ARITH_SUB; |
| 1003 | goto gen_arith64; |
| 1004 | case INDEX_op_and_i64: |
| 1005 | c = ARITH_AND; |
| 1006 | goto gen_arith64; |
| 1007 | case INDEX_op_or_i64: |
| 1008 | c = ARITH_OR; |
| 1009 | goto gen_arith64; |
| 1010 | case INDEX_op_xor_i64: |
| 1011 | c = ARITH_XOR; |
| 1012 | goto gen_arith64; |
| 1013 | case INDEX_op_add_i64: |
| 1014 | c = ARITH_ADD; |
| 1015 | gen_arith64: |
| 1016 | if (const_args[2]) { |
| 1017 | tgen_arithi64(s, c, args[0], args[2]); |
| 1018 | } else { |
| 1019 | tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]); |
| 1020 | } |
| 1021 | break; |
| 1022 | |
| 1023 | case INDEX_op_mul_i32: |
| 1024 | if (const_args[2]) { |
| 1025 | int32_t val; |
| 1026 | val = args[2]; |
| 1027 | if (val == (int8_t)val) { |
| 1028 | tcg_out_modrm(s, 0x6b, args[0], args[0]); |
| 1029 | tcg_out8(s, val); |
| 1030 | } else { |
| 1031 | tcg_out_modrm(s, 0x69, args[0], args[0]); |
| 1032 | tcg_out32(s, val); |
| 1033 | } |
| 1034 | } else { |
| 1035 | tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]); |
| 1036 | } |
| 1037 | break; |
| 1038 | case INDEX_op_mul_i64: |
| 1039 | if (const_args[2]) { |
| 1040 | int32_t val; |
| 1041 | val = args[2]; |
| 1042 | if (val == (int8_t)val) { |
| 1043 | tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]); |
| 1044 | tcg_out8(s, val); |
| 1045 | } else { |
| 1046 | tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]); |
| 1047 | tcg_out32(s, val); |
| 1048 | } |
| 1049 | } else { |
| 1050 | tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]); |
| 1051 | } |
| 1052 | break; |
| 1053 | case INDEX_op_div2_i32: |
| 1054 | tcg_out_modrm(s, 0xf7, 7, args[4]); |
| 1055 | break; |
| 1056 | case INDEX_op_divu2_i32: |
| 1057 | tcg_out_modrm(s, 0xf7, 6, args[4]); |
| 1058 | break; |
| 1059 | case INDEX_op_div2_i64: |
| 1060 | tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]); |
| 1061 | break; |
| 1062 | case INDEX_op_divu2_i64: |
| 1063 | tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]); |
| 1064 | break; |
| 1065 | |
| 1066 | case INDEX_op_shl_i32: |
| 1067 | c = SHIFT_SHL; |
| 1068 | gen_shift32: |
| 1069 | if (const_args[2]) { |
| 1070 | if (args[2] == 1) { |
| 1071 | tcg_out_modrm(s, 0xd1, c, args[0]); |
| 1072 | } else { |
| 1073 | tcg_out_modrm(s, 0xc1, c, args[0]); |
| 1074 | tcg_out8(s, args[2]); |
| 1075 | } |
| 1076 | } else { |
| 1077 | tcg_out_modrm(s, 0xd3, c, args[0]); |
| 1078 | } |
| 1079 | break; |
| 1080 | case INDEX_op_shr_i32: |
| 1081 | c = SHIFT_SHR; |
| 1082 | goto gen_shift32; |
| 1083 | case INDEX_op_sar_i32: |
| 1084 | c = SHIFT_SAR; |
| 1085 | goto gen_shift32; |
aurel32 | d42f183 | 2009-03-09 18:50:53 +0000 | [diff] [blame] | 1086 | case INDEX_op_rotl_i32: |
| 1087 | c = SHIFT_ROL; |
| 1088 | goto gen_shift32; |
| 1089 | case INDEX_op_rotr_i32: |
| 1090 | c = SHIFT_ROR; |
| 1091 | goto gen_shift32; |
| 1092 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1093 | case INDEX_op_shl_i64: |
| 1094 | c = SHIFT_SHL; |
| 1095 | gen_shift64: |
| 1096 | if (const_args[2]) { |
| 1097 | if (args[2] == 1) { |
| 1098 | tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]); |
| 1099 | } else { |
| 1100 | tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]); |
| 1101 | tcg_out8(s, args[2]); |
| 1102 | } |
| 1103 | } else { |
| 1104 | tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]); |
| 1105 | } |
| 1106 | break; |
| 1107 | case INDEX_op_shr_i64: |
| 1108 | c = SHIFT_SHR; |
| 1109 | goto gen_shift64; |
| 1110 | case INDEX_op_sar_i64: |
| 1111 | c = SHIFT_SAR; |
| 1112 | goto gen_shift64; |
aurel32 | d42f183 | 2009-03-09 18:50:53 +0000 | [diff] [blame] | 1113 | case INDEX_op_rotl_i64: |
| 1114 | c = SHIFT_ROL; |
| 1115 | goto gen_shift64; |
| 1116 | case INDEX_op_rotr_i64: |
| 1117 | c = SHIFT_ROR; |
| 1118 | goto gen_shift64; |
| 1119 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1120 | case INDEX_op_brcond_i32: |
| 1121 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
| 1122 | args[3], 0); |
| 1123 | break; |
| 1124 | case INDEX_op_brcond_i64: |
| 1125 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
| 1126 | args[3], P_REXW); |
| 1127 | break; |
| 1128 | |
aurel32 | 86dbdd4 | 2009-03-13 09:35:55 +0000 | [diff] [blame] | 1129 | case INDEX_op_bswap16_i32: |
| 1130 | case INDEX_op_bswap16_i64: |
| 1131 | tcg_out8(s, 0x66); |
| 1132 | tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]); |
| 1133 | tcg_out8(s, 8); |
| 1134 | break; |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1135 | case INDEX_op_bswap32_i32: |
aurel32 | 86dbdd4 | 2009-03-13 09:35:55 +0000 | [diff] [blame] | 1136 | case INDEX_op_bswap32_i64: |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1137 | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0); |
| 1138 | break; |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1139 | case INDEX_op_bswap64_i64: |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1140 | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0); |
| 1141 | break; |
| 1142 | |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1143 | case INDEX_op_neg_i32: |
| 1144 | tcg_out_modrm(s, 0xf7, 3, args[0]); |
| 1145 | break; |
| 1146 | case INDEX_op_neg_i64: |
| 1147 | tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]); |
| 1148 | break; |
| 1149 | |
aurel32 | d260428 | 2009-03-09 22:35:13 +0000 | [diff] [blame] | 1150 | case INDEX_op_not_i32: |
| 1151 | tcg_out_modrm(s, 0xf7, 2, args[0]); |
| 1152 | break; |
| 1153 | case INDEX_op_not_i64: |
| 1154 | tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]); |
| 1155 | break; |
| 1156 | |
pbrook | b6d1715 | 2008-09-07 17:45:15 +0000 | [diff] [blame] | 1157 | case INDEX_op_ext8s_i32: |
| 1158 | tcg_out_modrm(s, 0xbe | P_EXT | P_REXB, args[0], args[1]); |
| 1159 | break; |
| 1160 | case INDEX_op_ext16s_i32: |
| 1161 | tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); |
| 1162 | break; |
| 1163 | case INDEX_op_ext8s_i64: |
| 1164 | tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]); |
| 1165 | break; |
| 1166 | case INDEX_op_ext16s_i64: |
| 1167 | tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]); |
| 1168 | break; |
| 1169 | case INDEX_op_ext32s_i64: |
| 1170 | tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]); |
| 1171 | break; |
| 1172 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1173 | case INDEX_op_qemu_ld8u: |
| 1174 | tcg_out_qemu_ld(s, args, 0); |
| 1175 | break; |
| 1176 | case INDEX_op_qemu_ld8s: |
| 1177 | tcg_out_qemu_ld(s, args, 0 | 4); |
| 1178 | break; |
| 1179 | case INDEX_op_qemu_ld16u: |
| 1180 | tcg_out_qemu_ld(s, args, 1); |
| 1181 | break; |
| 1182 | case INDEX_op_qemu_ld16s: |
| 1183 | tcg_out_qemu_ld(s, args, 1 | 4); |
| 1184 | break; |
| 1185 | case INDEX_op_qemu_ld32u: |
| 1186 | tcg_out_qemu_ld(s, args, 2); |
| 1187 | break; |
| 1188 | case INDEX_op_qemu_ld32s: |
| 1189 | tcg_out_qemu_ld(s, args, 2 | 4); |
| 1190 | break; |
| 1191 | case INDEX_op_qemu_ld64: |
| 1192 | tcg_out_qemu_ld(s, args, 3); |
| 1193 | break; |
| 1194 | |
| 1195 | case INDEX_op_qemu_st8: |
| 1196 | tcg_out_qemu_st(s, args, 0); |
| 1197 | break; |
| 1198 | case INDEX_op_qemu_st16: |
| 1199 | tcg_out_qemu_st(s, args, 1); |
| 1200 | break; |
| 1201 | case INDEX_op_qemu_st32: |
| 1202 | tcg_out_qemu_st(s, args, 2); |
| 1203 | break; |
| 1204 | case INDEX_op_qemu_st64: |
| 1205 | tcg_out_qemu_st(s, args, 3); |
| 1206 | break; |
| 1207 | |
| 1208 | default: |
| 1209 | tcg_abort(); |
| 1210 | } |
| 1211 | } |
| 1212 | |
bellard | b03cce8 | 2008-05-10 10:52:05 +0000 | [diff] [blame] | 1213 | static int tcg_target_callee_save_regs[] = { |
bellard | b03cce8 | 2008-05-10 10:52:05 +0000 | [diff] [blame] | 1214 | TCG_REG_RBP, |
| 1215 | TCG_REG_RBX, |
| 1216 | TCG_REG_R12, |
| 1217 | TCG_REG_R13, |
| 1218 | /* TCG_REG_R14, */ /* currently used for the global env, so no |
| 1219 | need to save */ |
| 1220 | TCG_REG_R15, |
| 1221 | }; |
| 1222 | |
| 1223 | static inline void tcg_out_push(TCGContext *s, int reg) |
| 1224 | { |
| 1225 | tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0); |
| 1226 | } |
| 1227 | |
| 1228 | static inline void tcg_out_pop(TCGContext *s, int reg) |
| 1229 | { |
| 1230 | tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0); |
| 1231 | } |
| 1232 | |
| 1233 | /* Generate global QEMU prologue and epilogue code */ |
| 1234 | void tcg_target_qemu_prologue(TCGContext *s) |
| 1235 | { |
| 1236 | int i, frame_size, push_size, stack_addend; |
| 1237 | |
| 1238 | /* TB prologue */ |
| 1239 | /* save all callee saved registers */ |
| 1240 | for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { |
| 1241 | tcg_out_push(s, tcg_target_callee_save_regs[i]); |
| 1242 | |
| 1243 | } |
| 1244 | /* reserve some stack space */ |
| 1245 | push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8; |
| 1246 | frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE; |
| 1247 | frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) & |
| 1248 | ~(TCG_TARGET_STACK_ALIGN - 1); |
| 1249 | stack_addend = frame_size - push_size; |
| 1250 | tcg_out_addi(s, TCG_REG_RSP, -stack_addend); |
| 1251 | |
| 1252 | tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */ |
| 1253 | |
| 1254 | /* TB epilogue */ |
| 1255 | tb_ret_addr = s->code_ptr; |
| 1256 | tcg_out_addi(s, TCG_REG_RSP, stack_addend); |
| 1257 | for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { |
| 1258 | tcg_out_pop(s, tcg_target_callee_save_regs[i]); |
| 1259 | } |
| 1260 | tcg_out8(s, 0xc3); /* ret */ |
| 1261 | } |
| 1262 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1263 | static const TCGTargetOpDef x86_64_op_defs[] = { |
| 1264 | { INDEX_op_exit_tb, { } }, |
| 1265 | { INDEX_op_goto_tb, { } }, |
| 1266 | { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */ |
| 1267 | { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */ |
| 1268 | { INDEX_op_br, { } }, |
| 1269 | |
| 1270 | { INDEX_op_mov_i32, { "r", "r" } }, |
| 1271 | { INDEX_op_movi_i32, { "r" } }, |
| 1272 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
| 1273 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
| 1274 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
| 1275 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
| 1276 | { INDEX_op_ld_i32, { "r", "r" } }, |
| 1277 | { INDEX_op_st8_i32, { "r", "r" } }, |
| 1278 | { INDEX_op_st16_i32, { "r", "r" } }, |
| 1279 | { INDEX_op_st_i32, { "r", "r" } }, |
| 1280 | |
| 1281 | { INDEX_op_add_i32, { "r", "0", "ri" } }, |
| 1282 | { INDEX_op_mul_i32, { "r", "0", "ri" } }, |
| 1283 | { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } }, |
| 1284 | { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } }, |
| 1285 | { INDEX_op_sub_i32, { "r", "0", "ri" } }, |
| 1286 | { INDEX_op_and_i32, { "r", "0", "ri" } }, |
| 1287 | { INDEX_op_or_i32, { "r", "0", "ri" } }, |
| 1288 | { INDEX_op_xor_i32, { "r", "0", "ri" } }, |
| 1289 | |
| 1290 | { INDEX_op_shl_i32, { "r", "0", "ci" } }, |
| 1291 | { INDEX_op_shr_i32, { "r", "0", "ci" } }, |
| 1292 | { INDEX_op_sar_i32, { "r", "0", "ci" } }, |
aurel32 | d42f183 | 2009-03-09 18:50:53 +0000 | [diff] [blame] | 1293 | { INDEX_op_rotl_i32, { "r", "0", "ci" } }, |
| 1294 | { INDEX_op_rotr_i32, { "r", "0", "ci" } }, |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1295 | |
| 1296 | { INDEX_op_brcond_i32, { "r", "ri" } }, |
| 1297 | |
| 1298 | { INDEX_op_mov_i64, { "r", "r" } }, |
| 1299 | { INDEX_op_movi_i64, { "r" } }, |
| 1300 | { INDEX_op_ld8u_i64, { "r", "r" } }, |
| 1301 | { INDEX_op_ld8s_i64, { "r", "r" } }, |
| 1302 | { INDEX_op_ld16u_i64, { "r", "r" } }, |
| 1303 | { INDEX_op_ld16s_i64, { "r", "r" } }, |
| 1304 | { INDEX_op_ld32u_i64, { "r", "r" } }, |
| 1305 | { INDEX_op_ld32s_i64, { "r", "r" } }, |
| 1306 | { INDEX_op_ld_i64, { "r", "r" } }, |
| 1307 | { INDEX_op_st8_i64, { "r", "r" } }, |
| 1308 | { INDEX_op_st16_i64, { "r", "r" } }, |
| 1309 | { INDEX_op_st32_i64, { "r", "r" } }, |
| 1310 | { INDEX_op_st_i64, { "r", "r" } }, |
| 1311 | |
| 1312 | { INDEX_op_add_i64, { "r", "0", "re" } }, |
| 1313 | { INDEX_op_mul_i64, { "r", "0", "re" } }, |
| 1314 | { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } }, |
| 1315 | { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } }, |
| 1316 | { INDEX_op_sub_i64, { "r", "0", "re" } }, |
| 1317 | { INDEX_op_and_i64, { "r", "0", "reZ" } }, |
| 1318 | { INDEX_op_or_i64, { "r", "0", "re" } }, |
| 1319 | { INDEX_op_xor_i64, { "r", "0", "re" } }, |
| 1320 | |
| 1321 | { INDEX_op_shl_i64, { "r", "0", "ci" } }, |
| 1322 | { INDEX_op_shr_i64, { "r", "0", "ci" } }, |
| 1323 | { INDEX_op_sar_i64, { "r", "0", "ci" } }, |
aurel32 | d42f183 | 2009-03-09 18:50:53 +0000 | [diff] [blame] | 1324 | { INDEX_op_rotl_i64, { "r", "0", "ci" } }, |
| 1325 | { INDEX_op_rotr_i64, { "r", "0", "ci" } }, |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1326 | |
| 1327 | { INDEX_op_brcond_i64, { "r", "re" } }, |
| 1328 | |
aurel32 | 86dbdd4 | 2009-03-13 09:35:55 +0000 | [diff] [blame] | 1329 | { INDEX_op_bswap16_i32, { "r", "0" } }, |
| 1330 | { INDEX_op_bswap16_i64, { "r", "0" } }, |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1331 | { INDEX_op_bswap32_i32, { "r", "0" } }, |
aurel32 | 86dbdd4 | 2009-03-13 09:35:55 +0000 | [diff] [blame] | 1332 | { INDEX_op_bswap32_i64, { "r", "0" } }, |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 1333 | { INDEX_op_bswap64_i64, { "r", "0" } }, |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1334 | |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 1335 | { INDEX_op_neg_i32, { "r", "0" } }, |
| 1336 | { INDEX_op_neg_i64, { "r", "0" } }, |
| 1337 | |
aurel32 | d260428 | 2009-03-09 22:35:13 +0000 | [diff] [blame] | 1338 | { INDEX_op_not_i32, { "r", "0" } }, |
| 1339 | { INDEX_op_not_i64, { "r", "0" } }, |
| 1340 | |
pbrook | b6d1715 | 2008-09-07 17:45:15 +0000 | [diff] [blame] | 1341 | { INDEX_op_ext8s_i32, { "r", "r"} }, |
| 1342 | { INDEX_op_ext16s_i32, { "r", "r"} }, |
| 1343 | { INDEX_op_ext8s_i64, { "r", "r"} }, |
| 1344 | { INDEX_op_ext16s_i64, { "r", "r"} }, |
| 1345 | { INDEX_op_ext32s_i64, { "r", "r"} }, |
| 1346 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1347 | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
| 1348 | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
| 1349 | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
| 1350 | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
| 1351 | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
| 1352 | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
| 1353 | { INDEX_op_qemu_ld64, { "r", "L" } }, |
| 1354 | |
| 1355 | { INDEX_op_qemu_st8, { "L", "L" } }, |
| 1356 | { INDEX_op_qemu_st16, { "L", "L" } }, |
| 1357 | { INDEX_op_qemu_st32, { "L", "L" } }, |
| 1358 | { INDEX_op_qemu_st64, { "L", "L", "L" } }, |
| 1359 | |
| 1360 | { -1 }, |
| 1361 | }; |
| 1362 | |
| 1363 | void tcg_target_init(TCGContext *s) |
| 1364 | { |
bellard | b03cce8 | 2008-05-10 10:52:05 +0000 | [diff] [blame] | 1365 | /* fail safe */ |
| 1366 | if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) |
| 1367 | tcg_abort(); |
| 1368 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1369 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); |
| 1370 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); |
| 1371 | tcg_regset_set32(tcg_target_call_clobber_regs, 0, |
| 1372 | (1 << TCG_REG_RDI) | |
| 1373 | (1 << TCG_REG_RSI) | |
| 1374 | (1 << TCG_REG_RDX) | |
| 1375 | (1 << TCG_REG_RCX) | |
| 1376 | (1 << TCG_REG_R8) | |
| 1377 | (1 << TCG_REG_R9) | |
| 1378 | (1 << TCG_REG_RAX) | |
| 1379 | (1 << TCG_REG_R10) | |
| 1380 | (1 << TCG_REG_R11)); |
| 1381 | |
| 1382 | tcg_regset_clear(s->reserved_regs); |
| 1383 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP); |
bellard | 3c3a1d2 | 2008-05-10 21:42:05 +0000 | [diff] [blame] | 1384 | |
bellard | c896fe2 | 2008-02-01 10:05:41 +0000 | [diff] [blame] | 1385 | tcg_add_target_add_op_defs(x86_64_op_defs); |
| 1386 | } |