blob: 60bbb00946e2a25453268bffbf2080299b763670 [file] [log] [blame]
bellarda541f292004-04-12 20:39:29 +00001/*
bellard819385c2005-10-30 16:58:32 +00002 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
ths5fafdf22007-09-16 21:08:06 +00003 *
blueswir13ccacc42007-04-14 13:01:31 +00004 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
ths5fafdf22007-09-16 21:08:06 +00005 *
bellarda541f292004-04-12 20:39:29 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
pbrook87ecb682007-11-17 17:14:51 +000024#include "hw.h"
25#include "nvram.h"
pbrook87ecb682007-11-17 17:14:51 +000026#include "qemu-timer.h"
27#include "sysemu.h"
Blue Swirld27cf0a2009-07-12 20:07:07 +000028#include "sysbus.h"
Blue Swirlf80237d2009-09-14 15:33:28 +000029#include "isa.h"
bellarda541f292004-04-12 20:39:29 +000030
bellard13ab5da2004-05-17 20:21:49 +000031//#define DEBUG_NVRAM
bellarda541f292004-04-12 20:39:29 +000032
bellard13ab5da2004-05-17 20:21:49 +000033#if defined(DEBUG_NVRAM)
Blue Swirl001faf32009-05-13 17:53:17 +000034#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
bellarda541f292004-04-12 20:39:29 +000035#else
Blue Swirl001faf32009-05-13 17:53:17 +000036#define NVRAM_PRINTF(fmt, ...) do { } while (0)
bellarda541f292004-04-12 20:39:29 +000037#endif
38
bellard819385c2005-10-30 16:58:32 +000039/*
blueswir14aed2c32007-12-29 09:05:30 +000040 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
bellard819385c2005-10-30 16:58:32 +000041 * alarm and a watchdog timer and related control registers. In the
42 * PPC platform there is also a nvram lock function.
43 */
Blue Swirl930f3fe2009-10-13 18:56:27 +000044
45/*
46 * Chipset docs:
47 * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
48 * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
49 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
50 */
51
Blue Swirl43a34702010-02-07 08:05:03 +000052struct M48t59State {
bellarda541f292004-04-12 20:39:29 +000053 /* Hardware parameters */
pbrookd537cf62007-04-07 18:14:41 +000054 qemu_irq IRQ;
Avi Kivity5a31cd62011-11-13 12:16:07 +020055 MemoryRegion iomem;
bellarda541f292004-04-12 20:39:29 +000056 uint32_t io_base;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +020057 uint32_t size;
bellarda541f292004-04-12 20:39:29 +000058 /* RTC management */
59 time_t time_offset;
60 time_t stop_time;
61 /* Alarm & watchdog */
balrogf6503052008-02-17 11:42:19 +000062 struct tm alarm;
bellarda541f292004-04-12 20:39:29 +000063 struct QEMUTimer *alrm_timer;
64 struct QEMUTimer *wd_timer;
65 /* NVRAM storage */
bellarda541f292004-04-12 20:39:29 +000066 uint8_t *buffer;
Blue Swirl42c812b2011-08-07 20:02:02 +000067 /* Model parameters */
68 uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
69 /* NVRAM storage */
70 uint16_t addr;
71 uint8_t lock;
bellardc5df0182004-04-12 20:54:52 +000072};
bellarda541f292004-04-12 20:39:29 +000073
Blue Swirlf80237d2009-09-14 15:33:28 +000074typedef struct M48t59ISAState {
75 ISADevice busdev;
Blue Swirl43a34702010-02-07 08:05:03 +000076 M48t59State state;
Richard Henderson9936d6e2011-08-15 15:33:40 -070077 MemoryRegion io;
Blue Swirlf80237d2009-09-14 15:33:28 +000078} M48t59ISAState;
79
80typedef struct M48t59SysBusState {
81 SysBusDevice busdev;
Blue Swirl43a34702010-02-07 08:05:03 +000082 M48t59State state;
Blue Swirlf80237d2009-09-14 15:33:28 +000083} M48t59SysBusState;
84
bellarda541f292004-04-12 20:39:29 +000085/* Fake timer functions */
bellarda541f292004-04-12 20:39:29 +000086
bellarda541f292004-04-12 20:39:29 +000087/* Alarm management */
88static void alarm_cb (void *opaque)
89{
balrogf6503052008-02-17 11:42:19 +000090 struct tm tm;
bellarda541f292004-04-12 20:39:29 +000091 uint64_t next_time;
Blue Swirl43a34702010-02-07 08:05:03 +000092 M48t59State *NVRAM = opaque;
bellarda541f292004-04-12 20:39:29 +000093
pbrookd537cf62007-04-07 18:14:41 +000094 qemu_set_irq(NVRAM->IRQ, 1);
ths5fafdf22007-09-16 21:08:06 +000095 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
bellarda541f292004-04-12 20:39:29 +000096 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
97 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
98 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
balrogf6503052008-02-17 11:42:19 +000099 /* Repeat once a month */
100 qemu_get_timedate(&tm, NVRAM->time_offset);
101 tm.tm_mon++;
102 if (tm.tm_mon == 13) {
103 tm.tm_mon = 1;
104 tm.tm_year++;
105 }
106 next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
bellarda541f292004-04-12 20:39:29 +0000107 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
108 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
109 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
110 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
balrogf6503052008-02-17 11:42:19 +0000111 /* Repeat once a day */
112 next_time = 24 * 60 * 60;
bellarda541f292004-04-12 20:39:29 +0000113 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
114 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
115 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
116 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
balrogf6503052008-02-17 11:42:19 +0000117 /* Repeat once an hour */
118 next_time = 60 * 60;
bellarda541f292004-04-12 20:39:29 +0000119 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
120 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
121 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
122 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
balrogf6503052008-02-17 11:42:19 +0000123 /* Repeat once a minute */
124 next_time = 60;
bellarda541f292004-04-12 20:39:29 +0000125 } else {
balrogf6503052008-02-17 11:42:19 +0000126 /* Repeat once a second */
127 next_time = 1;
bellarda541f292004-04-12 20:39:29 +0000128 }
Paolo Bonzini1d849502012-01-20 13:05:00 +0100129 qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) +
balrogf6503052008-02-17 11:42:19 +0000130 next_time * 1000);
pbrookd537cf62007-04-07 18:14:41 +0000131 qemu_set_irq(NVRAM->IRQ, 0);
bellarda541f292004-04-12 20:39:29 +0000132}
133
Blue Swirl43a34702010-02-07 08:05:03 +0000134static void set_alarm(M48t59State *NVRAM)
bellarda541f292004-04-12 20:39:29 +0000135{
balrogf6503052008-02-17 11:42:19 +0000136 int diff;
bellarda541f292004-04-12 20:39:29 +0000137 if (NVRAM->alrm_timer != NULL) {
138 qemu_del_timer(NVRAM->alrm_timer);
balrogf6503052008-02-17 11:42:19 +0000139 diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
140 if (diff > 0)
141 qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
bellarda541f292004-04-12 20:39:29 +0000142 }
bellarda541f292004-04-12 20:39:29 +0000143}
144
balrogf6503052008-02-17 11:42:19 +0000145/* RTC management helpers */
Blue Swirl43a34702010-02-07 08:05:03 +0000146static inline void get_time(M48t59State *NVRAM, struct tm *tm)
balrogf6503052008-02-17 11:42:19 +0000147{
148 qemu_get_timedate(tm, NVRAM->time_offset);
149}
150
Blue Swirl43a34702010-02-07 08:05:03 +0000151static void set_time(M48t59State *NVRAM, struct tm *tm)
balrogf6503052008-02-17 11:42:19 +0000152{
153 NVRAM->time_offset = qemu_timedate_diff(tm);
154 set_alarm(NVRAM);
155}
156
bellarda541f292004-04-12 20:39:29 +0000157/* Watchdog management */
158static void watchdog_cb (void *opaque)
159{
Blue Swirl43a34702010-02-07 08:05:03 +0000160 M48t59State *NVRAM = opaque;
bellarda541f292004-04-12 20:39:29 +0000161
162 NVRAM->buffer[0x1FF0] |= 0x80;
163 if (NVRAM->buffer[0x1FF7] & 0x80) {
164 NVRAM->buffer[0x1FF7] = 0x00;
165 NVRAM->buffer[0x1FFC] &= ~0x40;
bellard13ab5da2004-05-17 20:21:49 +0000166 /* May it be a hw CPU Reset instead ? */
bellardd7d02e32004-06-20 12:58:36 +0000167 qemu_system_reset_request();
bellarda541f292004-04-12 20:39:29 +0000168 } else {
pbrookd537cf62007-04-07 18:14:41 +0000169 qemu_set_irq(NVRAM->IRQ, 1);
170 qemu_set_irq(NVRAM->IRQ, 0);
bellarda541f292004-04-12 20:39:29 +0000171 }
172}
173
Blue Swirl43a34702010-02-07 08:05:03 +0000174static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
bellarda541f292004-04-12 20:39:29 +0000175{
176 uint64_t interval; /* in 1/16 seconds */
177
j_mayer868d5852007-09-30 01:29:07 +0000178 NVRAM->buffer[0x1FF0] &= ~0x80;
bellarda541f292004-04-12 20:39:29 +0000179 if (NVRAM->wd_timer != NULL) {
180 qemu_del_timer(NVRAM->wd_timer);
j_mayer868d5852007-09-30 01:29:07 +0000181 if (value != 0) {
182 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
183 qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
184 ((interval * 1000) >> 4));
185 }
bellarda541f292004-04-12 20:39:29 +0000186 }
187}
188
189/* Direct access to NVRAM */
j_mayer897b4c62007-10-28 23:33:05 +0000190void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
bellarda541f292004-04-12 20:39:29 +0000191{
Blue Swirl43a34702010-02-07 08:05:03 +0000192 M48t59State *NVRAM = opaque;
bellarda541f292004-04-12 20:39:29 +0000193 struct tm tm;
194 int tmp;
195
bellard819385c2005-10-30 16:58:32 +0000196 if (addr > 0x1FF8 && addr < 0x2000)
197 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
blueswir14aed2c32007-12-29 09:05:30 +0000198
199 /* check for NVRAM access */
200 if ((NVRAM->type == 2 && addr < 0x7f8) ||
201 (NVRAM->type == 8 && addr < 0x1ff8) ||
202 (NVRAM->type == 59 && addr < 0x1ff0))
bellard819385c2005-10-30 16:58:32 +0000203 goto do_write;
blueswir14aed2c32007-12-29 09:05:30 +0000204
205 /* TOD access */
bellard819385c2005-10-30 16:58:32 +0000206 switch (addr) {
bellarda541f292004-04-12 20:39:29 +0000207 case 0x1FF0:
208 /* flags register : read-only */
209 break;
210 case 0x1FF1:
211 /* unused */
212 break;
213 case 0x1FF2:
214 /* alarm seconds */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000215 tmp = from_bcd(val & 0x7F);
bellard819385c2005-10-30 16:58:32 +0000216 if (tmp >= 0 && tmp <= 59) {
balrogf6503052008-02-17 11:42:19 +0000217 NVRAM->alarm.tm_sec = tmp;
bellard819385c2005-10-30 16:58:32 +0000218 NVRAM->buffer[0x1FF2] = val;
balrogf6503052008-02-17 11:42:19 +0000219 set_alarm(NVRAM);
bellard819385c2005-10-30 16:58:32 +0000220 }
bellarda541f292004-04-12 20:39:29 +0000221 break;
222 case 0x1FF3:
223 /* alarm minutes */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000224 tmp = from_bcd(val & 0x7F);
bellard819385c2005-10-30 16:58:32 +0000225 if (tmp >= 0 && tmp <= 59) {
balrogf6503052008-02-17 11:42:19 +0000226 NVRAM->alarm.tm_min = tmp;
bellard819385c2005-10-30 16:58:32 +0000227 NVRAM->buffer[0x1FF3] = val;
balrogf6503052008-02-17 11:42:19 +0000228 set_alarm(NVRAM);
bellard819385c2005-10-30 16:58:32 +0000229 }
bellarda541f292004-04-12 20:39:29 +0000230 break;
231 case 0x1FF4:
232 /* alarm hours */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000233 tmp = from_bcd(val & 0x3F);
bellard819385c2005-10-30 16:58:32 +0000234 if (tmp >= 0 && tmp <= 23) {
balrogf6503052008-02-17 11:42:19 +0000235 NVRAM->alarm.tm_hour = tmp;
bellard819385c2005-10-30 16:58:32 +0000236 NVRAM->buffer[0x1FF4] = val;
balrogf6503052008-02-17 11:42:19 +0000237 set_alarm(NVRAM);
bellard819385c2005-10-30 16:58:32 +0000238 }
bellarda541f292004-04-12 20:39:29 +0000239 break;
240 case 0x1FF5:
241 /* alarm date */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000242 tmp = from_bcd(val & 0x1F);
bellard819385c2005-10-30 16:58:32 +0000243 if (tmp != 0) {
balrogf6503052008-02-17 11:42:19 +0000244 NVRAM->alarm.tm_mday = tmp;
bellard819385c2005-10-30 16:58:32 +0000245 NVRAM->buffer[0x1FF5] = val;
balrogf6503052008-02-17 11:42:19 +0000246 set_alarm(NVRAM);
bellard819385c2005-10-30 16:58:32 +0000247 }
bellarda541f292004-04-12 20:39:29 +0000248 break;
249 case 0x1FF6:
250 /* interrupts */
bellard819385c2005-10-30 16:58:32 +0000251 NVRAM->buffer[0x1FF6] = val;
bellarda541f292004-04-12 20:39:29 +0000252 break;
253 case 0x1FF7:
254 /* watchdog */
bellard819385c2005-10-30 16:58:32 +0000255 NVRAM->buffer[0x1FF7] = val;
256 set_up_watchdog(NVRAM, val);
bellarda541f292004-04-12 20:39:29 +0000257 break;
258 case 0x1FF8:
blueswir14aed2c32007-12-29 09:05:30 +0000259 case 0x07F8:
bellarda541f292004-04-12 20:39:29 +0000260 /* control */
blueswir14aed2c32007-12-29 09:05:30 +0000261 NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
bellarda541f292004-04-12 20:39:29 +0000262 break;
263 case 0x1FF9:
blueswir14aed2c32007-12-29 09:05:30 +0000264 case 0x07F9:
bellarda541f292004-04-12 20:39:29 +0000265 /* seconds (BCD) */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000266 tmp = from_bcd(val & 0x7F);
bellarda541f292004-04-12 20:39:29 +0000267 if (tmp >= 0 && tmp <= 59) {
268 get_time(NVRAM, &tm);
269 tm.tm_sec = tmp;
270 set_time(NVRAM, &tm);
271 }
balrogf6503052008-02-17 11:42:19 +0000272 if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
bellarda541f292004-04-12 20:39:29 +0000273 if (val & 0x80) {
274 NVRAM->stop_time = time(NULL);
275 } else {
276 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
277 NVRAM->stop_time = 0;
278 }
279 }
balrogf6503052008-02-17 11:42:19 +0000280 NVRAM->buffer[addr] = val & 0x80;
bellarda541f292004-04-12 20:39:29 +0000281 break;
282 case 0x1FFA:
blueswir14aed2c32007-12-29 09:05:30 +0000283 case 0x07FA:
bellarda541f292004-04-12 20:39:29 +0000284 /* minutes (BCD) */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000285 tmp = from_bcd(val & 0x7F);
bellarda541f292004-04-12 20:39:29 +0000286 if (tmp >= 0 && tmp <= 59) {
287 get_time(NVRAM, &tm);
288 tm.tm_min = tmp;
289 set_time(NVRAM, &tm);
290 }
291 break;
292 case 0x1FFB:
blueswir14aed2c32007-12-29 09:05:30 +0000293 case 0x07FB:
bellarda541f292004-04-12 20:39:29 +0000294 /* hours (BCD) */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000295 tmp = from_bcd(val & 0x3F);
bellarda541f292004-04-12 20:39:29 +0000296 if (tmp >= 0 && tmp <= 23) {
297 get_time(NVRAM, &tm);
298 tm.tm_hour = tmp;
299 set_time(NVRAM, &tm);
300 }
301 break;
302 case 0x1FFC:
blueswir14aed2c32007-12-29 09:05:30 +0000303 case 0x07FC:
bellarda541f292004-04-12 20:39:29 +0000304 /* day of the week / century */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000305 tmp = from_bcd(val & 0x07);
bellarda541f292004-04-12 20:39:29 +0000306 get_time(NVRAM, &tm);
307 tm.tm_wday = tmp;
308 set_time(NVRAM, &tm);
blueswir14aed2c32007-12-29 09:05:30 +0000309 NVRAM->buffer[addr] = val & 0x40;
bellarda541f292004-04-12 20:39:29 +0000310 break;
311 case 0x1FFD:
blueswir14aed2c32007-12-29 09:05:30 +0000312 case 0x07FD:
bellarda541f292004-04-12 20:39:29 +0000313 /* date */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000314 tmp = from_bcd(val & 0x1F);
bellarda541f292004-04-12 20:39:29 +0000315 if (tmp != 0) {
316 get_time(NVRAM, &tm);
317 tm.tm_mday = tmp;
318 set_time(NVRAM, &tm);
319 }
320 break;
321 case 0x1FFE:
blueswir14aed2c32007-12-29 09:05:30 +0000322 case 0x07FE:
bellarda541f292004-04-12 20:39:29 +0000323 /* month */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000324 tmp = from_bcd(val & 0x1F);
bellarda541f292004-04-12 20:39:29 +0000325 if (tmp >= 1 && tmp <= 12) {
326 get_time(NVRAM, &tm);
327 tm.tm_mon = tmp - 1;
328 set_time(NVRAM, &tm);
329 }
330 break;
331 case 0x1FFF:
blueswir14aed2c32007-12-29 09:05:30 +0000332 case 0x07FF:
bellarda541f292004-04-12 20:39:29 +0000333 /* year */
Paul Brookabd0c6b2009-11-20 00:03:47 +0000334 tmp = from_bcd(val);
bellarda541f292004-04-12 20:39:29 +0000335 if (tmp >= 0 && tmp <= 99) {
336 get_time(NVRAM, &tm);
bellard180b7002006-06-14 12:41:34 +0000337 if (NVRAM->type == 8)
Paul Brookabd0c6b2009-11-20 00:03:47 +0000338 tm.tm_year = from_bcd(val) + 68; // Base year is 1968
bellard180b7002006-06-14 12:41:34 +0000339 else
Paul Brookabd0c6b2009-11-20 00:03:47 +0000340 tm.tm_year = from_bcd(val);
bellarda541f292004-04-12 20:39:29 +0000341 set_time(NVRAM, &tm);
342 }
343 break;
344 default:
bellard13ab5da2004-05-17 20:21:49 +0000345 /* Check lock registers state */
bellard819385c2005-10-30 16:58:32 +0000346 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
bellard13ab5da2004-05-17 20:21:49 +0000347 break;
bellard819385c2005-10-30 16:58:32 +0000348 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
bellard13ab5da2004-05-17 20:21:49 +0000349 break;
bellard819385c2005-10-30 16:58:32 +0000350 do_write:
351 if (addr < NVRAM->size) {
352 NVRAM->buffer[addr] = val & 0xFF;
bellarda541f292004-04-12 20:39:29 +0000353 }
354 break;
355 }
356}
357
j_mayer897b4c62007-10-28 23:33:05 +0000358uint32_t m48t59_read (void *opaque, uint32_t addr)
bellarda541f292004-04-12 20:39:29 +0000359{
Blue Swirl43a34702010-02-07 08:05:03 +0000360 M48t59State *NVRAM = opaque;
bellarda541f292004-04-12 20:39:29 +0000361 struct tm tm;
362 uint32_t retval = 0xFF;
363
blueswir14aed2c32007-12-29 09:05:30 +0000364 /* check for NVRAM access */
365 if ((NVRAM->type == 2 && addr < 0x078f) ||
366 (NVRAM->type == 8 && addr < 0x1ff8) ||
367 (NVRAM->type == 59 && addr < 0x1ff0))
bellard819385c2005-10-30 16:58:32 +0000368 goto do_read;
blueswir14aed2c32007-12-29 09:05:30 +0000369
370 /* TOD access */
bellard819385c2005-10-30 16:58:32 +0000371 switch (addr) {
bellarda541f292004-04-12 20:39:29 +0000372 case 0x1FF0:
373 /* flags register */
374 goto do_read;
375 case 0x1FF1:
376 /* unused */
377 retval = 0;
378 break;
379 case 0x1FF2:
380 /* alarm seconds */
381 goto do_read;
382 case 0x1FF3:
383 /* alarm minutes */
384 goto do_read;
385 case 0x1FF4:
386 /* alarm hours */
387 goto do_read;
388 case 0x1FF5:
389 /* alarm date */
390 goto do_read;
391 case 0x1FF6:
392 /* interrupts */
393 goto do_read;
394 case 0x1FF7:
395 /* A read resets the watchdog */
396 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
397 goto do_read;
398 case 0x1FF8:
blueswir14aed2c32007-12-29 09:05:30 +0000399 case 0x07F8:
bellarda541f292004-04-12 20:39:29 +0000400 /* control */
401 goto do_read;
402 case 0x1FF9:
blueswir14aed2c32007-12-29 09:05:30 +0000403 case 0x07F9:
bellarda541f292004-04-12 20:39:29 +0000404 /* seconds (BCD) */
405 get_time(NVRAM, &tm);
Paul Brookabd0c6b2009-11-20 00:03:47 +0000406 retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
bellarda541f292004-04-12 20:39:29 +0000407 break;
408 case 0x1FFA:
blueswir14aed2c32007-12-29 09:05:30 +0000409 case 0x07FA:
bellarda541f292004-04-12 20:39:29 +0000410 /* minutes (BCD) */
411 get_time(NVRAM, &tm);
Paul Brookabd0c6b2009-11-20 00:03:47 +0000412 retval = to_bcd(tm.tm_min);
bellarda541f292004-04-12 20:39:29 +0000413 break;
414 case 0x1FFB:
blueswir14aed2c32007-12-29 09:05:30 +0000415 case 0x07FB:
bellarda541f292004-04-12 20:39:29 +0000416 /* hours (BCD) */
417 get_time(NVRAM, &tm);
Paul Brookabd0c6b2009-11-20 00:03:47 +0000418 retval = to_bcd(tm.tm_hour);
bellarda541f292004-04-12 20:39:29 +0000419 break;
420 case 0x1FFC:
blueswir14aed2c32007-12-29 09:05:30 +0000421 case 0x07FC:
bellarda541f292004-04-12 20:39:29 +0000422 /* day of the week / century */
423 get_time(NVRAM, &tm);
blueswir14aed2c32007-12-29 09:05:30 +0000424 retval = NVRAM->buffer[addr] | tm.tm_wday;
bellarda541f292004-04-12 20:39:29 +0000425 break;
426 case 0x1FFD:
blueswir14aed2c32007-12-29 09:05:30 +0000427 case 0x07FD:
bellarda541f292004-04-12 20:39:29 +0000428 /* date */
429 get_time(NVRAM, &tm);
Paul Brookabd0c6b2009-11-20 00:03:47 +0000430 retval = to_bcd(tm.tm_mday);
bellarda541f292004-04-12 20:39:29 +0000431 break;
432 case 0x1FFE:
blueswir14aed2c32007-12-29 09:05:30 +0000433 case 0x07FE:
bellarda541f292004-04-12 20:39:29 +0000434 /* month */
435 get_time(NVRAM, &tm);
Paul Brookabd0c6b2009-11-20 00:03:47 +0000436 retval = to_bcd(tm.tm_mon + 1);
bellarda541f292004-04-12 20:39:29 +0000437 break;
438 case 0x1FFF:
blueswir14aed2c32007-12-29 09:05:30 +0000439 case 0x07FF:
bellarda541f292004-04-12 20:39:29 +0000440 /* year */
441 get_time(NVRAM, &tm);
ths5fafdf22007-09-16 21:08:06 +0000442 if (NVRAM->type == 8)
Paul Brookabd0c6b2009-11-20 00:03:47 +0000443 retval = to_bcd(tm.tm_year - 68); // Base year is 1968
bellard180b7002006-06-14 12:41:34 +0000444 else
Paul Brookabd0c6b2009-11-20 00:03:47 +0000445 retval = to_bcd(tm.tm_year);
bellarda541f292004-04-12 20:39:29 +0000446 break;
447 default:
bellard13ab5da2004-05-17 20:21:49 +0000448 /* Check lock registers state */
bellard819385c2005-10-30 16:58:32 +0000449 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
bellard13ab5da2004-05-17 20:21:49 +0000450 break;
bellard819385c2005-10-30 16:58:32 +0000451 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
bellard13ab5da2004-05-17 20:21:49 +0000452 break;
bellard819385c2005-10-30 16:58:32 +0000453 do_read:
454 if (addr < NVRAM->size) {
455 retval = NVRAM->buffer[addr];
bellarda541f292004-04-12 20:39:29 +0000456 }
457 break;
458 }
bellard819385c2005-10-30 16:58:32 +0000459 if (addr > 0x1FF9 && addr < 0x2000)
blueswir19ed1e662007-12-29 09:03:43 +0000460 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
bellarda541f292004-04-12 20:39:29 +0000461
462 return retval;
463}
464
j_mayer897b4c62007-10-28 23:33:05 +0000465void m48t59_set_addr (void *opaque, uint32_t addr)
bellarda541f292004-04-12 20:39:29 +0000466{
Blue Swirl43a34702010-02-07 08:05:03 +0000467 M48t59State *NVRAM = opaque;
j_mayer897b4c62007-10-28 23:33:05 +0000468
bellarda541f292004-04-12 20:39:29 +0000469 NVRAM->addr = addr;
470}
471
j_mayer897b4c62007-10-28 23:33:05 +0000472void m48t59_toggle_lock (void *opaque, int lock)
bellard13ab5da2004-05-17 20:21:49 +0000473{
Blue Swirl43a34702010-02-07 08:05:03 +0000474 M48t59State *NVRAM = opaque;
j_mayer897b4c62007-10-28 23:33:05 +0000475
bellard13ab5da2004-05-17 20:21:49 +0000476 NVRAM->lock ^= 1 << lock;
477}
478
bellarda541f292004-04-12 20:39:29 +0000479/* IO access to NVRAM */
480static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
481{
Blue Swirl43a34702010-02-07 08:05:03 +0000482 M48t59State *NVRAM = opaque;
bellarda541f292004-04-12 20:39:29 +0000483
blueswir19ed1e662007-12-29 09:03:43 +0000484 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
bellarda541f292004-04-12 20:39:29 +0000485 switch (addr) {
486 case 0:
487 NVRAM->addr &= ~0x00FF;
488 NVRAM->addr |= val;
489 break;
490 case 1:
491 NVRAM->addr &= ~0xFF00;
492 NVRAM->addr |= val << 8;
493 break;
494 case 3:
Blue Swirlb1f88302011-10-15 08:05:18 +0000495 m48t59_write(NVRAM, NVRAM->addr, val);
bellarda541f292004-04-12 20:39:29 +0000496 NVRAM->addr = 0x0000;
497 break;
498 default:
499 break;
500 }
501}
502
503static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
504{
Blue Swirl43a34702010-02-07 08:05:03 +0000505 M48t59State *NVRAM = opaque;
bellard13ab5da2004-05-17 20:21:49 +0000506 uint32_t retval;
bellarda541f292004-04-12 20:39:29 +0000507
bellard13ab5da2004-05-17 20:21:49 +0000508 switch (addr) {
509 case 3:
bellard819385c2005-10-30 16:58:32 +0000510 retval = m48t59_read(NVRAM, NVRAM->addr);
bellard13ab5da2004-05-17 20:21:49 +0000511 break;
512 default:
513 retval = -1;
514 break;
515 }
blueswir19ed1e662007-12-29 09:03:43 +0000516 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
bellarda541f292004-04-12 20:39:29 +0000517
bellard13ab5da2004-05-17 20:21:49 +0000518 return retval;
bellarda541f292004-04-12 20:39:29 +0000519}
520
Anthony Liguoric227f092009-10-01 16:12:16 -0500521static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
bellarde1bb04f2004-06-21 16:49:53 +0000522{
Blue Swirl43a34702010-02-07 08:05:03 +0000523 M48t59State *NVRAM = opaque;
ths3b46e622007-09-17 08:09:54 +0000524
bellard819385c2005-10-30 16:58:32 +0000525 m48t59_write(NVRAM, addr, value & 0xff);
bellarde1bb04f2004-06-21 16:49:53 +0000526}
527
Anthony Liguoric227f092009-10-01 16:12:16 -0500528static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
bellarde1bb04f2004-06-21 16:49:53 +0000529{
Blue Swirl43a34702010-02-07 08:05:03 +0000530 M48t59State *NVRAM = opaque;
ths3b46e622007-09-17 08:09:54 +0000531
bellard819385c2005-10-30 16:58:32 +0000532 m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
533 m48t59_write(NVRAM, addr + 1, value & 0xff);
bellarde1bb04f2004-06-21 16:49:53 +0000534}
535
Anthony Liguoric227f092009-10-01 16:12:16 -0500536static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
bellarde1bb04f2004-06-21 16:49:53 +0000537{
Blue Swirl43a34702010-02-07 08:05:03 +0000538 M48t59State *NVRAM = opaque;
ths3b46e622007-09-17 08:09:54 +0000539
bellard819385c2005-10-30 16:58:32 +0000540 m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
541 m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
542 m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
543 m48t59_write(NVRAM, addr + 3, value & 0xff);
bellarde1bb04f2004-06-21 16:49:53 +0000544}
545
Anthony Liguoric227f092009-10-01 16:12:16 -0500546static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
bellarde1bb04f2004-06-21 16:49:53 +0000547{
Blue Swirl43a34702010-02-07 08:05:03 +0000548 M48t59State *NVRAM = opaque;
bellard819385c2005-10-30 16:58:32 +0000549 uint32_t retval;
ths3b46e622007-09-17 08:09:54 +0000550
bellard819385c2005-10-30 16:58:32 +0000551 retval = m48t59_read(NVRAM, addr);
bellarde1bb04f2004-06-21 16:49:53 +0000552 return retval;
553}
554
Anthony Liguoric227f092009-10-01 16:12:16 -0500555static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
bellarde1bb04f2004-06-21 16:49:53 +0000556{
Blue Swirl43a34702010-02-07 08:05:03 +0000557 M48t59State *NVRAM = opaque;
bellard819385c2005-10-30 16:58:32 +0000558 uint32_t retval;
ths3b46e622007-09-17 08:09:54 +0000559
bellard819385c2005-10-30 16:58:32 +0000560 retval = m48t59_read(NVRAM, addr) << 8;
561 retval |= m48t59_read(NVRAM, addr + 1);
bellarde1bb04f2004-06-21 16:49:53 +0000562 return retval;
563}
564
Anthony Liguoric227f092009-10-01 16:12:16 -0500565static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
bellarde1bb04f2004-06-21 16:49:53 +0000566{
Blue Swirl43a34702010-02-07 08:05:03 +0000567 M48t59State *NVRAM = opaque;
bellard819385c2005-10-30 16:58:32 +0000568 uint32_t retval;
bellarde1bb04f2004-06-21 16:49:53 +0000569
bellard819385c2005-10-30 16:58:32 +0000570 retval = m48t59_read(NVRAM, addr) << 24;
571 retval |= m48t59_read(NVRAM, addr + 1) << 16;
572 retval |= m48t59_read(NVRAM, addr + 2) << 8;
573 retval |= m48t59_read(NVRAM, addr + 3);
bellarde1bb04f2004-06-21 16:49:53 +0000574 return retval;
575}
576
Avi Kivity5a31cd62011-11-13 12:16:07 +0200577static const MemoryRegionOps nvram_ops = {
578 .old_mmio = {
579 .read = { nvram_readb, nvram_readw, nvram_readl, },
580 .write = { nvram_writeb, nvram_writew, nvram_writel, },
581 },
582 .endianness = DEVICE_NATIVE_ENDIAN,
bellarde1bb04f2004-06-21 16:49:53 +0000583};
bellard819385c2005-10-30 16:58:32 +0000584
Juan Quintelafd484ae2010-12-02 00:16:33 +0100585static const VMStateDescription vmstate_m48t59 = {
586 .name = "m48t59",
587 .version_id = 1,
588 .minimum_version_id = 1,
589 .minimum_version_id_old = 1,
590 .fields = (VMStateField[]) {
591 VMSTATE_UINT8(lock, M48t59State),
592 VMSTATE_UINT16(addr, M48t59State),
593 VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
594 VMSTATE_END_OF_LIST()
595 }
596};
blueswir13ccacc42007-04-14 13:01:31 +0000597
Blue Swirl43a34702010-02-07 08:05:03 +0000598static void m48t59_reset_common(M48t59State *NVRAM)
blueswir13ccacc42007-04-14 13:01:31 +0000599{
blueswir16e6b7362008-12-28 18:27:10 +0000600 NVRAM->addr = 0;
601 NVRAM->lock = 0;
blueswir13ccacc42007-04-14 13:01:31 +0000602 if (NVRAM->alrm_timer != NULL)
603 qemu_del_timer(NVRAM->alrm_timer);
604
605 if (NVRAM->wd_timer != NULL)
606 qemu_del_timer(NVRAM->wd_timer);
607}
608
Blue Swirl285e4682009-10-24 19:22:56 +0000609static void m48t59_reset_isa(DeviceState *d)
610{
611 M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
Blue Swirl43a34702010-02-07 08:05:03 +0000612 M48t59State *NVRAM = &isa->state;
Blue Swirl285e4682009-10-24 19:22:56 +0000613
614 m48t59_reset_common(NVRAM);
615}
616
617static void m48t59_reset_sysbus(DeviceState *d)
618{
619 M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
Blue Swirl43a34702010-02-07 08:05:03 +0000620 M48t59State *NVRAM = &sys->state;
Blue Swirl285e4682009-10-24 19:22:56 +0000621
622 m48t59_reset_common(NVRAM);
623}
624
Richard Henderson9936d6e2011-08-15 15:33:40 -0700625static const MemoryRegionPortio m48t59_portio[] = {
626 {0, 4, 1, .read = NVRAM_readb, .write = NVRAM_writeb },
627 PORTIO_END_OF_LIST(),
628};
629
630static const MemoryRegionOps m48t59_io_ops = {
631 .old_portio = m48t59_portio,
632};
633
bellarda541f292004-04-12 20:39:29 +0000634/* Initialisation routine */
Blue Swirl43a34702010-02-07 08:05:03 +0000635M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
636 uint32_t io_base, uint16_t size, int type)
bellarda541f292004-04-12 20:39:29 +0000637{
Blue Swirld27cf0a2009-07-12 20:07:07 +0000638 DeviceState *dev;
639 SysBusDevice *s;
Blue Swirlf80237d2009-09-14 15:33:28 +0000640 M48t59SysBusState *d;
Hervé Poussineau51f9b842011-01-02 19:44:49 +0100641 M48t59State *state;
bellarda541f292004-04-12 20:39:29 +0000642
Blue Swirld27cf0a2009-07-12 20:07:07 +0000643 dev = qdev_create(NULL, "m48t59");
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200644 qdev_prop_set_uint32(dev, "type", type);
645 qdev_prop_set_uint32(dev, "size", size);
646 qdev_prop_set_uint32(dev, "io_base", io_base);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200647 qdev_init_nofail(dev);
Blue Swirld27cf0a2009-07-12 20:07:07 +0000648 s = sysbus_from_qdev(dev);
Hervé Poussineau51f9b842011-01-02 19:44:49 +0100649 d = FROM_SYSBUS(M48t59SysBusState, s);
650 state = &d->state;
Blue Swirld27cf0a2009-07-12 20:07:07 +0000651 sysbus_connect_irq(s, 0, IRQ);
bellard819385c2005-10-30 16:58:32 +0000652 if (io_base != 0) {
Hervé Poussineau51f9b842011-01-02 19:44:49 +0100653 register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state);
654 register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state);
bellard819385c2005-10-30 16:58:32 +0000655 }
bellarde1bb04f2004-06-21 16:49:53 +0000656 if (mem_base != 0) {
Blue Swirld27cf0a2009-07-12 20:07:07 +0000657 sysbus_mmio_map(s, 0, mem_base);
bellarde1bb04f2004-06-21 16:49:53 +0000658 }
Blue Swirld27cf0a2009-07-12 20:07:07 +0000659
Hervé Poussineau51f9b842011-01-02 19:44:49 +0100660 return state;
Blue Swirld27cf0a2009-07-12 20:07:07 +0000661}
662
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100663M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
664 int type)
Blue Swirld27cf0a2009-07-12 20:07:07 +0000665{
Blue Swirlf80237d2009-09-14 15:33:28 +0000666 M48t59ISAState *d;
667 ISADevice *dev;
Blue Swirl43a34702010-02-07 08:05:03 +0000668 M48t59State *s;
Blue Swirld27cf0a2009-07-12 20:07:07 +0000669
Hervé Poussineau48a18b32011-12-15 22:09:51 +0100670 dev = isa_create(bus, "m48t59_isa");
Blue Swirlf80237d2009-09-14 15:33:28 +0000671 qdev_prop_set_uint32(&dev->qdev, "type", type);
672 qdev_prop_set_uint32(&dev->qdev, "size", size);
673 qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200674 qdev_init_nofail(&dev->qdev);
Blue Swirlf80237d2009-09-14 15:33:28 +0000675 d = DO_UPCAST(M48t59ISAState, busdev, dev);
676 s = &d->state;
677
Richard Henderson9936d6e2011-08-15 15:33:40 -0700678 memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4);
Blue Swirlf80237d2009-09-14 15:33:28 +0000679 if (io_base != 0) {
Richard Henderson9936d6e2011-08-15 15:33:40 -0700680 isa_register_ioport(dev, &d->io, io_base);
Blue Swirlf80237d2009-09-14 15:33:28 +0000681 }
682
683 return s;
684}
685
Blue Swirl43a34702010-02-07 08:05:03 +0000686static void m48t59_init_common(M48t59State *s)
Blue Swirlf80237d2009-09-14 15:33:28 +0000687{
Anthony Liguori7267c092011-08-20 22:09:37 -0500688 s->buffer = g_malloc0(s->size);
Blue Swirld27cf0a2009-07-12 20:07:07 +0000689 if (s->type == 59) {
Paolo Bonzini1d849502012-01-20 13:05:00 +0100690 s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s);
Paolo Bonzini74475452011-03-11 16:47:48 +0100691 s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
bellard819385c2005-10-30 16:58:32 +0000692 }
balrogf6503052008-02-17 11:42:19 +0000693 qemu_get_timedate(&s->alarm, 0);
bellard13ab5da2004-05-17 20:21:49 +0000694
Juan Quintelafd484ae2010-12-02 00:16:33 +0100695 vmstate_register(NULL, -1, &vmstate_m48t59, s);
Blue Swirlf80237d2009-09-14 15:33:28 +0000696}
697
698static int m48t59_init_isa1(ISADevice *dev)
699{
700 M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
Blue Swirl43a34702010-02-07 08:05:03 +0000701 M48t59State *s = &d->state;
Blue Swirlf80237d2009-09-14 15:33:28 +0000702
703 isa_init_irq(dev, &s->IRQ, 8);
704 m48t59_init_common(s);
705
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200706 return 0;
bellarda541f292004-04-12 20:39:29 +0000707}
Blue Swirld27cf0a2009-07-12 20:07:07 +0000708
Blue Swirlf80237d2009-09-14 15:33:28 +0000709static int m48t59_init1(SysBusDevice *dev)
710{
711 M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
Blue Swirl43a34702010-02-07 08:05:03 +0000712 M48t59State *s = &d->state;
Blue Swirlf80237d2009-09-14 15:33:28 +0000713
714 sysbus_init_irq(dev, &s->IRQ);
715
Avi Kivity5a31cd62011-11-13 12:16:07 +0200716 memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size);
Avi Kivity750ecd42011-11-27 11:38:10 +0200717 sysbus_init_mmio(dev, &s->iomem);
Blue Swirlf80237d2009-09-14 15:33:28 +0000718 m48t59_init_common(s);
719
720 return 0;
721}
722
Anthony Liguori39bffca2011-12-07 21:34:16 -0600723static Property m48t59_isa_properties[] = {
724 DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
725 DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1),
726 DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0),
727 DEFINE_PROP_END_OF_LIST(),
728};
729
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600730static void m48t59_init_class_isa1(ObjectClass *klass, void *data)
731{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600732 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600733 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
734 ic->init = m48t59_init_isa1;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600735 dc->no_user = 1;
736 dc->reset = m48t59_reset_isa;
737 dc->props = m48t59_isa_properties;
Anthony Liguori8f04ee02011-12-04 11:52:49 -0600738}
739
Anthony Liguori39bffca2011-12-07 21:34:16 -0600740static TypeInfo m48t59_isa_info = {
741 .name = "m48t59_isa",
742 .parent = TYPE_ISA_DEVICE,
743 .instance_size = sizeof(M48t59ISAState),
744 .class_init = m48t59_init_class_isa1,
Blue Swirlf80237d2009-09-14 15:33:28 +0000745};
746
Anthony Liguori999e12b2012-01-24 13:12:29 -0600747static Property m48t59_properties[] = {
748 DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
749 DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1),
750 DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0),
751 DEFINE_PROP_END_OF_LIST(),
752};
753
754static void m48t59_class_init(ObjectClass *klass, void *data)
755{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600756 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600757 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
758
759 k->init = m48t59_init1;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600760 dc->reset = m48t59_reset_sysbus;
761 dc->props = m48t59_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600762}
763
Anthony Liguori39bffca2011-12-07 21:34:16 -0600764static TypeInfo m48t59_info = {
765 .name = "m48t59",
766 .parent = TYPE_SYS_BUS_DEVICE,
767 .instance_size = sizeof(M48t59SysBusState),
768 .class_init = m48t59_class_init,
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200769};
770
Andreas Färber83f7d432012-02-09 15:20:55 +0100771static void m48t59_register_types(void)
Blue Swirld27cf0a2009-07-12 20:07:07 +0000772{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600773 type_register_static(&m48t59_info);
774 type_register_static(&m48t59_isa_info);
Blue Swirld27cf0a2009-07-12 20:07:07 +0000775}
776
Andreas Färber83f7d432012-02-09 15:20:55 +0100777type_init(m48t59_register_types)