bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1 | /* |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 2 | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
blueswir1 | 3ccacc4 | 2007-04-14 13:01:31 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 24 | #include "hw.h" |
| 25 | #include "nvram.h" |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 26 | #include "qemu-timer.h" |
| 27 | #include "sysemu.h" |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 28 | #include "sysbus.h" |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 29 | #include "isa.h" |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 30 | |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 31 | //#define DEBUG_NVRAM |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 32 | |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 33 | #if defined(DEBUG_NVRAM) |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 34 | #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 35 | #else |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 36 | #define NVRAM_PRINTF(fmt, ...) do { } while (0) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 37 | #endif |
| 38 | |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 39 | /* |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 40 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 41 | * alarm and a watchdog timer and related control registers. In the |
| 42 | * PPC platform there is also a nvram lock function. |
| 43 | */ |
Blue Swirl | 930f3fe | 2009-10-13 18:56:27 +0000 | [diff] [blame] | 44 | |
| 45 | /* |
| 46 | * Chipset docs: |
| 47 | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf |
| 48 | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf |
| 49 | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf |
| 50 | */ |
| 51 | |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 52 | struct M48t59State { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 53 | /* Hardware parameters */ |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 54 | qemu_irq IRQ; |
Avi Kivity | 5a31cd6 | 2011-11-13 12:16:07 +0200 | [diff] [blame] | 55 | MemoryRegion iomem; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 56 | uint32_t io_base; |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 57 | uint32_t size; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 58 | /* RTC management */ |
| 59 | time_t time_offset; |
| 60 | time_t stop_time; |
| 61 | /* Alarm & watchdog */ |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 62 | struct tm alarm; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 63 | struct QEMUTimer *alrm_timer; |
| 64 | struct QEMUTimer *wd_timer; |
| 65 | /* NVRAM storage */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 66 | uint8_t *buffer; |
Blue Swirl | 42c812b | 2011-08-07 20:02:02 +0000 | [diff] [blame] | 67 | /* Model parameters */ |
| 68 | uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */ |
| 69 | /* NVRAM storage */ |
| 70 | uint16_t addr; |
| 71 | uint8_t lock; |
bellard | c5df018 | 2004-04-12 20:54:52 +0000 | [diff] [blame] | 72 | }; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 73 | |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 74 | typedef struct M48t59ISAState { |
| 75 | ISADevice busdev; |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 76 | M48t59State state; |
Richard Henderson | 9936d6e | 2011-08-15 15:33:40 -0700 | [diff] [blame] | 77 | MemoryRegion io; |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 78 | } M48t59ISAState; |
| 79 | |
| 80 | typedef struct M48t59SysBusState { |
| 81 | SysBusDevice busdev; |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 82 | M48t59State state; |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 83 | } M48t59SysBusState; |
| 84 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 85 | /* Fake timer functions */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 86 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 87 | /* Alarm management */ |
| 88 | static void alarm_cb (void *opaque) |
| 89 | { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 90 | struct tm tm; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 91 | uint64_t next_time; |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 92 | M48t59State *NVRAM = opaque; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 93 | |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 94 | qemu_set_irq(NVRAM->IRQ, 1); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 95 | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 96 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
| 97 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
| 98 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 99 | /* Repeat once a month */ |
| 100 | qemu_get_timedate(&tm, NVRAM->time_offset); |
| 101 | tm.tm_mon++; |
| 102 | if (tm.tm_mon == 13) { |
| 103 | tm.tm_mon = 1; |
| 104 | tm.tm_year++; |
| 105 | } |
| 106 | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 107 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
| 108 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
| 109 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
| 110 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 111 | /* Repeat once a day */ |
| 112 | next_time = 24 * 60 * 60; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 113 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
| 114 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
| 115 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
| 116 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 117 | /* Repeat once an hour */ |
| 118 | next_time = 60 * 60; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 119 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
| 120 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && |
| 121 | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && |
| 122 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 123 | /* Repeat once a minute */ |
| 124 | next_time = 60; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 125 | } else { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 126 | /* Repeat once a second */ |
| 127 | next_time = 1; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 128 | } |
Paolo Bonzini | 1d84950 | 2012-01-20 13:05:00 +0100 | [diff] [blame] | 129 | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) + |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 130 | next_time * 1000); |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 131 | qemu_set_irq(NVRAM->IRQ, 0); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 132 | } |
| 133 | |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 134 | static void set_alarm(M48t59State *NVRAM) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 135 | { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 136 | int diff; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 137 | if (NVRAM->alrm_timer != NULL) { |
| 138 | qemu_del_timer(NVRAM->alrm_timer); |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 139 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
| 140 | if (diff > 0) |
| 141 | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 142 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 143 | } |
| 144 | |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 145 | /* RTC management helpers */ |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 146 | static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 147 | { |
| 148 | qemu_get_timedate(tm, NVRAM->time_offset); |
| 149 | } |
| 150 | |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 151 | static void set_time(M48t59State *NVRAM, struct tm *tm) |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 152 | { |
| 153 | NVRAM->time_offset = qemu_timedate_diff(tm); |
| 154 | set_alarm(NVRAM); |
| 155 | } |
| 156 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 157 | /* Watchdog management */ |
| 158 | static void watchdog_cb (void *opaque) |
| 159 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 160 | M48t59State *NVRAM = opaque; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 161 | |
| 162 | NVRAM->buffer[0x1FF0] |= 0x80; |
| 163 | if (NVRAM->buffer[0x1FF7] & 0x80) { |
| 164 | NVRAM->buffer[0x1FF7] = 0x00; |
| 165 | NVRAM->buffer[0x1FFC] &= ~0x40; |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 166 | /* May it be a hw CPU Reset instead ? */ |
bellard | d7d02e3 | 2004-06-20 12:58:36 +0000 | [diff] [blame] | 167 | qemu_system_reset_request(); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 168 | } else { |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 169 | qemu_set_irq(NVRAM->IRQ, 1); |
| 170 | qemu_set_irq(NVRAM->IRQ, 0); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 171 | } |
| 172 | } |
| 173 | |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 174 | static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 175 | { |
| 176 | uint64_t interval; /* in 1/16 seconds */ |
| 177 | |
j_mayer | 868d585 | 2007-09-30 01:29:07 +0000 | [diff] [blame] | 178 | NVRAM->buffer[0x1FF0] &= ~0x80; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 179 | if (NVRAM->wd_timer != NULL) { |
| 180 | qemu_del_timer(NVRAM->wd_timer); |
j_mayer | 868d585 | 2007-09-30 01:29:07 +0000 | [diff] [blame] | 181 | if (value != 0) { |
| 182 | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); |
| 183 | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
| 184 | ((interval * 1000) >> 4)); |
| 185 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 186 | } |
| 187 | } |
| 188 | |
| 189 | /* Direct access to NVRAM */ |
j_mayer | 897b4c6 | 2007-10-28 23:33:05 +0000 | [diff] [blame] | 190 | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 191 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 192 | M48t59State *NVRAM = opaque; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 193 | struct tm tm; |
| 194 | int tmp; |
| 195 | |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 196 | if (addr > 0x1FF8 && addr < 0x2000) |
| 197 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 198 | |
| 199 | /* check for NVRAM access */ |
| 200 | if ((NVRAM->type == 2 && addr < 0x7f8) || |
| 201 | (NVRAM->type == 8 && addr < 0x1ff8) || |
| 202 | (NVRAM->type == 59 && addr < 0x1ff0)) |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 203 | goto do_write; |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 204 | |
| 205 | /* TOD access */ |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 206 | switch (addr) { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 207 | case 0x1FF0: |
| 208 | /* flags register : read-only */ |
| 209 | break; |
| 210 | case 0x1FF1: |
| 211 | /* unused */ |
| 212 | break; |
| 213 | case 0x1FF2: |
| 214 | /* alarm seconds */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 215 | tmp = from_bcd(val & 0x7F); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 216 | if (tmp >= 0 && tmp <= 59) { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 217 | NVRAM->alarm.tm_sec = tmp; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 218 | NVRAM->buffer[0x1FF2] = val; |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 219 | set_alarm(NVRAM); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 220 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 221 | break; |
| 222 | case 0x1FF3: |
| 223 | /* alarm minutes */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 224 | tmp = from_bcd(val & 0x7F); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 225 | if (tmp >= 0 && tmp <= 59) { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 226 | NVRAM->alarm.tm_min = tmp; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 227 | NVRAM->buffer[0x1FF3] = val; |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 228 | set_alarm(NVRAM); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 229 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 230 | break; |
| 231 | case 0x1FF4: |
| 232 | /* alarm hours */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 233 | tmp = from_bcd(val & 0x3F); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 234 | if (tmp >= 0 && tmp <= 23) { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 235 | NVRAM->alarm.tm_hour = tmp; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 236 | NVRAM->buffer[0x1FF4] = val; |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 237 | set_alarm(NVRAM); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 238 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 239 | break; |
| 240 | case 0x1FF5: |
| 241 | /* alarm date */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 242 | tmp = from_bcd(val & 0x1F); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 243 | if (tmp != 0) { |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 244 | NVRAM->alarm.tm_mday = tmp; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 245 | NVRAM->buffer[0x1FF5] = val; |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 246 | set_alarm(NVRAM); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 247 | } |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 248 | break; |
| 249 | case 0x1FF6: |
| 250 | /* interrupts */ |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 251 | NVRAM->buffer[0x1FF6] = val; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 252 | break; |
| 253 | case 0x1FF7: |
| 254 | /* watchdog */ |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 255 | NVRAM->buffer[0x1FF7] = val; |
| 256 | set_up_watchdog(NVRAM, val); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 257 | break; |
| 258 | case 0x1FF8: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 259 | case 0x07F8: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 260 | /* control */ |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 261 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 262 | break; |
| 263 | case 0x1FF9: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 264 | case 0x07F9: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 265 | /* seconds (BCD) */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 266 | tmp = from_bcd(val & 0x7F); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 267 | if (tmp >= 0 && tmp <= 59) { |
| 268 | get_time(NVRAM, &tm); |
| 269 | tm.tm_sec = tmp; |
| 270 | set_time(NVRAM, &tm); |
| 271 | } |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 272 | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 273 | if (val & 0x80) { |
| 274 | NVRAM->stop_time = time(NULL); |
| 275 | } else { |
| 276 | NVRAM->time_offset += NVRAM->stop_time - time(NULL); |
| 277 | NVRAM->stop_time = 0; |
| 278 | } |
| 279 | } |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 280 | NVRAM->buffer[addr] = val & 0x80; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 281 | break; |
| 282 | case 0x1FFA: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 283 | case 0x07FA: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 284 | /* minutes (BCD) */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 285 | tmp = from_bcd(val & 0x7F); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 286 | if (tmp >= 0 && tmp <= 59) { |
| 287 | get_time(NVRAM, &tm); |
| 288 | tm.tm_min = tmp; |
| 289 | set_time(NVRAM, &tm); |
| 290 | } |
| 291 | break; |
| 292 | case 0x1FFB: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 293 | case 0x07FB: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 294 | /* hours (BCD) */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 295 | tmp = from_bcd(val & 0x3F); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 296 | if (tmp >= 0 && tmp <= 23) { |
| 297 | get_time(NVRAM, &tm); |
| 298 | tm.tm_hour = tmp; |
| 299 | set_time(NVRAM, &tm); |
| 300 | } |
| 301 | break; |
| 302 | case 0x1FFC: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 303 | case 0x07FC: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 304 | /* day of the week / century */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 305 | tmp = from_bcd(val & 0x07); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 306 | get_time(NVRAM, &tm); |
| 307 | tm.tm_wday = tmp; |
| 308 | set_time(NVRAM, &tm); |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 309 | NVRAM->buffer[addr] = val & 0x40; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 310 | break; |
| 311 | case 0x1FFD: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 312 | case 0x07FD: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 313 | /* date */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 314 | tmp = from_bcd(val & 0x1F); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 315 | if (tmp != 0) { |
| 316 | get_time(NVRAM, &tm); |
| 317 | tm.tm_mday = tmp; |
| 318 | set_time(NVRAM, &tm); |
| 319 | } |
| 320 | break; |
| 321 | case 0x1FFE: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 322 | case 0x07FE: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 323 | /* month */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 324 | tmp = from_bcd(val & 0x1F); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 325 | if (tmp >= 1 && tmp <= 12) { |
| 326 | get_time(NVRAM, &tm); |
| 327 | tm.tm_mon = tmp - 1; |
| 328 | set_time(NVRAM, &tm); |
| 329 | } |
| 330 | break; |
| 331 | case 0x1FFF: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 332 | case 0x07FF: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 333 | /* year */ |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 334 | tmp = from_bcd(val); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 335 | if (tmp >= 0 && tmp <= 99) { |
| 336 | get_time(NVRAM, &tm); |
bellard | 180b700 | 2006-06-14 12:41:34 +0000 | [diff] [blame] | 337 | if (NVRAM->type == 8) |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 338 | tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
bellard | 180b700 | 2006-06-14 12:41:34 +0000 | [diff] [blame] | 339 | else |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 340 | tm.tm_year = from_bcd(val); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 341 | set_time(NVRAM, &tm); |
| 342 | } |
| 343 | break; |
| 344 | default: |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 345 | /* Check lock registers state */ |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 346 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 347 | break; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 348 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 349 | break; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 350 | do_write: |
| 351 | if (addr < NVRAM->size) { |
| 352 | NVRAM->buffer[addr] = val & 0xFF; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 353 | } |
| 354 | break; |
| 355 | } |
| 356 | } |
| 357 | |
j_mayer | 897b4c6 | 2007-10-28 23:33:05 +0000 | [diff] [blame] | 358 | uint32_t m48t59_read (void *opaque, uint32_t addr) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 359 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 360 | M48t59State *NVRAM = opaque; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 361 | struct tm tm; |
| 362 | uint32_t retval = 0xFF; |
| 363 | |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 364 | /* check for NVRAM access */ |
| 365 | if ((NVRAM->type == 2 && addr < 0x078f) || |
| 366 | (NVRAM->type == 8 && addr < 0x1ff8) || |
| 367 | (NVRAM->type == 59 && addr < 0x1ff0)) |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 368 | goto do_read; |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 369 | |
| 370 | /* TOD access */ |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 371 | switch (addr) { |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 372 | case 0x1FF0: |
| 373 | /* flags register */ |
| 374 | goto do_read; |
| 375 | case 0x1FF1: |
| 376 | /* unused */ |
| 377 | retval = 0; |
| 378 | break; |
| 379 | case 0x1FF2: |
| 380 | /* alarm seconds */ |
| 381 | goto do_read; |
| 382 | case 0x1FF3: |
| 383 | /* alarm minutes */ |
| 384 | goto do_read; |
| 385 | case 0x1FF4: |
| 386 | /* alarm hours */ |
| 387 | goto do_read; |
| 388 | case 0x1FF5: |
| 389 | /* alarm date */ |
| 390 | goto do_read; |
| 391 | case 0x1FF6: |
| 392 | /* interrupts */ |
| 393 | goto do_read; |
| 394 | case 0x1FF7: |
| 395 | /* A read resets the watchdog */ |
| 396 | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]); |
| 397 | goto do_read; |
| 398 | case 0x1FF8: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 399 | case 0x07F8: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 400 | /* control */ |
| 401 | goto do_read; |
| 402 | case 0x1FF9: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 403 | case 0x07F9: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 404 | /* seconds (BCD) */ |
| 405 | get_time(NVRAM, &tm); |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 406 | retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 407 | break; |
| 408 | case 0x1FFA: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 409 | case 0x07FA: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 410 | /* minutes (BCD) */ |
| 411 | get_time(NVRAM, &tm); |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 412 | retval = to_bcd(tm.tm_min); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 413 | break; |
| 414 | case 0x1FFB: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 415 | case 0x07FB: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 416 | /* hours (BCD) */ |
| 417 | get_time(NVRAM, &tm); |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 418 | retval = to_bcd(tm.tm_hour); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 419 | break; |
| 420 | case 0x1FFC: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 421 | case 0x07FC: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 422 | /* day of the week / century */ |
| 423 | get_time(NVRAM, &tm); |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 424 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 425 | break; |
| 426 | case 0x1FFD: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 427 | case 0x07FD: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 428 | /* date */ |
| 429 | get_time(NVRAM, &tm); |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 430 | retval = to_bcd(tm.tm_mday); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 431 | break; |
| 432 | case 0x1FFE: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 433 | case 0x07FE: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 434 | /* month */ |
| 435 | get_time(NVRAM, &tm); |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 436 | retval = to_bcd(tm.tm_mon + 1); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 437 | break; |
| 438 | case 0x1FFF: |
blueswir1 | 4aed2c3 | 2007-12-29 09:05:30 +0000 | [diff] [blame] | 439 | case 0x07FF: |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 440 | /* year */ |
| 441 | get_time(NVRAM, &tm); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 442 | if (NVRAM->type == 8) |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 443 | retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
bellard | 180b700 | 2006-06-14 12:41:34 +0000 | [diff] [blame] | 444 | else |
Paul Brook | abd0c6b | 2009-11-20 00:03:47 +0000 | [diff] [blame] | 445 | retval = to_bcd(tm.tm_year); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 446 | break; |
| 447 | default: |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 448 | /* Check lock registers state */ |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 449 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 450 | break; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 451 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 452 | break; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 453 | do_read: |
| 454 | if (addr < NVRAM->size) { |
| 455 | retval = NVRAM->buffer[addr]; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 456 | } |
| 457 | break; |
| 458 | } |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 459 | if (addr > 0x1FF9 && addr < 0x2000) |
blueswir1 | 9ed1e66 | 2007-12-29 09:03:43 +0000 | [diff] [blame] | 460 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 461 | |
| 462 | return retval; |
| 463 | } |
| 464 | |
j_mayer | 897b4c6 | 2007-10-28 23:33:05 +0000 | [diff] [blame] | 465 | void m48t59_set_addr (void *opaque, uint32_t addr) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 466 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 467 | M48t59State *NVRAM = opaque; |
j_mayer | 897b4c6 | 2007-10-28 23:33:05 +0000 | [diff] [blame] | 468 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 469 | NVRAM->addr = addr; |
| 470 | } |
| 471 | |
j_mayer | 897b4c6 | 2007-10-28 23:33:05 +0000 | [diff] [blame] | 472 | void m48t59_toggle_lock (void *opaque, int lock) |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 473 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 474 | M48t59State *NVRAM = opaque; |
j_mayer | 897b4c6 | 2007-10-28 23:33:05 +0000 | [diff] [blame] | 475 | |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 476 | NVRAM->lock ^= 1 << lock; |
| 477 | } |
| 478 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 479 | /* IO access to NVRAM */ |
| 480 | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) |
| 481 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 482 | M48t59State *NVRAM = opaque; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 483 | |
blueswir1 | 9ed1e66 | 2007-12-29 09:03:43 +0000 | [diff] [blame] | 484 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 485 | switch (addr) { |
| 486 | case 0: |
| 487 | NVRAM->addr &= ~0x00FF; |
| 488 | NVRAM->addr |= val; |
| 489 | break; |
| 490 | case 1: |
| 491 | NVRAM->addr &= ~0xFF00; |
| 492 | NVRAM->addr |= val << 8; |
| 493 | break; |
| 494 | case 3: |
Blue Swirl | b1f8830 | 2011-10-15 08:05:18 +0000 | [diff] [blame] | 495 | m48t59_write(NVRAM, NVRAM->addr, val); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 496 | NVRAM->addr = 0x0000; |
| 497 | break; |
| 498 | default: |
| 499 | break; |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) |
| 504 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 505 | M48t59State *NVRAM = opaque; |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 506 | uint32_t retval; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 507 | |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 508 | switch (addr) { |
| 509 | case 3: |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 510 | retval = m48t59_read(NVRAM, NVRAM->addr); |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 511 | break; |
| 512 | default: |
| 513 | retval = -1; |
| 514 | break; |
| 515 | } |
blueswir1 | 9ed1e66 | 2007-12-29 09:03:43 +0000 | [diff] [blame] | 516 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 517 | |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 518 | return retval; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 519 | } |
| 520 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 521 | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 522 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 523 | M48t59State *NVRAM = opaque; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 524 | |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 525 | m48t59_write(NVRAM, addr, value & 0xff); |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 526 | } |
| 527 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 528 | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 529 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 530 | M48t59State *NVRAM = opaque; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 531 | |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 532 | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
| 533 | m48t59_write(NVRAM, addr + 1, value & 0xff); |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 534 | } |
| 535 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 536 | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 537 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 538 | M48t59State *NVRAM = opaque; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 539 | |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 540 | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
| 541 | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); |
| 542 | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); |
| 543 | m48t59_write(NVRAM, addr + 3, value & 0xff); |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 544 | } |
| 545 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 546 | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 547 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 548 | M48t59State *NVRAM = opaque; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 549 | uint32_t retval; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 550 | |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 551 | retval = m48t59_read(NVRAM, addr); |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 552 | return retval; |
| 553 | } |
| 554 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 555 | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 556 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 557 | M48t59State *NVRAM = opaque; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 558 | uint32_t retval; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 559 | |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 560 | retval = m48t59_read(NVRAM, addr) << 8; |
| 561 | retval |= m48t59_read(NVRAM, addr + 1); |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 562 | return retval; |
| 563 | } |
| 564 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 565 | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 566 | { |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 567 | M48t59State *NVRAM = opaque; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 568 | uint32_t retval; |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 569 | |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 570 | retval = m48t59_read(NVRAM, addr) << 24; |
| 571 | retval |= m48t59_read(NVRAM, addr + 1) << 16; |
| 572 | retval |= m48t59_read(NVRAM, addr + 2) << 8; |
| 573 | retval |= m48t59_read(NVRAM, addr + 3); |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 574 | return retval; |
| 575 | } |
| 576 | |
Avi Kivity | 5a31cd6 | 2011-11-13 12:16:07 +0200 | [diff] [blame] | 577 | static const MemoryRegionOps nvram_ops = { |
| 578 | .old_mmio = { |
| 579 | .read = { nvram_readb, nvram_readw, nvram_readl, }, |
| 580 | .write = { nvram_writeb, nvram_writew, nvram_writel, }, |
| 581 | }, |
| 582 | .endianness = DEVICE_NATIVE_ENDIAN, |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 583 | }; |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 584 | |
Juan Quintela | fd484ae | 2010-12-02 00:16:33 +0100 | [diff] [blame] | 585 | static const VMStateDescription vmstate_m48t59 = { |
| 586 | .name = "m48t59", |
| 587 | .version_id = 1, |
| 588 | .minimum_version_id = 1, |
| 589 | .minimum_version_id_old = 1, |
| 590 | .fields = (VMStateField[]) { |
| 591 | VMSTATE_UINT8(lock, M48t59State), |
| 592 | VMSTATE_UINT16(addr, M48t59State), |
| 593 | VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), |
| 594 | VMSTATE_END_OF_LIST() |
| 595 | } |
| 596 | }; |
blueswir1 | 3ccacc4 | 2007-04-14 13:01:31 +0000 | [diff] [blame] | 597 | |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 598 | static void m48t59_reset_common(M48t59State *NVRAM) |
blueswir1 | 3ccacc4 | 2007-04-14 13:01:31 +0000 | [diff] [blame] | 599 | { |
blueswir1 | 6e6b736 | 2008-12-28 18:27:10 +0000 | [diff] [blame] | 600 | NVRAM->addr = 0; |
| 601 | NVRAM->lock = 0; |
blueswir1 | 3ccacc4 | 2007-04-14 13:01:31 +0000 | [diff] [blame] | 602 | if (NVRAM->alrm_timer != NULL) |
| 603 | qemu_del_timer(NVRAM->alrm_timer); |
| 604 | |
| 605 | if (NVRAM->wd_timer != NULL) |
| 606 | qemu_del_timer(NVRAM->wd_timer); |
| 607 | } |
| 608 | |
Blue Swirl | 285e468 | 2009-10-24 19:22:56 +0000 | [diff] [blame] | 609 | static void m48t59_reset_isa(DeviceState *d) |
| 610 | { |
| 611 | M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev); |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 612 | M48t59State *NVRAM = &isa->state; |
Blue Swirl | 285e468 | 2009-10-24 19:22:56 +0000 | [diff] [blame] | 613 | |
| 614 | m48t59_reset_common(NVRAM); |
| 615 | } |
| 616 | |
| 617 | static void m48t59_reset_sysbus(DeviceState *d) |
| 618 | { |
| 619 | M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 620 | M48t59State *NVRAM = &sys->state; |
Blue Swirl | 285e468 | 2009-10-24 19:22:56 +0000 | [diff] [blame] | 621 | |
| 622 | m48t59_reset_common(NVRAM); |
| 623 | } |
| 624 | |
Richard Henderson | 9936d6e | 2011-08-15 15:33:40 -0700 | [diff] [blame] | 625 | static const MemoryRegionPortio m48t59_portio[] = { |
| 626 | {0, 4, 1, .read = NVRAM_readb, .write = NVRAM_writeb }, |
| 627 | PORTIO_END_OF_LIST(), |
| 628 | }; |
| 629 | |
| 630 | static const MemoryRegionOps m48t59_io_ops = { |
| 631 | .old_portio = m48t59_portio, |
| 632 | }; |
| 633 | |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 634 | /* Initialisation routine */ |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 635 | M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, |
| 636 | uint32_t io_base, uint16_t size, int type) |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 637 | { |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 638 | DeviceState *dev; |
| 639 | SysBusDevice *s; |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 640 | M48t59SysBusState *d; |
Hervé Poussineau | 51f9b84 | 2011-01-02 19:44:49 +0100 | [diff] [blame] | 641 | M48t59State *state; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 642 | |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 643 | dev = qdev_create(NULL, "m48t59"); |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 644 | qdev_prop_set_uint32(dev, "type", type); |
| 645 | qdev_prop_set_uint32(dev, "size", size); |
| 646 | qdev_prop_set_uint32(dev, "io_base", io_base); |
Markus Armbruster | e23a1b3 | 2009-10-07 01:15:58 +0200 | [diff] [blame] | 647 | qdev_init_nofail(dev); |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 648 | s = sysbus_from_qdev(dev); |
Hervé Poussineau | 51f9b84 | 2011-01-02 19:44:49 +0100 | [diff] [blame] | 649 | d = FROM_SYSBUS(M48t59SysBusState, s); |
| 650 | state = &d->state; |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 651 | sysbus_connect_irq(s, 0, IRQ); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 652 | if (io_base != 0) { |
Hervé Poussineau | 51f9b84 | 2011-01-02 19:44:49 +0100 | [diff] [blame] | 653 | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state); |
| 654 | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 655 | } |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 656 | if (mem_base != 0) { |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 657 | sysbus_mmio_map(s, 0, mem_base); |
bellard | e1bb04f | 2004-06-21 16:49:53 +0000 | [diff] [blame] | 658 | } |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 659 | |
Hervé Poussineau | 51f9b84 | 2011-01-02 19:44:49 +0100 | [diff] [blame] | 660 | return state; |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 661 | } |
| 662 | |
Hervé Poussineau | 48a18b3 | 2011-12-15 22:09:51 +0100 | [diff] [blame] | 663 | M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, |
| 664 | int type) |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 665 | { |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 666 | M48t59ISAState *d; |
| 667 | ISADevice *dev; |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 668 | M48t59State *s; |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 669 | |
Hervé Poussineau | 48a18b3 | 2011-12-15 22:09:51 +0100 | [diff] [blame] | 670 | dev = isa_create(bus, "m48t59_isa"); |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 671 | qdev_prop_set_uint32(&dev->qdev, "type", type); |
| 672 | qdev_prop_set_uint32(&dev->qdev, "size", size); |
| 673 | qdev_prop_set_uint32(&dev->qdev, "io_base", io_base); |
Markus Armbruster | e23a1b3 | 2009-10-07 01:15:58 +0200 | [diff] [blame] | 674 | qdev_init_nofail(&dev->qdev); |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 675 | d = DO_UPCAST(M48t59ISAState, busdev, dev); |
| 676 | s = &d->state; |
| 677 | |
Richard Henderson | 9936d6e | 2011-08-15 15:33:40 -0700 | [diff] [blame] | 678 | memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 679 | if (io_base != 0) { |
Richard Henderson | 9936d6e | 2011-08-15 15:33:40 -0700 | [diff] [blame] | 680 | isa_register_ioport(dev, &d->io, io_base); |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 681 | } |
| 682 | |
| 683 | return s; |
| 684 | } |
| 685 | |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 686 | static void m48t59_init_common(M48t59State *s) |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 687 | { |
Anthony Liguori | 7267c09 | 2011-08-20 22:09:37 -0500 | [diff] [blame] | 688 | s->buffer = g_malloc0(s->size); |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 689 | if (s->type == 59) { |
Paolo Bonzini | 1d84950 | 2012-01-20 13:05:00 +0100 | [diff] [blame] | 690 | s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s); |
Paolo Bonzini | 7447545 | 2011-03-11 16:47:48 +0100 | [diff] [blame] | 691 | s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); |
bellard | 819385c | 2005-10-30 16:58:32 +0000 | [diff] [blame] | 692 | } |
balrog | f650305 | 2008-02-17 11:42:19 +0000 | [diff] [blame] | 693 | qemu_get_timedate(&s->alarm, 0); |
bellard | 13ab5da | 2004-05-17 20:21:49 +0000 | [diff] [blame] | 694 | |
Juan Quintela | fd484ae | 2010-12-02 00:16:33 +0100 | [diff] [blame] | 695 | vmstate_register(NULL, -1, &vmstate_m48t59, s); |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 696 | } |
| 697 | |
| 698 | static int m48t59_init_isa1(ISADevice *dev) |
| 699 | { |
| 700 | M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 701 | M48t59State *s = &d->state; |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 702 | |
| 703 | isa_init_irq(dev, &s->IRQ, 8); |
| 704 | m48t59_init_common(s); |
| 705 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 706 | return 0; |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 707 | } |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 708 | |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 709 | static int m48t59_init1(SysBusDevice *dev) |
| 710 | { |
| 711 | M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); |
Blue Swirl | 43a3470 | 2010-02-07 08:05:03 +0000 | [diff] [blame] | 712 | M48t59State *s = &d->state; |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 713 | |
| 714 | sysbus_init_irq(dev, &s->IRQ); |
| 715 | |
Avi Kivity | 5a31cd6 | 2011-11-13 12:16:07 +0200 | [diff] [blame] | 716 | memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size); |
Avi Kivity | 750ecd4 | 2011-11-27 11:38:10 +0200 | [diff] [blame] | 717 | sysbus_init_mmio(dev, &s->iomem); |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 718 | m48t59_init_common(s); |
| 719 | |
| 720 | return 0; |
| 721 | } |
| 722 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 723 | static Property m48t59_isa_properties[] = { |
| 724 | DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), |
| 725 | DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1), |
| 726 | DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
| 727 | DEFINE_PROP_END_OF_LIST(), |
| 728 | }; |
| 729 | |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 730 | static void m48t59_init_class_isa1(ObjectClass *klass, void *data) |
| 731 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 732 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 733 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
| 734 | ic->init = m48t59_init_isa1; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 735 | dc->no_user = 1; |
| 736 | dc->reset = m48t59_reset_isa; |
| 737 | dc->props = m48t59_isa_properties; |
Anthony Liguori | 8f04ee0 | 2011-12-04 11:52:49 -0600 | [diff] [blame] | 738 | } |
| 739 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 740 | static TypeInfo m48t59_isa_info = { |
| 741 | .name = "m48t59_isa", |
| 742 | .parent = TYPE_ISA_DEVICE, |
| 743 | .instance_size = sizeof(M48t59ISAState), |
| 744 | .class_init = m48t59_init_class_isa1, |
Blue Swirl | f80237d | 2009-09-14 15:33:28 +0000 | [diff] [blame] | 745 | }; |
| 746 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 747 | static Property m48t59_properties[] = { |
| 748 | DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
| 749 | DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1), |
| 750 | DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
| 751 | DEFINE_PROP_END_OF_LIST(), |
| 752 | }; |
| 753 | |
| 754 | static void m48t59_class_init(ObjectClass *klass, void *data) |
| 755 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 756 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 757 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
| 758 | |
| 759 | k->init = m48t59_init1; |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 760 | dc->reset = m48t59_reset_sysbus; |
| 761 | dc->props = m48t59_properties; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 762 | } |
| 763 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 764 | static TypeInfo m48t59_info = { |
| 765 | .name = "m48t59", |
| 766 | .parent = TYPE_SYS_BUS_DEVICE, |
| 767 | .instance_size = sizeof(M48t59SysBusState), |
| 768 | .class_init = m48t59_class_init, |
Gerd Hoffmann | ee6847d | 2009-07-15 13:43:31 +0200 | [diff] [blame] | 769 | }; |
| 770 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 771 | static void m48t59_register_types(void) |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 772 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 773 | type_register_static(&m48t59_info); |
| 774 | type_register_static(&m48t59_isa_info); |
Blue Swirl | d27cf0a | 2009-07-12 20:07:07 +0000 | [diff] [blame] | 775 | } |
| 776 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 777 | type_init(m48t59_register_types) |