bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 1 | /* General "disassemble this chunk" code. Used for debugging. */ |
bellard | 5bbe929 | 2003-06-09 19:38:38 +0000 | [diff] [blame] | 2 | #include "config.h" |
Paolo Bonzini | 76cad71 | 2012-10-24 11:12:21 +0200 | [diff] [blame] | 3 | #include "disas/bfd.h" |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 4 | #include "elf.h" |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 5 | #include <errno.h> |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 6 | |
bellard | c6105c0 | 2003-10-27 21:13:58 +0000 | [diff] [blame] | 7 | #include "cpu.h" |
Paolo Bonzini | 76cad71 | 2012-10-24 11:12:21 +0200 | [diff] [blame] | 8 | #include "disas/disas.h" |
bellard | c6105c0 | 2003-10-27 21:13:58 +0000 | [diff] [blame] | 9 | |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 10 | typedef struct CPUDebug { |
| 11 | struct disassemble_info info; |
| 12 | CPUArchState *env; |
| 13 | } CPUDebug; |
| 14 | |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 15 | /* Filled in by elfload.c. Simplistic, but will do for now. */ |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 16 | struct syminfo *syminfos = NULL; |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 17 | |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 18 | /* Get LENGTH bytes from info's buffer, at target address memaddr. |
| 19 | Transfer them to myaddr. */ |
| 20 | int |
pbrook | 3a742b7 | 2008-10-22 15:55:18 +0000 | [diff] [blame] | 21 | buffer_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length, |
| 22 | struct disassemble_info *info) |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 23 | { |
bellard | c6105c0 | 2003-10-27 21:13:58 +0000 | [diff] [blame] | 24 | if (memaddr < info->buffer_vma |
| 25 | || memaddr + length > info->buffer_vma + info->buffer_length) |
| 26 | /* Out of bounds. Use EIO because GDB uses it. */ |
| 27 | return EIO; |
| 28 | memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length); |
| 29 | return 0; |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 30 | } |
| 31 | |
bellard | c6105c0 | 2003-10-27 21:13:58 +0000 | [diff] [blame] | 32 | /* Get LENGTH bytes from info's buffer, at target address memaddr. |
| 33 | Transfer them to myaddr. */ |
| 34 | static int |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 35 | target_read_memory (bfd_vma memaddr, |
| 36 | bfd_byte *myaddr, |
| 37 | int length, |
| 38 | struct disassemble_info *info) |
bellard | c6105c0 | 2003-10-27 21:13:58 +0000 | [diff] [blame] | 39 | { |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 40 | CPUDebug *s = container_of(info, CPUDebug, info); |
| 41 | |
Andreas Färber | f17ec44 | 2013-06-29 19:40:58 +0200 | [diff] [blame] | 42 | cpu_memory_rw_debug(ENV_GET_CPU(s->env), memaddr, myaddr, length, 0); |
bellard | c6105c0 | 2003-10-27 21:13:58 +0000 | [diff] [blame] | 43 | return 0; |
| 44 | } |
bellard | c6105c0 | 2003-10-27 21:13:58 +0000 | [diff] [blame] | 45 | |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 46 | /* Print an error message. We can assume that this is in response to |
| 47 | an error return from buffer_read_memory. */ |
| 48 | void |
pbrook | 3a742b7 | 2008-10-22 15:55:18 +0000 | [diff] [blame] | 49 | perror_memory (int status, bfd_vma memaddr, struct disassemble_info *info) |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 50 | { |
| 51 | if (status != EIO) |
| 52 | /* Can't happen. */ |
| 53 | (*info->fprintf_func) (info->stream, "Unknown error %d\n", status); |
| 54 | else |
| 55 | /* Actually, address between memaddr and memaddr + len was |
| 56 | out of bounds. */ |
| 57 | (*info->fprintf_func) (info->stream, |
bellard | 26a7646 | 2006-06-25 18:15:32 +0000 | [diff] [blame] | 58 | "Address 0x%" PRIx64 " is out of bounds.\n", memaddr); |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 59 | } |
| 60 | |
Jim Meyering | a31f053 | 2012-05-09 05:12:04 +0000 | [diff] [blame] | 61 | /* This could be in a separate file, to save minuscule amounts of space |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 62 | in statically linked executables. */ |
| 63 | |
| 64 | /* Just print the address is hex. This is included for completeness even |
| 65 | though both GDB and objdump provide their own (to print symbolic |
| 66 | addresses). */ |
| 67 | |
| 68 | void |
pbrook | 3a742b7 | 2008-10-22 15:55:18 +0000 | [diff] [blame] | 69 | generic_print_address (bfd_vma addr, struct disassemble_info *info) |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 70 | { |
bellard | 26a7646 | 2006-06-25 18:15:32 +0000 | [diff] [blame] | 71 | (*info->fprintf_func) (info->stream, "0x%" PRIx64, addr); |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 72 | } |
| 73 | |
Peter Maydell | 636bd28 | 2012-06-25 04:55:55 +0000 | [diff] [blame] | 74 | /* Print address in hex, truncated to the width of a target virtual address. */ |
| 75 | static void |
| 76 | generic_print_target_address(bfd_vma addr, struct disassemble_info *info) |
| 77 | { |
| 78 | uint64_t mask = ~0ULL >> (64 - TARGET_VIRT_ADDR_SPACE_BITS); |
| 79 | generic_print_address(addr & mask, info); |
| 80 | } |
| 81 | |
| 82 | /* Print address in hex, truncated to the width of a host virtual address. */ |
| 83 | static void |
| 84 | generic_print_host_address(bfd_vma addr, struct disassemble_info *info) |
| 85 | { |
| 86 | uint64_t mask = ~0ULL >> (64 - (sizeof(void *) * 8)); |
| 87 | generic_print_address(addr & mask, info); |
| 88 | } |
| 89 | |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 90 | /* Just return the given address. */ |
| 91 | |
| 92 | int |
pbrook | 3a742b7 | 2008-10-22 15:55:18 +0000 | [diff] [blame] | 93 | generic_symbol_at_address (bfd_vma addr, struct disassemble_info *info) |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 94 | { |
| 95 | return 1; |
| 96 | } |
| 97 | |
Aurelien Jarno | 903ec55 | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 98 | bfd_vma bfd_getl64 (const bfd_byte *addr) |
| 99 | { |
| 100 | unsigned long long v; |
| 101 | |
| 102 | v = (unsigned long long) addr[0]; |
| 103 | v |= (unsigned long long) addr[1] << 8; |
| 104 | v |= (unsigned long long) addr[2] << 16; |
| 105 | v |= (unsigned long long) addr[3] << 24; |
| 106 | v |= (unsigned long long) addr[4] << 32; |
| 107 | v |= (unsigned long long) addr[5] << 40; |
| 108 | v |= (unsigned long long) addr[6] << 48; |
| 109 | v |= (unsigned long long) addr[7] << 56; |
| 110 | return (bfd_vma) v; |
| 111 | } |
| 112 | |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 113 | bfd_vma bfd_getl32 (const bfd_byte *addr) |
| 114 | { |
| 115 | unsigned long v; |
| 116 | |
| 117 | v = (unsigned long) addr[0]; |
| 118 | v |= (unsigned long) addr[1] << 8; |
| 119 | v |= (unsigned long) addr[2] << 16; |
| 120 | v |= (unsigned long) addr[3] << 24; |
| 121 | return (bfd_vma) v; |
| 122 | } |
| 123 | |
| 124 | bfd_vma bfd_getb32 (const bfd_byte *addr) |
| 125 | { |
| 126 | unsigned long v; |
| 127 | |
| 128 | v = (unsigned long) addr[0] << 24; |
| 129 | v |= (unsigned long) addr[1] << 16; |
| 130 | v |= (unsigned long) addr[2] << 8; |
| 131 | v |= (unsigned long) addr[3]; |
| 132 | return (bfd_vma) v; |
| 133 | } |
| 134 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 135 | bfd_vma bfd_getl16 (const bfd_byte *addr) |
| 136 | { |
| 137 | unsigned long v; |
| 138 | |
| 139 | v = (unsigned long) addr[0]; |
| 140 | v |= (unsigned long) addr[1] << 8; |
| 141 | return (bfd_vma) v; |
| 142 | } |
| 143 | |
| 144 | bfd_vma bfd_getb16 (const bfd_byte *addr) |
| 145 | { |
| 146 | unsigned long v; |
| 147 | |
| 148 | v = (unsigned long) addr[0] << 24; |
| 149 | v |= (unsigned long) addr[1] << 16; |
| 150 | return (bfd_vma) v; |
| 151 | } |
| 152 | |
bellard | c2d551f | 2005-04-27 20:15:00 +0000 | [diff] [blame] | 153 | #ifdef TARGET_ARM |
| 154 | static int |
| 155 | print_insn_thumb1(bfd_vma pc, disassemble_info *info) |
| 156 | { |
| 157 | return print_insn_arm(pc | 1, info); |
| 158 | } |
| 159 | #endif |
| 160 | |
Richard Henderson | c46ffd5 | 2013-08-16 23:29:45 -0700 | [diff] [blame] | 161 | static int print_insn_objdump(bfd_vma pc, disassemble_info *info, |
| 162 | const char *prefix) |
| 163 | { |
| 164 | int i, n = info->buffer_length; |
| 165 | uint8_t *buf = g_malloc(n); |
| 166 | |
| 167 | info->read_memory_func(pc, buf, n, info); |
| 168 | |
| 169 | for (i = 0; i < n; ++i) { |
| 170 | if (i % 32 == 0) { |
| 171 | info->fprintf_func(info->stream, "\n%s: ", prefix); |
| 172 | } |
| 173 | info->fprintf_func(info->stream, "%02x", buf[i]); |
| 174 | } |
| 175 | |
| 176 | g_free(buf); |
| 177 | return n; |
| 178 | } |
| 179 | |
| 180 | static int print_insn_od_host(bfd_vma pc, disassemble_info *info) |
| 181 | { |
| 182 | return print_insn_objdump(pc, info, "OBJD-H"); |
| 183 | } |
| 184 | |
| 185 | static int print_insn_od_target(bfd_vma pc, disassemble_info *info) |
| 186 | { |
| 187 | return print_insn_objdump(pc, info, "OBJD-T"); |
| 188 | } |
| 189 | |
ths | e91c8a7 | 2007-06-03 13:35:16 +0000 | [diff] [blame] | 190 | /* Disassemble this for me please... (debugging). 'flags' has the following |
bellard | c2d551f | 2005-04-27 20:15:00 +0000 | [diff] [blame] | 191 | values: |
Frediano Ziglio | e99722f | 2011-08-25 09:14:38 +0200 | [diff] [blame] | 192 | i386 - 1 means 16 bit code, 2 means 64 bit code |
Claudio Fontana | 999b53e | 2014-02-05 17:27:28 +0000 | [diff] [blame] | 193 | arm - bit 0 = thumb, bit 1 = reverse endian, bit 2 = A64 |
Tom Musta | e13951f | 2014-04-09 14:53:23 -0500 | [diff] [blame] | 194 | ppc - bits 0:15 specify (optionally) the machine instruction set; |
| 195 | bit 16 indicates little endian. |
bellard | c2d551f | 2005-04-27 20:15:00 +0000 | [diff] [blame] | 196 | other targets - unused |
| 197 | */ |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 198 | void target_disas(FILE *out, CPUArchState *env, target_ulong code, |
| 199 | target_ulong size, int flags) |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 200 | { |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 201 | target_ulong pc; |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 202 | int count; |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 203 | CPUDebug s; |
Richard Henderson | c46ffd5 | 2013-08-16 23:29:45 -0700 | [diff] [blame] | 204 | int (*print_insn)(bfd_vma pc, disassemble_info *info) = NULL; |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 205 | |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 206 | INIT_DISASSEMBLE_INFO(s.info, out, fprintf); |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 207 | |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 208 | s.env = env; |
| 209 | s.info.read_memory_func = target_read_memory; |
| 210 | s.info.buffer_vma = code; |
| 211 | s.info.buffer_length = size; |
| 212 | s.info.print_address_func = generic_print_target_address; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 213 | |
| 214 | #ifdef TARGET_WORDS_BIGENDIAN |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 215 | s.info.endian = BFD_ENDIAN_BIG; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 216 | #else |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 217 | s.info.endian = BFD_ENDIAN_LITTLE; |
bellard | c6105c0 | 2003-10-27 21:13:58 +0000 | [diff] [blame] | 218 | #endif |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 219 | #if defined(TARGET_I386) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 220 | if (flags == 2) { |
| 221 | s.info.mach = bfd_mach_x86_64; |
| 222 | } else if (flags == 1) { |
| 223 | s.info.mach = bfd_mach_i386_i8086; |
| 224 | } else { |
| 225 | s.info.mach = bfd_mach_i386_i386; |
| 226 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 227 | print_insn = print_insn_i386; |
| 228 | #elif defined(TARGET_ARM) |
Claudio Fontana | 999b53e | 2014-02-05 17:27:28 +0000 | [diff] [blame] | 229 | if (flags & 4) { |
| 230 | /* We might not be compiled with the A64 disassembler |
| 231 | * because it needs a C++ compiler; in that case we will |
| 232 | * fall through to the default print_insn_od case. |
| 233 | */ |
| 234 | #if defined(CONFIG_ARM_A64_DIS) |
| 235 | print_insn = print_insn_arm_a64; |
| 236 | #endif |
| 237 | } else if (flags & 1) { |
Paul Brook | d8fd295 | 2012-03-30 18:02:50 +0100 | [diff] [blame] | 238 | print_insn = print_insn_thumb1; |
| 239 | } else { |
| 240 | print_insn = print_insn_arm; |
| 241 | } |
| 242 | if (flags & 2) { |
| 243 | #ifdef TARGET_WORDS_BIGENDIAN |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 244 | s.info.endian = BFD_ENDIAN_LITTLE; |
Paul Brook | d8fd295 | 2012-03-30 18:02:50 +0100 | [diff] [blame] | 245 | #else |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 246 | s.info.endian = BFD_ENDIAN_BIG; |
Paul Brook | d8fd295 | 2012-03-30 18:02:50 +0100 | [diff] [blame] | 247 | #endif |
| 248 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 249 | #elif defined(TARGET_SPARC) |
| 250 | print_insn = print_insn_sparc; |
bellard | 3475187 | 2005-07-02 14:31:34 +0000 | [diff] [blame] | 251 | #ifdef TARGET_SPARC64 |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 252 | s.info.mach = bfd_mach_sparc_v9b; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 253 | #endif |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 254 | #elif defined(TARGET_PPC) |
Tom Musta | e13951f | 2014-04-09 14:53:23 -0500 | [diff] [blame] | 255 | if ((flags >> 16) & 1) { |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 256 | s.info.endian = BFD_ENDIAN_LITTLE; |
| 257 | } |
j_mayer | 237c0af | 2007-09-29 12:01:46 +0000 | [diff] [blame] | 258 | if (flags & 0xFFFF) { |
Tom Musta | e13951f | 2014-04-09 14:53:23 -0500 | [diff] [blame] | 259 | /* If we have a precise definition of the instruction set, use it. */ |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 260 | s.info.mach = flags & 0xFFFF; |
j_mayer | 237c0af | 2007-09-29 12:01:46 +0000 | [diff] [blame] | 261 | } else { |
bellard | a245862 | 2005-07-23 22:39:53 +0000 | [diff] [blame] | 262 | #ifdef TARGET_PPC64 |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 263 | s.info.mach = bfd_mach_ppc64; |
bellard | a245862 | 2005-07-23 22:39:53 +0000 | [diff] [blame] | 264 | #else |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 265 | s.info.mach = bfd_mach_ppc; |
bellard | a245862 | 2005-07-23 22:39:53 +0000 | [diff] [blame] | 266 | #endif |
j_mayer | 237c0af | 2007-09-29 12:01:46 +0000 | [diff] [blame] | 267 | } |
Aurelien Jarno | 88770fe | 2013-04-20 08:56:14 +0000 | [diff] [blame] | 268 | s.info.disassembler_options = (char *)"any"; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 269 | print_insn = print_insn_ppc; |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 270 | #elif defined(TARGET_M68K) |
| 271 | print_insn = print_insn_m68k; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 272 | #elif defined(TARGET_MIPS) |
bellard | 76b3030 | 2005-12-17 01:10:04 +0000 | [diff] [blame] | 273 | #ifdef TARGET_WORDS_BIGENDIAN |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 274 | print_insn = print_insn_big_mips; |
bellard | 76b3030 | 2005-12-17 01:10:04 +0000 | [diff] [blame] | 275 | #else |
| 276 | print_insn = print_insn_little_mips; |
| 277 | #endif |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 278 | #elif defined(TARGET_SH4) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 279 | s.info.mach = bfd_mach_sh4; |
bellard | fdf9b3e | 2006-04-27 21:07:38 +0000 | [diff] [blame] | 280 | print_insn = print_insn_sh; |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 281 | #elif defined(TARGET_ALPHA) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 282 | s.info.mach = bfd_mach_alpha_ev6; |
j_mayer | eddf68a | 2007-04-05 07:22:49 +0000 | [diff] [blame] | 283 | print_insn = print_insn_alpha; |
ths | a25fd13 | 2007-10-08 12:46:58 +0000 | [diff] [blame] | 284 | #elif defined(TARGET_CRIS) |
Edgar E. Iglesias | b09cd07 | 2011-01-10 22:31:09 +0100 | [diff] [blame] | 285 | if (flags != 32) { |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 286 | s.info.mach = bfd_mach_cris_v0_v10; |
Edgar E. Iglesias | b09cd07 | 2011-01-10 22:31:09 +0100 | [diff] [blame] | 287 | print_insn = print_insn_crisv10; |
| 288 | } else { |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 289 | s.info.mach = bfd_mach_cris_v32; |
Edgar E. Iglesias | b09cd07 | 2011-01-10 22:31:09 +0100 | [diff] [blame] | 290 | print_insn = print_insn_crisv32; |
| 291 | } |
Ulrich Hecht | db50060 | 2011-03-29 15:29:32 +0200 | [diff] [blame] | 292 | #elif defined(TARGET_S390X) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 293 | s.info.mach = bfd_mach_s390_64; |
Ulrich Hecht | db50060 | 2011-03-29 15:29:32 +0200 | [diff] [blame] | 294 | print_insn = print_insn_s390; |
Edgar E. Iglesias | e90e390 | 2009-05-20 20:07:38 +0200 | [diff] [blame] | 295 | #elif defined(TARGET_MICROBLAZE) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 296 | s.info.mach = bfd_arch_microblaze; |
Edgar E. Iglesias | e90e390 | 2009-05-20 20:07:38 +0200 | [diff] [blame] | 297 | print_insn = print_insn_microblaze; |
Anthony Green | bd86a88 | 2013-03-18 15:49:23 -0400 | [diff] [blame] | 298 | #elif defined(TARGET_MOXIE) |
| 299 | s.info.mach = bfd_arch_moxie; |
| 300 | print_insn = print_insn_moxie; |
Michael Walle | 79368f4 | 2012-03-31 19:54:20 +0200 | [diff] [blame] | 301 | #elif defined(TARGET_LM32) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 302 | s.info.mach = bfd_mach_lm32; |
Michael Walle | 79368f4 | 2012-03-31 19:54:20 +0200 | [diff] [blame] | 303 | print_insn = print_insn_lm32; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 304 | #endif |
Richard Henderson | c46ffd5 | 2013-08-16 23:29:45 -0700 | [diff] [blame] | 305 | if (print_insn == NULL) { |
| 306 | print_insn = print_insn_od_target; |
| 307 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 308 | |
blueswir1 | 7e000c2 | 2009-02-13 21:44:41 +0000 | [diff] [blame] | 309 | for (pc = code; size > 0; pc += count, size -= count) { |
bellard | fa15e03 | 2005-01-31 23:32:31 +0000 | [diff] [blame] | 310 | fprintf(out, "0x" TARGET_FMT_lx ": ", pc); |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 311 | count = print_insn(pc, &s.info); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 312 | #if 0 |
| 313 | { |
| 314 | int i; |
| 315 | uint8_t b; |
| 316 | fprintf(out, " {"); |
| 317 | for(i = 0; i < count; i++) { |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 318 | target_read_memory(pc + i, &b, 1, &s.info); |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 319 | fprintf(out, " %02x", b); |
| 320 | } |
| 321 | fprintf(out, " }"); |
| 322 | } |
| 323 | #endif |
| 324 | fprintf(out, "\n"); |
| 325 | if (count < 0) |
| 326 | break; |
malc | 754d00a | 2009-04-21 22:26:22 +0000 | [diff] [blame] | 327 | if (size < count) { |
| 328 | fprintf(out, |
| 329 | "Disassembler disagrees with translator over instruction " |
| 330 | "decoding\n" |
| 331 | "Please report this to qemu-devel@nongnu.org\n"); |
| 332 | break; |
| 333 | } |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 334 | } |
| 335 | } |
| 336 | |
| 337 | /* Disassemble this for me please... (debugging). */ |
| 338 | void disas(FILE *out, void *code, unsigned long size) |
| 339 | { |
Stefan Weil | b0b0f1c | 2012-04-12 15:44:35 +0200 | [diff] [blame] | 340 | uintptr_t pc; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 341 | int count; |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 342 | CPUDebug s; |
Richard Henderson | c46ffd5 | 2013-08-16 23:29:45 -0700 | [diff] [blame] | 343 | int (*print_insn)(bfd_vma pc, disassemble_info *info) = NULL; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 344 | |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 345 | INIT_DISASSEMBLE_INFO(s.info, out, fprintf); |
| 346 | s.info.print_address_func = generic_print_host_address; |
bellard | c6105c0 | 2003-10-27 21:13:58 +0000 | [diff] [blame] | 347 | |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 348 | s.info.buffer = code; |
| 349 | s.info.buffer_vma = (uintptr_t)code; |
| 350 | s.info.buffer_length = size; |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 351 | |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 352 | #ifdef HOST_WORDS_BIGENDIAN |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 353 | s.info.endian = BFD_ENDIAN_BIG; |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 354 | #else |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 355 | s.info.endian = BFD_ENDIAN_LITTLE; |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 356 | #endif |
Stefan Weil | 5826e51 | 2011-10-05 20:03:53 +0200 | [diff] [blame] | 357 | #if defined(CONFIG_TCG_INTERPRETER) |
| 358 | print_insn = print_insn_tci; |
| 359 | #elif defined(__i386__) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 360 | s.info.mach = bfd_mach_i386_i386; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 361 | print_insn = print_insn_i386; |
bellard | bc51c5c | 2004-03-17 23:46:04 +0000 | [diff] [blame] | 362 | #elif defined(__x86_64__) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 363 | s.info.mach = bfd_mach_x86_64; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 364 | print_insn = print_insn_i386; |
malc | e58ffeb | 2009-01-14 18:39:49 +0000 | [diff] [blame] | 365 | #elif defined(_ARCH_PPC) |
Richard Henderson | 66d4f6a | 2013-01-31 11:16:21 -0800 | [diff] [blame] | 366 | s.info.disassembler_options = (char *)"any"; |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 367 | print_insn = print_insn_ppc; |
Claudio Fontana | 999b53e | 2014-02-05 17:27:28 +0000 | [diff] [blame] | 368 | #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS) |
| 369 | print_insn = print_insn_arm_a64; |
bellard | a993ba8 | 2003-05-11 12:25:45 +0000 | [diff] [blame] | 370 | #elif defined(__alpha__) |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 371 | print_insn = print_insn_alpha; |
bellard | aa0aa4f | 2003-06-09 15:23:31 +0000 | [diff] [blame] | 372 | #elif defined(__sparc__) |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 373 | print_insn = print_insn_sparc; |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 374 | s.info.mach = bfd_mach_sparc_v9b; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 375 | #elif defined(__arm__) |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 376 | print_insn = print_insn_arm; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 377 | #elif defined(__MIPSEB__) |
| 378 | print_insn = print_insn_big_mips; |
| 379 | #elif defined(__MIPSEL__) |
| 380 | print_insn = print_insn_little_mips; |
bellard | 48024e4 | 2005-11-06 16:52:11 +0000 | [diff] [blame] | 381 | #elif defined(__m68k__) |
| 382 | print_insn = print_insn_m68k; |
ths | 8f860bb | 2007-07-31 23:44:21 +0000 | [diff] [blame] | 383 | #elif defined(__s390__) |
| 384 | print_insn = print_insn_s390; |
aurel32 | f54b3f9 | 2008-04-12 20:14:54 +0000 | [diff] [blame] | 385 | #elif defined(__hppa__) |
| 386 | print_insn = print_insn_hppa; |
Aurelien Jarno | 903ec55 | 2010-03-29 02:12:51 +0200 | [diff] [blame] | 387 | #elif defined(__ia64__) |
| 388 | print_insn = print_insn_ia64; |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 389 | #endif |
Richard Henderson | c46ffd5 | 2013-08-16 23:29:45 -0700 | [diff] [blame] | 390 | if (print_insn == NULL) { |
| 391 | print_insn = print_insn_od_host; |
| 392 | } |
Stefan Weil | b0b0f1c | 2012-04-12 15:44:35 +0200 | [diff] [blame] | 393 | for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) { |
| 394 | fprintf(out, "0x%08" PRIxPTR ": ", pc); |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 395 | count = print_insn(pc, &s.info); |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 396 | fprintf(out, "\n"); |
| 397 | if (count < 0) |
| 398 | break; |
| 399 | } |
| 400 | } |
| 401 | |
| 402 | /* Look up symbol for debugging purpose. Returns "" if unknown. */ |
bellard | c27004e | 2005-01-03 23:35:10 +0000 | [diff] [blame] | 403 | const char *lookup_symbol(target_ulong orig_addr) |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 404 | { |
pbrook | 49918a7 | 2008-10-22 15:11:31 +0000 | [diff] [blame] | 405 | const char *symbol = ""; |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 406 | struct syminfo *s; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 407 | |
bellard | e80cfcf | 2004-12-19 23:18:01 +0000 | [diff] [blame] | 408 | for (s = syminfos; s; s = s->next) { |
pbrook | 49918a7 | 2008-10-22 15:11:31 +0000 | [diff] [blame] | 409 | symbol = s->lookup_symbol(s, orig_addr); |
| 410 | if (symbol[0] != '\0') { |
| 411 | break; |
| 412 | } |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 413 | } |
pbrook | 49918a7 | 2008-10-22 15:11:31 +0000 | [diff] [blame] | 414 | |
| 415 | return symbol; |
bellard | b9adb4a | 2003-04-29 20:41:16 +0000 | [diff] [blame] | 416 | } |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 417 | |
| 418 | #if !defined(CONFIG_USER_ONLY) |
| 419 | |
Paolo Bonzini | 83c9089 | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 420 | #include "monitor/monitor.h" |
bellard | 3d2cfdf | 2004-08-01 21:49:07 +0000 | [diff] [blame] | 421 | |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 422 | static int monitor_disas_is_physical; |
| 423 | |
| 424 | static int |
blueswir1 | a5f1b96 | 2008-08-17 20:21:51 +0000 | [diff] [blame] | 425 | monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length, |
| 426 | struct disassemble_info *info) |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 427 | { |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 428 | CPUDebug *s = container_of(info, CPUDebug, info); |
| 429 | |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 430 | if (monitor_disas_is_physical) { |
Stefan Weil | 54f7b4a | 2011-04-10 18:23:39 +0200 | [diff] [blame] | 431 | cpu_physical_memory_read(memaddr, myaddr, length); |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 432 | } else { |
Andreas Färber | f17ec44 | 2013-06-29 19:40:58 +0200 | [diff] [blame] | 433 | cpu_memory_rw_debug(ENV_GET_CPU(s->env), memaddr, myaddr, length, 0); |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 434 | } |
| 435 | return 0; |
| 436 | } |
| 437 | |
Stefan Weil | 8b7968f | 2010-09-23 21:28:05 +0200 | [diff] [blame] | 438 | static int GCC_FMT_ATTR(2, 3) |
| 439 | monitor_fprintf(FILE *stream, const char *fmt, ...) |
bellard | 3d2cfdf | 2004-08-01 21:49:07 +0000 | [diff] [blame] | 440 | { |
| 441 | va_list ap; |
| 442 | va_start(ap, fmt); |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 443 | monitor_vprintf((Monitor *)stream, fmt, ap); |
bellard | 3d2cfdf | 2004-08-01 21:49:07 +0000 | [diff] [blame] | 444 | va_end(ap); |
| 445 | return 0; |
| 446 | } |
| 447 | |
Tom Musta | 1c38f84 | 2014-04-09 14:53:24 -0500 | [diff] [blame] | 448 | /* Disassembler for the monitor. |
| 449 | See target_disas for a description of flags. */ |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 450 | void monitor_disas(Monitor *mon, CPUArchState *env, |
bellard | 6a00d60 | 2005-11-21 23:25:50 +0000 | [diff] [blame] | 451 | target_ulong pc, int nb_insn, int is_physical, int flags) |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 452 | { |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 453 | int count, i; |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 454 | CPUDebug s; |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 455 | int (*print_insn)(bfd_vma pc, disassemble_info *info); |
| 456 | |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 457 | INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf); |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 458 | |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 459 | s.env = env; |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 460 | monitor_disas_is_physical = is_physical; |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 461 | s.info.read_memory_func = monitor_read_memory; |
| 462 | s.info.print_address_func = generic_print_target_address; |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 463 | |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 464 | s.info.buffer_vma = pc; |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 465 | |
| 466 | #ifdef TARGET_WORDS_BIGENDIAN |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 467 | s.info.endian = BFD_ENDIAN_BIG; |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 468 | #else |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 469 | s.info.endian = BFD_ENDIAN_LITTLE; |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 470 | #endif |
| 471 | #if defined(TARGET_I386) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 472 | if (flags == 2) { |
| 473 | s.info.mach = bfd_mach_x86_64; |
| 474 | } else if (flags == 1) { |
| 475 | s.info.mach = bfd_mach_i386_i8086; |
| 476 | } else { |
| 477 | s.info.mach = bfd_mach_i386_i386; |
| 478 | } |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 479 | print_insn = print_insn_i386; |
| 480 | #elif defined(TARGET_ARM) |
| 481 | print_insn = print_insn_arm; |
ths | cbd669d | 2007-12-25 00:26:36 +0000 | [diff] [blame] | 482 | #elif defined(TARGET_ALPHA) |
| 483 | print_insn = print_insn_alpha; |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 484 | #elif defined(TARGET_SPARC) |
| 485 | print_insn = print_insn_sparc; |
blueswir1 | 682c4f1 | 2007-04-09 15:14:57 +0000 | [diff] [blame] | 486 | #ifdef TARGET_SPARC64 |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 487 | s.info.mach = bfd_mach_sparc_v9b; |
blueswir1 | 682c4f1 | 2007-04-09 15:14:57 +0000 | [diff] [blame] | 488 | #endif |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 489 | #elif defined(TARGET_PPC) |
Tom Musta | 1c38f84 | 2014-04-09 14:53:24 -0500 | [diff] [blame] | 490 | if (flags & 0xFFFF) { |
| 491 | /* If we have a precise definition of the instruction set, use it. */ |
| 492 | s.info.mach = flags & 0xFFFF; |
| 493 | } else { |
bellard | a245862 | 2005-07-23 22:39:53 +0000 | [diff] [blame] | 494 | #ifdef TARGET_PPC64 |
Tom Musta | 1c38f84 | 2014-04-09 14:53:24 -0500 | [diff] [blame] | 495 | s.info.mach = bfd_mach_ppc64; |
bellard | a245862 | 2005-07-23 22:39:53 +0000 | [diff] [blame] | 496 | #else |
Tom Musta | 1c38f84 | 2014-04-09 14:53:24 -0500 | [diff] [blame] | 497 | s.info.mach = bfd_mach_ppc; |
bellard | a245862 | 2005-07-23 22:39:53 +0000 | [diff] [blame] | 498 | #endif |
Tom Musta | 1c38f84 | 2014-04-09 14:53:24 -0500 | [diff] [blame] | 499 | } |
| 500 | if ((flags >> 16) & 1) { |
| 501 | s.info.endian = BFD_ENDIAN_LITTLE; |
| 502 | } |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 503 | print_insn = print_insn_ppc; |
pbrook | e6e5906 | 2006-10-22 00:18:54 +0000 | [diff] [blame] | 504 | #elif defined(TARGET_M68K) |
| 505 | print_insn = print_insn_m68k; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 506 | #elif defined(TARGET_MIPS) |
bellard | 76b3030 | 2005-12-17 01:10:04 +0000 | [diff] [blame] | 507 | #ifdef TARGET_WORDS_BIGENDIAN |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 508 | print_insn = print_insn_big_mips; |
bellard | 76b3030 | 2005-12-17 01:10:04 +0000 | [diff] [blame] | 509 | #else |
| 510 | print_insn = print_insn_little_mips; |
| 511 | #endif |
Magnus Damm | b4e1f07 | 2009-11-13 18:54:22 +0900 | [diff] [blame] | 512 | #elif defined(TARGET_SH4) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 513 | s.info.mach = bfd_mach_sh4; |
Magnus Damm | b4e1f07 | 2009-11-13 18:54:22 +0900 | [diff] [blame] | 514 | print_insn = print_insn_sh; |
Ulrich Hecht | db50060 | 2011-03-29 15:29:32 +0200 | [diff] [blame] | 515 | #elif defined(TARGET_S390X) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 516 | s.info.mach = bfd_mach_s390_64; |
Ulrich Hecht | db50060 | 2011-03-29 15:29:32 +0200 | [diff] [blame] | 517 | print_insn = print_insn_s390; |
Anthony Green | bd86a88 | 2013-03-18 15:49:23 -0400 | [diff] [blame] | 518 | #elif defined(TARGET_MOXIE) |
| 519 | s.info.mach = bfd_arch_moxie; |
| 520 | print_insn = print_insn_moxie; |
Michael Walle | 79368f4 | 2012-03-31 19:54:20 +0200 | [diff] [blame] | 521 | #elif defined(TARGET_LM32) |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 522 | s.info.mach = bfd_mach_lm32; |
Michael Walle | 79368f4 | 2012-03-31 19:54:20 +0200 | [diff] [blame] | 523 | print_insn = print_insn_lm32; |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 524 | #else |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 525 | monitor_printf(mon, "0x" TARGET_FMT_lx |
| 526 | ": Asm output not supported on this arch\n", pc); |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 527 | return; |
| 528 | #endif |
| 529 | |
| 530 | for(i = 0; i < nb_insn; i++) { |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 531 | monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc); |
Blue Swirl | f4359b9 | 2012-09-08 12:40:00 +0000 | [diff] [blame] | 532 | count = print_insn(pc, &s.info); |
aliguori | 376253e | 2009-03-05 23:01:23 +0000 | [diff] [blame] | 533 | monitor_printf(mon, "\n"); |
bellard | 9307c4c | 2004-04-04 12:57:25 +0000 | [diff] [blame] | 534 | if (count < 0) |
| 535 | break; |
| 536 | pc += count; |
| 537 | } |
| 538 | } |
| 539 | #endif |