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pbrooke6e59062006-10-22 00:18:54 +00001/*
2 * m68k virtual CPU header
ths5fafdf22007-09-16 21:08:06 +00003 *
pbrook06338792007-05-23 19:58:11 +00004 * Copyright (c) 2005-2007 CodeSourcery
pbrooke6e59062006-10-22 00:18:54 +00005 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
pbrooke6e59062006-10-22 00:18:54 +000019 */
20#ifndef CPU_M68K_H
21#define CPU_M68K_H
22
23#define TARGET_LONG_BITS 32
24
Andreas Färber9349b4f2012-03-14 01:38:32 +010025#define CPUArchState struct CPUM68KState
pbrookc2764712009-03-07 15:24:59 +000026
Stefan Weil3aef4812012-02-01 20:55:18 +010027#include "config.h"
Stefan Weil9a78eea2010-10-22 23:03:33 +020028#include "qemu-common.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010029#include "exec/cpu-defs.h"
pbrooke6e59062006-10-22 00:18:54 +000030
Paolo Bonzini6b4c3052012-10-24 13:12:00 +020031#include "fpu/softfloat.h"
pbrooke6e59062006-10-22 00:18:54 +000032
33#define MAX_QREGS 32
34
pbrooke6e59062006-10-22 00:18:54 +000035#define EXCP_ACCESS 2 /* Access (MMU) error. */
36#define EXCP_ADDRESS 3 /* Address error. */
37#define EXCP_ILLEGAL 4 /* Illegal instruction. */
38#define EXCP_DIV0 5 /* Divide by zero */
39#define EXCP_PRIVILEGE 8 /* Privilege violation. */
40#define EXCP_TRACE 9
41#define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
42#define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
43#define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
44#define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
45#define EXCP_FORMAT 14 /* RTE format error. */
46#define EXCP_UNINITIALIZED 15
47#define EXCP_TRAP0 32 /* User trap #0. */
48#define EXCP_TRAP15 47 /* User trap #15. */
49#define EXCP_UNSUPPORTED 61
50#define EXCP_ICE 13
51
pbrook06338792007-05-23 19:58:11 +000052#define EXCP_RTE 0x100
pbrooka87295e2007-05-26 15:09:38 +000053#define EXCP_HALT_INSN 0x101
pbrook06338792007-05-23 19:58:11 +000054
j_mayer6ebbf392007-10-14 07:07:08 +000055#define NB_MMU_MODES 2
56
pbrooke6e59062006-10-22 00:18:54 +000057typedef struct CPUM68KState {
58 uint32_t dregs[8];
59 uint32_t aregs[8];
60 uint32_t pc;
61 uint32_t sr;
62
pbrook20dcee92007-06-03 11:13:39 +000063 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */
64 int current_sp;
65 uint32_t sp[2];
66
pbrooke6e59062006-10-22 00:18:54 +000067 /* Condition flags. */
68 uint32_t cc_op;
69 uint32_t cc_dest;
70 uint32_t cc_src;
71 uint32_t cc_x;
72
73 float64 fregs[8];
74 float64 fp_result;
75 uint32_t fpcr;
76 uint32_t fpsr;
77 float_status fp_status;
78
pbrookacf930a2007-05-29 14:57:59 +000079 uint64_t mactmp;
80 /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
81 two 8-bit parts. We store a single 64-bit value and
82 rearrange/extend this when changing modes. */
83 uint64_t macc[4];
84 uint32_t macsr;
85 uint32_t mac_mask;
86
pbrooke6e59062006-10-22 00:18:54 +000087 /* Temporary storage for DIV helpers. */
88 uint32_t div1;
89 uint32_t div2;
ths3b46e622007-09-17 08:09:54 +000090
pbrooke6e59062006-10-22 00:18:54 +000091 /* MMU status. */
92 struct {
93 uint32_t ar;
94 } mmu;
pbrook06338792007-05-23 19:58:11 +000095
96 /* Control registers. */
97 uint32_t vbr;
98 uint32_t mbar;
99 uint32_t rambar0;
pbrook20dcee92007-06-03 11:13:39 +0000100 uint32_t cacr;
pbrook06338792007-05-23 19:58:11 +0000101
pbrook06338792007-05-23 19:58:11 +0000102 int pending_vector;
103 int pending_level;
pbrooke6e59062006-10-22 00:18:54 +0000104
105 uint32_t qregs[MAX_QREGS];
106
107 CPU_COMMON
bellardaaed9092007-11-10 15:15:54 +0000108
Andreas Färberf0c3c502013-08-26 21:22:53 +0200109 /* Fields from here on are preserved across CPU reset. */
bellardaaed9092007-11-10 15:15:54 +0000110 uint32_t features;
pbrooke6e59062006-10-22 00:18:54 +0000111} CPUM68KState;
112
Andreas Färberb9e7a232012-04-15 00:35:50 +0200113#include "cpu-qom.h"
114
pbrooke1f38082008-05-24 22:29:16 +0000115void m68k_tcg_init(void);
Andreas Färber6d1bbc62013-01-05 15:15:30 +0100116void m68k_cpu_init_gdb(M68kCPU *cpu);
Andreas Färberc7937d92013-01-18 14:03:58 +0100117M68kCPU *cpu_m68k_init(const char *cpu_model);
Peter Crosthwaiteea3e9842015-06-18 10:24:55 -0700118int cpu_m68k_exec(CPUState *cpu);
pbrooke6e59062006-10-22 00:18:54 +0000119/* you can call this signal handler from your SIGBUS and SIGSEGV
120 signal handlers to inform the virtual CPU of exceptions. non zero
121 is returned if the signal was handled by the virtual CPU. */
ths5fafdf22007-09-16 21:08:06 +0000122int cpu_m68k_signal_handler(int host_signum, void *pinfo,
pbrooke6e59062006-10-22 00:18:54 +0000123 void *puc);
124void cpu_m68k_flush_flags(CPUM68KState *, int);
125
126enum {
127 CC_OP_DYNAMIC, /* Use env->cc_op */
128 CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
129 CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
130 CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */
131 CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */
132 CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */
133 CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
134 CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
135 CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
pbrooke1f38082008-05-24 22:29:16 +0000136 CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
pbrooke6e59062006-10-22 00:18:54 +0000137};
138
139#define CCF_C 0x01
140#define CCF_V 0x02
141#define CCF_Z 0x04
142#define CCF_N 0x08
pbrook06338792007-05-23 19:58:11 +0000143#define CCF_X 0x10
144
145#define SR_I_SHIFT 8
146#define SR_I 0x0700
147#define SR_M 0x1000
148#define SR_S 0x2000
149#define SR_T 0x8000
pbrooke6e59062006-10-22 00:18:54 +0000150
pbrook20dcee92007-06-03 11:13:39 +0000151#define M68K_SSP 0
152#define M68K_USP 1
153
154/* CACR fields are implementation defined, but some bits are common. */
155#define M68K_CACR_EUSP 0x10
156
pbrookacf930a2007-05-29 14:57:59 +0000157#define MACSR_PAV0 0x100
158#define MACSR_OMC 0x080
159#define MACSR_SU 0x040
160#define MACSR_FI 0x020
161#define MACSR_RT 0x010
162#define MACSR_N 0x008
163#define MACSR_Z 0x004
164#define MACSR_V 0x002
165#define MACSR_EV 0x001
166
Andreas Färbercb3fb382013-01-18 14:20:52 +0100167void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
pbrookacf930a2007-05-29 14:57:59 +0000168void m68k_set_macsr(CPUM68KState *env, uint32_t val);
pbrook20dcee92007-06-03 11:13:39 +0000169void m68k_switch_sp(CPUM68KState *env);
pbrooke6e59062006-10-22 00:18:54 +0000170
171#define M68K_FPCR_PREC (1 << 6)
172
pbrooka87295e2007-05-26 15:09:38 +0000173void do_m68k_semihosting(CPUM68KState *env, int nr);
174
pbrookd315c882007-06-03 12:35:08 +0000175/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
176 Each feature covers the subset of instructions common to the
177 ISA revisions mentioned. */
178
pbrook0402f762007-05-26 16:52:21 +0000179enum m68k_features {
180 M68K_FEATURE_CF_ISA_A,
pbrookd315c882007-06-03 12:35:08 +0000181 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
182 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
183 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
pbrook0402f762007-05-26 16:52:21 +0000184 M68K_FEATURE_CF_FPU,
185 M68K_FEATURE_CF_MAC,
186 M68K_FEATURE_CF_EMAC,
pbrookd315c882007-06-03 12:35:08 +0000187 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
188 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
pbrooke6dbd3b2007-05-26 21:16:48 +0000189 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
190 M68K_FEATURE_WORD_INDEX /* word sized address index registers. */
pbrook0402f762007-05-26 16:52:21 +0000191};
192
193static inline int m68k_feature(CPUM68KState *env, int feature)
194{
195 return (env->features & (1u << feature)) != 0;
196}
197
Stefan Weil9a78eea2010-10-22 23:03:33 +0200198void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
Laurent Vivier009a4352009-05-09 22:21:39 +0200199
pbrook0402f762007-05-26 16:52:21 +0000200void register_m68k_insns (CPUM68KState *env);
201
pbrooke6e59062006-10-22 00:18:54 +0000202#ifdef CONFIG_USER_ONLY
203/* Linux uses 8k pages. */
204#define TARGET_PAGE_BITS 13
205#else
ths5fafdf22007-09-16 21:08:06 +0000206/* Smallest TLB entry size is 1k. */
pbrooke6e59062006-10-22 00:18:54 +0000207#define TARGET_PAGE_BITS 10
208#endif
ths9467d442007-06-03 21:02:38 +0000209
Richard Henderson52705892010-03-10 14:33:23 -0800210#define TARGET_PHYS_ADDR_SPACE_BITS 32
211#define TARGET_VIRT_ADDR_SPACE_BITS 32
212
Eduardo Habkost2994fd92015-02-26 17:37:49 -0300213#define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
Andreas Färberc7937d92013-01-18 14:03:58 +0100214
ths9467d442007-06-03 21:02:38 +0000215#define cpu_exec cpu_m68k_exec
ths9467d442007-06-03 21:02:38 +0000216#define cpu_signal_handler cpu_m68k_signal_handler
Laurent Vivier009a4352009-05-09 22:21:39 +0200217#define cpu_list m68k_cpu_list
ths9467d442007-06-03 21:02:38 +0000218
j_mayer6ebbf392007-10-14 07:07:08 +0000219/* MMU modes definitions */
220#define MMU_MODE0_SUFFIX _kernel
221#define MMU_MODE1_SUFFIX _user
222#define MMU_USER_IDX 1
Benjamin Herrenschmidt97ed5cc2015-08-17 17:34:10 +1000223static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
j_mayer6ebbf392007-10-14 07:07:08 +0000224{
225 return (env->sr & SR_S) == 0 ? 1 : 0;
226}
227
Andreas Färber75104542013-08-26 03:01:33 +0200228int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
Blue Swirl97b348e2011-08-01 16:12:17 +0000229 int mmu_idx);
aurel32aaedd1f2009-03-07 21:48:08 +0000230
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100231#include "exec/cpu-all.h"
aliguori622ed362008-11-18 19:36:03 +0000232
Andreas Färber2b3e3cf2012-03-14 01:38:22 +0100233static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
aliguori6b917542008-11-18 19:46:41 +0000234 target_ulong *cs_base, int *flags)
235{
236 *pc = env->pc;
237 *cs_base = 0;
238 *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
239 | (env->sr & SR_S) /* Bit 13 */
240 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
241}
242
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100243#include "exec/exec-all.h"
Blue Swirlf081c762011-05-21 07:10:23 +0000244
pbrooke6e59062006-10-22 00:18:54 +0000245#endif