Stefano Garzarella | d0fb965 | 2021-05-17 17:16:58 +0200 | [diff] [blame] | 1 | # See docs/devel/tracing.rst for syntax documentation. |
Daniel P. Berrange | 0b8276d | 2016-06-16 09:40:17 +0100 | [diff] [blame] | 2 | |
Markus Armbruster | 500016e | 2019-03-14 19:09:26 +0100 | [diff] [blame] | 3 | # virt-acpi-build.c |
Daniel P. Berrange | 0b8276d | 2016-06-16 09:40:17 +0100 | [diff] [blame] | 4 | virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." |
Eric Auger | cac994e | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 5 | |
Markus Armbruster | 500016e | 2019-03-14 19:09:26 +0100 | [diff] [blame] | 6 | # smmu-common.c |
Eric Auger | 9364194 | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 7 | smmu_add_mr(const char *name) "%s" |
Eric Auger | 9364194 | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 8 | smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64 |
| 9 | smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64 |
| 10 | smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64 |
| 11 | smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB" |
| 12 | smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64 |
Eric Auger | cc27ed8 | 2018-06-26 17:50:42 +0100 | [diff] [blame] | 13 | smmu_iotlb_inv_all(void) "IOTLB invalidate all" |
| 14 | smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d" |
| 15 | smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64 |
Eric Auger | 832e422 | 2018-06-26 17:50:42 +0100 | [diff] [blame] | 16 | smmu_inv_notifiers_mr(const char *name) "iommu mr=%s" |
Eric Auger | 6808bca | 2020-07-28 17:08:06 +0200 | [diff] [blame] | 17 | smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" |
| 18 | smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" |
Eric Auger | 9e54dee | 2020-07-28 17:08:09 +0200 | [diff] [blame] | 19 | smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d addr=0x%"PRIx64" tg=%d level=%d" |
Prem Mallappa | 10a83cb | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 20 | |
Markus Armbruster | 500016e | 2019-03-14 19:09:26 +0100 | [diff] [blame] | 21 | # smmuv3.c |
Prem Mallappa | 10a83cb | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 22 | smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" |
Eric Auger | 6a73603 | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 23 | smmuv3_trigger_irq(int irq) "irq=%d" |
| 24 | smmuv3_write_gerror(uint32_t toggled, uint32_t gerror) "toggled=0x%x, new GERROR=0x%x" |
| 25 | smmuv3_write_gerrorn(uint32_t acked, uint32_t gerrorn) "acked=0x%x, new GERRORN=0x%x" |
Eric Auger | dadd1a0 | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 26 | smmuv3_unhandled_cmd(uint32_t type) "Unhandled command type=%d" |
| 27 | smmuv3_cmdq_consume(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod=%d cons=%d prod.wrap=%d cons.wrap=%d" |
| 28 | smmuv3_cmdq_opcode(const char *opcode) "<--- %s" |
| 29 | smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, uint8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d " |
| 30 | smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) "Error on %s command execution: %d" |
Eric Auger | fae4be3 | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 31 | smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" |
Eric Auger | fe2f5cb | 2021-03-09 11:27:42 +0100 | [diff] [blame] | 32 | smmuv3_record_event(const char *type, uint32_t sid) "%s sid=0x%x" |
| 33 | smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "sid=0x%x features:0x%x, sid_split:0x%x" |
Eric Auger | 9bde7f0 | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 34 | smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offset, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRIx64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_ste:%d" |
| 35 | smmuv3_get_ste(uint64_t addr) "STE addr: 0x%"PRIx64 |
Eric Auger | fe2f5cb | 2021-03-09 11:27:42 +0100 | [diff] [blame] | 36 | smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x bypass (smmu disabled) iova:0x%"PRIx64" is_write=%d" |
| 37 | smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x STE bypass iova:0x%"PRIx64" is_write=%d" |
| 38 | smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x abort on iova:0x%"PRIx64" is_write=%d" |
| 39 | smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t translated, int perm) "%s sid=0x%x iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x" |
Eric Auger | 9bde7f0 | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 40 | smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64 |
Eric Auger | 9bde7f0 | 2018-05-04 18:05:51 +0100 | [diff] [blame] | 41 | smmuv3_decode_cd(uint32_t oas) "oas=%d" |
Eric Auger | e7c3b9d | 2020-07-28 17:08:14 +0200 | [diff] [blame] | 42 | smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d" |
Eric Auger | fe2f5cb | 2021-03-09 11:27:42 +0100 | [diff] [blame] | 43 | smmuv3_cmdq_cfgi_ste(int streamid) "streamid= 0x%x" |
Dr. David Alan Gilbert | 43f828e | 2020-10-14 20:33:55 +0100 | [diff] [blame] | 44 | smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x" |
Eric Auger | fe2f5cb | 2021-03-09 11:27:42 +0100 | [diff] [blame] | 45 | smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x" |
| 46 | smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)" |
| 47 | smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)" |
| 48 | smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d" |
Eric Auger | cc27ed8 | 2018-06-26 17:50:42 +0100 | [diff] [blame] | 49 | smmuv3_cmdq_tlbi_nh(void) "" |
| 50 | smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d" |
Eric Auger | fe2f5cb | 2021-03-09 11:27:42 +0100 | [diff] [blame] | 51 | smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x" |
Eric Auger | 832e422 | 2018-06-26 17:50:42 +0100 | [diff] [blame] | 52 | smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" |
| 53 | smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" |
Eric Auger | d529156 | 2020-07-28 17:08:11 +0200 | [diff] [blame] | 54 | smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64 |
Eric Auger | 832e422 | 2018-06-26 17:50:42 +0100 | [diff] [blame] | 55 | |