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Paul Brookf7c70322009-11-19 16:45:21 +00001/*
2 * Cortex-A9MPCore internal peripheral emulation.
3 *
4 * Copyright (c) 2009 CodeSourcery.
Peter Maydellb12080c2011-12-01 21:16:34 +00005 * Copyright (c) 2011 Linaro Limited.
6 * Written by Paul Brook, Peter Maydell.
Paul Brookf7c70322009-11-19 16:45:21 +00007 *
Matthew Fernandez8e31bf32011-06-26 12:21:35 +10008 * This code is licensed under the GPL.
Paul Brookf7c70322009-11-19 16:45:21 +00009 */
10
Peter Maydell17b7f2d2016-01-26 18:17:28 +000011#include "qemu/osdep.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010012#include "qapi/error.h"
Andreas Färberde4c2dc2013-06-30 20:44:23 +020013#include "hw/cpu/a9mpcore.h"
Paolo Bonzini7d0c99a2015-12-04 11:10:07 +010014#include "qom/cpu.h"
Peter Maydellb12080c2011-12-01 21:16:34 +000015
Peter Maydellddd76162012-04-13 11:39:08 +000016static void a9mp_priv_set_irq(void *opaque, int irq, int level)
17{
Peter Crosthwaite845769f2013-02-28 18:23:13 +000018 A9MPPrivState *s = (A9MPPrivState *)opaque;
Andreas Färber9b5f9522013-06-30 19:01:18 +020019
20 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
Peter Maydellddd76162012-04-13 11:39:08 +000021}
22
Andreas Färber753bc6e2013-06-30 19:52:31 +020023static void a9mp_priv_initfn(Object *obj)
24{
25 A9MPPrivState *s = A9MPCORE_PRIV(obj);
26
27 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
28 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
Andreas Färber9b5f9522013-06-30 19:01:18 +020029
Andreas Färberfc719d72013-06-30 19:29:36 +020030 object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU);
31 qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
Andreas Färbereb110bd2013-06-30 20:30:27 +020032
Peter Crosthwaite4c25f362013-12-10 13:24:51 +000033 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
34 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
35
François LEGAL57e72f22013-12-01 23:37:11 -080036 object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER);
37 qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default());
38
Andreas Färbereb110bd2013-06-30 20:30:27 +020039 object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER);
40 qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default());
41
42 object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER);
43 qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
Andreas Färber753bc6e2013-06-30 19:52:31 +020044}
45
Andreas Färber837cf102013-06-30 20:36:15 +020046static void a9mp_priv_realize(DeviceState *dev, Error **errp)
Peter Maydellb12080c2011-12-01 21:16:34 +000047{
Andreas Färber837cf102013-06-30 20:36:15 +020048 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
Andreas Färber5126fec2013-06-30 19:07:29 +020049 A9MPPrivState *s = A9MPCORE_PRIV(dev);
François LEGAL57e72f22013-12-01 23:37:11 -080050 DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
51 SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev,
52 *wdtbusdev;
Andreas Färber837cf102013-06-30 20:36:15 +020053 Error *err = NULL;
Peter Maydellb12080c2011-12-01 21:16:34 +000054 int i;
Peter Maydell4182bbb2015-09-08 17:38:43 +010055 bool has_el3;
56 Object *cpuobj;
Peter Maydellb12080c2011-12-01 21:16:34 +000057
Peter Crosthwaite4c25f362013-12-10 13:24:51 +000058 scudev = DEVICE(&s->scu);
59 qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
60 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
61 if (err != NULL) {
62 error_propagate(errp, err);
63 return;
64 }
65 scubusdev = SYS_BUS_DEVICE(&s->scu);
66
Andreas Färber9b5f9522013-06-30 19:01:18 +020067 gicdev = DEVICE(&s->gic);
68 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
69 qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
Peter Maydell4182bbb2015-09-08 17:38:43 +010070
71 /* Make the GIC's TZ support match the CPUs. We assume that
72 * either all the CPUs have TZ, or none do.
73 */
74 cpuobj = OBJECT(qemu_get_cpu(0));
Edgar E. Iglesias6533a1f2015-09-14 14:39:49 +010075 has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
Peter Maydell4182bbb2015-09-08 17:38:43 +010076 object_property_get_bool(cpuobj, "has_el3", &error_abort);
77 qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
78
Andreas Färber837cf102013-06-30 20:36:15 +020079 object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
80 if (err != NULL) {
81 error_propagate(errp, err);
82 return;
83 }
Andreas Färber9b5f9522013-06-30 19:01:18 +020084 gicbusdev = SYS_BUS_DEVICE(&s->gic);
Peter Maydellddd76162012-04-13 11:39:08 +000085
86 /* Pass through outbound IRQ lines from the GIC */
Andreas Färber837cf102013-06-30 20:36:15 +020087 sysbus_pass_irq(sbd, gicbusdev);
Peter Maydellddd76162012-04-13 11:39:08 +000088
89 /* Pass through inbound GPIO lines to the GIC */
Andreas Färber837cf102013-06-30 20:36:15 +020090 qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
Peter Maydellb12080c2011-12-01 21:16:34 +000091
François LEGAL57e72f22013-12-01 23:37:11 -080092 gtimerdev = DEVICE(&s->gtimer);
93 qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
94 object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
95 if (err != NULL) {
96 error_propagate(errp, err);
97 return;
98 }
99 gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer);
100
Andreas Färbereb110bd2013-06-30 20:30:27 +0200101 mptimerdev = DEVICE(&s->mptimer);
102 qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
Andreas Färber837cf102013-06-30 20:36:15 +0200103 object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
104 if (err != NULL) {
105 error_propagate(errp, err);
106 return;
107 }
Peter Crosthwaited3053e62013-12-10 13:24:51 +0000108 mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer);
Peter Crosthwaitecde45772013-02-28 18:23:13 +0000109
Andreas Färbereb110bd2013-06-30 20:30:27 +0200110 wdtdev = DEVICE(&s->wdt);
111 qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
Andreas Färber837cf102013-06-30 20:36:15 +0200112 object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
113 if (err != NULL) {
114 error_propagate(errp, err);
115 return;
116 }
Andreas Färbereb110bd2013-06-30 20:30:27 +0200117 wdtbusdev = SYS_BUS_DEVICE(&s->wdt);
Peter Maydellb12080c2011-12-01 21:16:34 +0000118
119 /* Memory map (addresses are offsets from PERIPHBASE):
120 * 0x0000-0x00ff -- Snoop Control Unit
121 * 0x0100-0x01ff -- GIC CPU interface
122 * 0x0200-0x02ff -- Global Timer
123 * 0x0300-0x05ff -- nothing
124 * 0x0600-0x06ff -- private timers and watchdogs
125 * 0x0700-0x0fff -- nothing
126 * 0x1000-0x1fff -- GIC Distributor
Peter Maydellb12080c2011-12-01 21:16:34 +0000127 */
Peter Crosthwaite353575f2013-02-28 18:23:14 +0000128 memory_region_add_subregion(&s->container, 0,
129 sysbus_mmio_get_region(scubusdev, 0));
Peter Maydellb12080c2011-12-01 21:16:34 +0000130 /* GIC CPU interface */
Peter Maydellddd76162012-04-13 11:39:08 +0000131 memory_region_add_subregion(&s->container, 0x100,
132 sysbus_mmio_get_region(gicbusdev, 1));
François LEGAL57e72f22013-12-01 23:37:11 -0800133 memory_region_add_subregion(&s->container, 0x200,
134 sysbus_mmio_get_region(gtimerbusdev, 0));
Peter Maydellb12080c2011-12-01 21:16:34 +0000135 /* Note that the A9 exposes only the "timer/watchdog for this core"
136 * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
137 */
138 memory_region_add_subregion(&s->container, 0x600,
Peter Crosthwaited3053e62013-12-10 13:24:51 +0000139 sysbus_mmio_get_region(mptimerbusdev, 0));
Peter Maydellb12080c2011-12-01 21:16:34 +0000140 memory_region_add_subregion(&s->container, 0x620,
Peter Crosthwaitecde45772013-02-28 18:23:13 +0000141 sysbus_mmio_get_region(wdtbusdev, 0));
Peter Maydellddd76162012-04-13 11:39:08 +0000142 memory_region_add_subregion(&s->container, 0x1000,
143 sysbus_mmio_get_region(gicbusdev, 0));
Peter Maydellb12080c2011-12-01 21:16:34 +0000144
Peter Maydellddd76162012-04-13 11:39:08 +0000145 /* Wire up the interrupt from each watchdog and timer.
François LEGAL57e72f22013-12-01 23:37:11 -0800146 * For each core the global timer is PPI 27, the private
147 * timer is PPI 29 and the watchdog PPI 30.
Peter Maydellddd76162012-04-13 11:39:08 +0000148 */
149 for (i = 0; i < s->num_cpu; i++) {
150 int ppibase = (s->num_irq - 32) + i * 32;
François LEGAL57e72f22013-12-01 23:37:11 -0800151 sysbus_connect_irq(gtimerbusdev, i,
152 qdev_get_gpio_in(gicdev, ppibase + 27));
Peter Crosthwaited3053e62013-12-10 13:24:51 +0000153 sysbus_connect_irq(mptimerbusdev, i,
Andreas Färber9b5f9522013-06-30 19:01:18 +0200154 qdev_get_gpio_in(gicdev, ppibase + 29));
Peter Crosthwaitecde45772013-02-28 18:23:13 +0000155 sysbus_connect_irq(wdtbusdev, i,
Andreas Färber9b5f9522013-06-30 19:01:18 +0200156 qdev_get_gpio_in(gicdev, ppibase + 30));
Peter Maydellb12080c2011-12-01 21:16:34 +0000157 }
Peter Maydellb12080c2011-12-01 21:16:34 +0000158}
159
Anthony Liguori39bffca2011-12-07 21:34:16 -0600160static Property a9mp_priv_properties[] = {
Peter Crosthwaite845769f2013-02-28 18:23:13 +0000161 DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600162 /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
163 * IRQ lines (with another 32 internal). We default to 64+32, which
164 * is the number provided by the Cortex-A9MP test chip in the
165 * Realview PBX-A9 and Versatile Express A9 development boards.
166 * Other boards may differ and should set this property appropriately.
167 */
Peter Crosthwaite845769f2013-02-28 18:23:13 +0000168 DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600169 DEFINE_PROP_END_OF_LIST(),
170};
171
Anthony Liguori999e12b2012-01-24 13:12:29 -0600172static void a9mp_priv_class_init(ObjectClass *klass, void *data)
173{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600174 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600175
Andreas Färber837cf102013-06-30 20:36:15 +0200176 dc->realize = a9mp_priv_realize;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600177 dc->props = a9mp_priv_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600178}
179
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100180static const TypeInfo a9mp_priv_info = {
Andreas Färber5126fec2013-06-30 19:07:29 +0200181 .name = TYPE_A9MPCORE_PRIV,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600182 .parent = TYPE_SYS_BUS_DEVICE,
Peter Crosthwaite845769f2013-02-28 18:23:13 +0000183 .instance_size = sizeof(A9MPPrivState),
Andreas Färber753bc6e2013-06-30 19:52:31 +0200184 .instance_init = a9mp_priv_initfn,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600185 .class_init = a9mp_priv_class_init,
Paul Brookf7c70322009-11-19 16:45:21 +0000186};
187
Andreas Färber83f7d432012-02-09 15:20:55 +0100188static void a9mp_register_types(void)
Paul Brookf7c70322009-11-19 16:45:21 +0000189{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600190 type_register_static(&a9mp_priv_info);
Paul Brookf7c70322009-11-19 16:45:21 +0000191}
192
Andreas Färber83f7d432012-02-09 15:20:55 +0100193type_init(a9mp_register_types)