Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 1 | /* |
| 2 | * IDE test cases |
| 3 | * |
| 4 | * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
Peter Maydell | 5323926 | 2016-01-26 18:17:09 +0000 | [diff] [blame] | 25 | #include "qemu/osdep.h" |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 26 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 27 | |
| 28 | #include "libqtest.h" |
John Snow | 72c85e9 | 2015-04-28 15:27:51 -0400 | [diff] [blame] | 29 | #include "libqos/libqos.h" |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 30 | #include "libqos/pci-pc.h" |
| 31 | #include "libqos/malloc-pc.h" |
Markus Armbruster | 055a1ef | 2018-08-06 08:53:25 +0200 | [diff] [blame] | 32 | #include "qapi/qmp/qdict.h" |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 33 | #include "qemu-common.h" |
Paolo Bonzini | 58369e2 | 2016-03-15 17:22:36 +0100 | [diff] [blame] | 34 | #include "qemu/bswap.h" |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 35 | #include "hw/pci/pci_ids.h" |
| 36 | #include "hw/pci/pci_regs.h" |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 37 | |
Markus Armbruster | 055a1ef | 2018-08-06 08:53:25 +0200 | [diff] [blame] | 38 | /* TODO actually test the results and get rid of this */ |
| 39 | #define qmp_discard_response(...) qobject_unref(qmp(__VA_ARGS__)) |
| 40 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 41 | #define TEST_IMAGE_SIZE 64 * 1024 * 1024 |
| 42 | |
| 43 | #define IDE_PCI_DEV 1 |
| 44 | #define IDE_PCI_FUNC 1 |
| 45 | |
| 46 | #define IDE_BASE 0x1f0 |
| 47 | #define IDE_PRIMARY_IRQ 14 |
| 48 | |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 49 | #define ATAPI_BLOCK_SIZE 2048 |
| 50 | |
| 51 | /* How many bytes to receive via ATAPI PIO at one time. |
| 52 | * Must be less than 0xFFFF. */ |
| 53 | #define BYTE_COUNT_LIMIT 5120 |
| 54 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 55 | enum { |
| 56 | reg_data = 0x0, |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 57 | reg_feature = 0x1, |
Anton Nefedov | 29e1d47 | 2018-02-07 11:25:22 -0500 | [diff] [blame] | 58 | reg_error = 0x1, |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 59 | reg_nsectors = 0x2, |
| 60 | reg_lba_low = 0x3, |
| 61 | reg_lba_middle = 0x4, |
| 62 | reg_lba_high = 0x5, |
| 63 | reg_device = 0x6, |
| 64 | reg_status = 0x7, |
| 65 | reg_command = 0x7, |
| 66 | }; |
| 67 | |
| 68 | enum { |
| 69 | BSY = 0x80, |
| 70 | DRDY = 0x40, |
| 71 | DF = 0x20, |
| 72 | DRQ = 0x08, |
| 73 | ERR = 0x01, |
| 74 | }; |
| 75 | |
Anton Nefedov | 29e1d47 | 2018-02-07 11:25:22 -0500 | [diff] [blame] | 76 | /* Error field */ |
| 77 | enum { |
| 78 | ABRT = 0x04, |
| 79 | }; |
| 80 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 81 | enum { |
Kevin Wolf | c27d565 | 2013-06-05 15:17:56 +0200 | [diff] [blame] | 82 | DEV = 0x10, |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 83 | LBA = 0x40, |
| 84 | }; |
| 85 | |
| 86 | enum { |
| 87 | bmreg_cmd = 0x0, |
| 88 | bmreg_status = 0x2, |
| 89 | bmreg_prdt = 0x4, |
| 90 | }; |
| 91 | |
| 92 | enum { |
Anton Nefedov | 29e1d47 | 2018-02-07 11:25:22 -0500 | [diff] [blame] | 93 | CMD_DSM = 0x06, |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 94 | CMD_READ_DMA = 0xc8, |
| 95 | CMD_WRITE_DMA = 0xca, |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 96 | CMD_FLUSH_CACHE = 0xe7, |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 97 | CMD_IDENTIFY = 0xec, |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 98 | CMD_PACKET = 0xa0, |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 99 | |
| 100 | CMDF_ABORT = 0x100, |
Kevin Wolf | d7b7e58 | 2013-07-22 14:26:25 +0200 | [diff] [blame] | 101 | CMDF_NO_BM = 0x200, |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 102 | }; |
| 103 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 104 | enum { |
| 105 | BM_CMD_START = 0x1, |
| 106 | BM_CMD_WRITE = 0x8, /* write = from device to memory */ |
| 107 | }; |
| 108 | |
| 109 | enum { |
| 110 | BM_STS_ACTIVE = 0x1, |
| 111 | BM_STS_ERROR = 0x2, |
| 112 | BM_STS_INTR = 0x4, |
| 113 | }; |
| 114 | |
| 115 | enum { |
| 116 | PRDT_EOT = 0x80000000, |
| 117 | }; |
| 118 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 119 | #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) |
| 120 | #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) |
| 121 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 122 | static QPCIBus *pcibus = NULL; |
Paolo Bonzini | eb5937b | 2018-11-29 12:37:04 +0100 | [diff] [blame] | 123 | static QGuestAllocator guest_malloc; |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 124 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 125 | static char tmp_path[] = "/tmp/qtest.XXXXXX"; |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 126 | static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX"; |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 127 | |
| 128 | static void ide_test_start(const char *cmdline_fmt, ...) |
| 129 | { |
| 130 | va_list ap; |
| 131 | char *cmdline; |
| 132 | |
| 133 | va_start(ap, cmdline_fmt); |
| 134 | cmdline = g_strdup_vprintf(cmdline_fmt, ap); |
| 135 | va_end(ap); |
| 136 | |
| 137 | qtest_start(cmdline); |
Paolo Bonzini | eb5937b | 2018-11-29 12:37:04 +0100 | [diff] [blame] | 138 | pc_alloc_init(&guest_malloc, global_qtest, 0); |
John Snow | e42de18 | 2014-08-04 17:11:25 -0400 | [diff] [blame] | 139 | |
| 140 | g_free(cmdline); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | static void ide_test_quit(void) |
| 144 | { |
Thomas Huth | 3b6b0a8 | 2018-11-13 16:03:21 +0100 | [diff] [blame] | 145 | if (pcibus) { |
| 146 | qpci_free_pc(pcibus); |
| 147 | pcibus = NULL; |
| 148 | } |
Paolo Bonzini | eb5937b | 2018-11-29 12:37:04 +0100 | [diff] [blame] | 149 | alloc_destroy(&guest_malloc); |
Markus Armbruster | 1d9358e | 2013-06-20 08:55:29 +0200 | [diff] [blame] | 150 | qtest_end(); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 151 | } |
| 152 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 153 | static QPCIDevice *get_pci_device(QPCIBar *bmdma_bar, QPCIBar *ide_bar) |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 154 | { |
| 155 | QPCIDevice *dev; |
| 156 | uint16_t vendor_id, device_id; |
| 157 | |
| 158 | if (!pcibus) { |
Emanuele Giuseppe Esposito | 143e6db | 2018-07-19 13:50:27 +0200 | [diff] [blame] | 159 | pcibus = qpci_new_pc(global_qtest, NULL); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | /* Find PCI device and verify it's the right one */ |
| 163 | dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC)); |
| 164 | g_assert(dev != NULL); |
| 165 | |
| 166 | vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID); |
| 167 | device_id = qpci_config_readw(dev, PCI_DEVICE_ID); |
| 168 | g_assert(vendor_id == PCI_VENDOR_ID_INTEL); |
| 169 | g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1); |
| 170 | |
| 171 | /* Map bmdma BAR */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 172 | *bmdma_bar = qpci_iomap(dev, 4, NULL); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 173 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 174 | *ide_bar = qpci_legacy_iomap(dev, IDE_BASE); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 175 | |
| 176 | qpci_device_enable(dev); |
| 177 | |
| 178 | return dev; |
| 179 | } |
| 180 | |
| 181 | static void free_pci_device(QPCIDevice *dev) |
| 182 | { |
| 183 | /* libqos doesn't have a function for this, so free it manually */ |
| 184 | g_free(dev); |
| 185 | } |
| 186 | |
| 187 | typedef struct PrdtEntry { |
| 188 | uint32_t addr; |
| 189 | uint32_t size; |
| 190 | } QEMU_PACKED PrdtEntry; |
| 191 | |
| 192 | #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) |
| 193 | #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) |
| 194 | |
Anton Nefedov | 29e1d47 | 2018-02-07 11:25:22 -0500 | [diff] [blame] | 195 | static uint64_t trim_range_le(uint64_t sector, uint16_t count) |
| 196 | { |
| 197 | /* 2-byte range, 6-byte LBA */ |
| 198 | return cpu_to_le64(((uint64_t)count << 48) + sector); |
| 199 | } |
| 200 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 201 | static int send_dma_request(int cmd, uint64_t sector, int nb_sectors, |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 202 | PrdtEntry *prdt, int prdt_entries, |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 203 | void(*post_exec)(QPCIDevice *dev, QPCIBar ide_bar, |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 204 | uint64_t sector, int nb_sectors)) |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 205 | { |
| 206 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 207 | QPCIBar bmdma_bar, ide_bar; |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 208 | uintptr_t guest_prdt; |
| 209 | size_t len; |
| 210 | bool from_dev; |
| 211 | uint8_t status; |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 212 | int flags; |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 213 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 214 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 215 | |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 216 | flags = cmd & ~0xff; |
| 217 | cmd &= 0xff; |
| 218 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 219 | switch (cmd) { |
| 220 | case CMD_READ_DMA: |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 221 | case CMD_PACKET: |
| 222 | /* Assuming we only test data reads w/ ATAPI, otherwise we need to know |
| 223 | * the SCSI command being sent in the packet, too. */ |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 224 | from_dev = true; |
| 225 | break; |
Anton Nefedov | 29e1d47 | 2018-02-07 11:25:22 -0500 | [diff] [blame] | 226 | case CMD_DSM: |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 227 | case CMD_WRITE_DMA: |
| 228 | from_dev = false; |
| 229 | break; |
| 230 | default: |
| 231 | g_assert_not_reached(); |
| 232 | } |
| 233 | |
Kevin Wolf | d7b7e58 | 2013-07-22 14:26:25 +0200 | [diff] [blame] | 234 | if (flags & CMDF_NO_BM) { |
| 235 | qpci_config_writew(dev, PCI_COMMAND, |
| 236 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); |
| 237 | } |
| 238 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 239 | /* Select device 0 */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 240 | qpci_io_writeb(dev, ide_bar, reg_device, 0 | LBA); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 241 | |
| 242 | /* Stop any running transfer, clear any pending interrupt */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 243 | qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); |
| 244 | qpci_io_writeb(dev, bmdma_bar, bmreg_status, BM_STS_INTR); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 245 | |
| 246 | /* Setup PRDT */ |
| 247 | len = sizeof(*prdt) * prdt_entries; |
Paolo Bonzini | eb5937b | 2018-11-29 12:37:04 +0100 | [diff] [blame] | 248 | guest_prdt = guest_alloc(&guest_malloc, len); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 249 | memwrite(guest_prdt, prdt, len); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 250 | qpci_io_writel(dev, bmdma_bar, bmreg_prdt, guest_prdt); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 251 | |
| 252 | /* ATA DMA command */ |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 253 | if (cmd == CMD_PACKET) { |
| 254 | /* Enables ATAPI DMA; otherwise PIO is attempted */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 255 | qpci_io_writeb(dev, ide_bar, reg_feature, 0x01); |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 256 | } else { |
Anton Nefedov | 29e1d47 | 2018-02-07 11:25:22 -0500 | [diff] [blame] | 257 | if (cmd == CMD_DSM) { |
| 258 | /* trim bit */ |
| 259 | qpci_io_writeb(dev, ide_bar, reg_feature, 0x01); |
| 260 | } |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 261 | qpci_io_writeb(dev, ide_bar, reg_nsectors, nb_sectors); |
| 262 | qpci_io_writeb(dev, ide_bar, reg_lba_low, sector & 0xff); |
| 263 | qpci_io_writeb(dev, ide_bar, reg_lba_middle, (sector >> 8) & 0xff); |
| 264 | qpci_io_writeb(dev, ide_bar, reg_lba_high, (sector >> 16) & 0xff); |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 265 | } |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 266 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 267 | qpci_io_writeb(dev, ide_bar, reg_command, cmd); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 268 | |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 269 | if (post_exec) { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 270 | post_exec(dev, ide_bar, sector, nb_sectors); |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 271 | } |
| 272 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 273 | /* Start DMA transfer */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 274 | qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 275 | BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0)); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 276 | |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 277 | if (flags & CMDF_ABORT) { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 278 | qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 279 | } |
| 280 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 281 | /* Wait for the DMA transfer to complete */ |
| 282 | do { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 283 | status = qpci_io_readb(dev, bmdma_bar, bmreg_status); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 284 | } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE); |
| 285 | |
| 286 | g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR)); |
| 287 | |
| 288 | /* Check IDE status code */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 289 | assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), DRDY); |
| 290 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), BSY | DRQ); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 291 | |
| 292 | /* Reading the status register clears the IRQ */ |
| 293 | g_assert(!get_irq(IDE_PRIMARY_IRQ)); |
| 294 | |
| 295 | /* Stop DMA transfer if still active */ |
| 296 | if (status & BM_STS_ACTIVE) { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 297 | qpci_io_writeb(dev, bmdma_bar, bmreg_cmd, 0); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | free_pci_device(dev); |
| 301 | |
| 302 | return status; |
| 303 | } |
| 304 | |
| 305 | static void test_bmdma_simple_rw(void) |
| 306 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 307 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 308 | QPCIBar bmdma_bar, ide_bar; |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 309 | uint8_t status; |
| 310 | uint8_t *buf; |
| 311 | uint8_t *cmpbuf; |
| 312 | size_t len = 512; |
Paolo Bonzini | eb5937b | 2018-11-29 12:37:04 +0100 | [diff] [blame] | 313 | uintptr_t guest_buf = guest_alloc(&guest_malloc, len); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 314 | |
| 315 | PrdtEntry prdt[] = { |
Kevin Wolf | 262f27b | 2013-05-15 15:00:39 +0200 | [diff] [blame] | 316 | { |
| 317 | .addr = cpu_to_le32(guest_buf), |
| 318 | .size = cpu_to_le32(len | PRDT_EOT), |
| 319 | }, |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 320 | }; |
| 321 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 322 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 323 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 324 | buf = g_malloc(len); |
| 325 | cmpbuf = g_malloc(len); |
| 326 | |
| 327 | /* Write 0x55 pattern to sector 0 */ |
| 328 | memset(buf, 0x55, len); |
| 329 | memwrite(guest_buf, buf, len); |
| 330 | |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 331 | status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt, |
| 332 | ARRAY_SIZE(prdt), NULL); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 333 | g_assert_cmphex(status, ==, BM_STS_INTR); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 334 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 335 | |
| 336 | /* Write 0xaa pattern to sector 1 */ |
| 337 | memset(buf, 0xaa, len); |
| 338 | memwrite(guest_buf, buf, len); |
| 339 | |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 340 | status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, |
| 341 | ARRAY_SIZE(prdt), NULL); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 342 | g_assert_cmphex(status, ==, BM_STS_INTR); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 343 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 344 | |
| 345 | /* Read and verify 0x55 pattern in sector 0 */ |
| 346 | memset(cmpbuf, 0x55, len); |
| 347 | |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 348 | status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), NULL); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 349 | g_assert_cmphex(status, ==, BM_STS_INTR); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 350 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 351 | |
| 352 | memread(guest_buf, buf, len); |
| 353 | g_assert(memcmp(buf, cmpbuf, len) == 0); |
| 354 | |
| 355 | /* Read and verify 0xaa pattern in sector 1 */ |
| 356 | memset(cmpbuf, 0xaa, len); |
| 357 | |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 358 | status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), NULL); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 359 | g_assert_cmphex(status, ==, BM_STS_INTR); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 360 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 361 | |
| 362 | memread(guest_buf, buf, len); |
| 363 | g_assert(memcmp(buf, cmpbuf, len) == 0); |
| 364 | |
| 365 | |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 366 | free_pci_device(dev); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 367 | g_free(buf); |
| 368 | g_free(cmpbuf); |
| 369 | } |
| 370 | |
Anton Nefedov | 29e1d47 | 2018-02-07 11:25:22 -0500 | [diff] [blame] | 371 | static void test_bmdma_trim(void) |
| 372 | { |
| 373 | QPCIDevice *dev; |
| 374 | QPCIBar bmdma_bar, ide_bar; |
| 375 | uint8_t status; |
| 376 | const uint64_t trim_range[] = { trim_range_le(0, 2), |
| 377 | trim_range_le(6, 8), |
| 378 | trim_range_le(10, 1), |
| 379 | }; |
| 380 | const uint64_t bad_range = trim_range_le(TEST_IMAGE_SIZE / 512 - 1, 2); |
| 381 | size_t len = 512; |
| 382 | uint8_t *buf; |
Paolo Bonzini | eb5937b | 2018-11-29 12:37:04 +0100 | [diff] [blame] | 383 | uintptr_t guest_buf = guest_alloc(&guest_malloc, len); |
Anton Nefedov | 29e1d47 | 2018-02-07 11:25:22 -0500 | [diff] [blame] | 384 | |
| 385 | PrdtEntry prdt[] = { |
| 386 | { |
| 387 | .addr = cpu_to_le32(guest_buf), |
| 388 | .size = cpu_to_le32(len | PRDT_EOT), |
| 389 | }, |
| 390 | }; |
| 391 | |
| 392 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
| 393 | |
| 394 | buf = g_malloc(len); |
| 395 | |
| 396 | /* Normal request */ |
| 397 | *((uint64_t *)buf) = trim_range[0]; |
| 398 | *((uint64_t *)buf + 1) = trim_range[1]; |
| 399 | |
| 400 | memwrite(guest_buf, buf, 2 * sizeof(uint64_t)); |
| 401 | |
| 402 | status = send_dma_request(CMD_DSM, 0, 1, prdt, |
| 403 | ARRAY_SIZE(prdt), NULL); |
| 404 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 405 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
| 406 | |
| 407 | /* Request contains invalid range */ |
| 408 | *((uint64_t *)buf) = trim_range[2]; |
| 409 | *((uint64_t *)buf + 1) = bad_range; |
| 410 | |
| 411 | memwrite(guest_buf, buf, 2 * sizeof(uint64_t)); |
| 412 | |
| 413 | status = send_dma_request(CMD_DSM, 0, 1, prdt, |
| 414 | ARRAY_SIZE(prdt), NULL); |
| 415 | g_assert_cmphex(status, ==, BM_STS_INTR); |
| 416 | assert_bit_set(qpci_io_readb(dev, ide_bar, reg_status), ERR); |
| 417 | assert_bit_set(qpci_io_readb(dev, ide_bar, reg_error), ABRT); |
| 418 | |
| 419 | free_pci_device(dev); |
| 420 | g_free(buf); |
| 421 | } |
| 422 | |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 423 | static void test_bmdma_short_prdt(void) |
| 424 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 425 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 426 | QPCIBar bmdma_bar, ide_bar; |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 427 | uint8_t status; |
| 428 | |
| 429 | PrdtEntry prdt[] = { |
Kevin Wolf | 262f27b | 2013-05-15 15:00:39 +0200 | [diff] [blame] | 430 | { |
| 431 | .addr = 0, |
| 432 | .size = cpu_to_le32(0x10 | PRDT_EOT), |
| 433 | }, |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 434 | }; |
| 435 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 436 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 437 | |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 438 | /* Normal request */ |
| 439 | status = send_dma_request(CMD_READ_DMA, 0, 1, |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 440 | prdt, ARRAY_SIZE(prdt), NULL); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 441 | g_assert_cmphex(status, ==, 0); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 442 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 443 | |
| 444 | /* Abort the request before it completes */ |
| 445 | status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 446 | prdt, ARRAY_SIZE(prdt), NULL); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 447 | g_assert_cmphex(status, ==, 0); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 448 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 449 | free_pci_device(dev); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 450 | } |
| 451 | |
Stefan Hajnoczi | 5873281 | 2015-07-20 12:21:18 -0400 | [diff] [blame] | 452 | static void test_bmdma_one_sector_short_prdt(void) |
| 453 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 454 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 455 | QPCIBar bmdma_bar, ide_bar; |
Stefan Hajnoczi | 5873281 | 2015-07-20 12:21:18 -0400 | [diff] [blame] | 456 | uint8_t status; |
| 457 | |
| 458 | /* Read 2 sectors but only give 1 sector in PRDT */ |
| 459 | PrdtEntry prdt[] = { |
| 460 | { |
| 461 | .addr = 0, |
| 462 | .size = cpu_to_le32(0x200 | PRDT_EOT), |
| 463 | }, |
| 464 | }; |
| 465 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 466 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 467 | |
Stefan Hajnoczi | 5873281 | 2015-07-20 12:21:18 -0400 | [diff] [blame] | 468 | /* Normal request */ |
| 469 | status = send_dma_request(CMD_READ_DMA, 0, 2, |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 470 | prdt, ARRAY_SIZE(prdt), NULL); |
Stefan Hajnoczi | 5873281 | 2015-07-20 12:21:18 -0400 | [diff] [blame] | 471 | g_assert_cmphex(status, ==, 0); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 472 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Stefan Hajnoczi | 5873281 | 2015-07-20 12:21:18 -0400 | [diff] [blame] | 473 | |
| 474 | /* Abort the request before it completes */ |
| 475 | status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 2, |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 476 | prdt, ARRAY_SIZE(prdt), NULL); |
Stefan Hajnoczi | 5873281 | 2015-07-20 12:21:18 -0400 | [diff] [blame] | 477 | g_assert_cmphex(status, ==, 0); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 478 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 479 | free_pci_device(dev); |
Stefan Hajnoczi | 5873281 | 2015-07-20 12:21:18 -0400 | [diff] [blame] | 480 | } |
| 481 | |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 482 | static void test_bmdma_long_prdt(void) |
| 483 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 484 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 485 | QPCIBar bmdma_bar, ide_bar; |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 486 | uint8_t status; |
| 487 | |
| 488 | PrdtEntry prdt[] = { |
Kevin Wolf | 262f27b | 2013-05-15 15:00:39 +0200 | [diff] [blame] | 489 | { |
| 490 | .addr = 0, |
| 491 | .size = cpu_to_le32(0x1000 | PRDT_EOT), |
| 492 | }, |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 493 | }; |
| 494 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 495 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 496 | |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 497 | /* Normal request */ |
| 498 | status = send_dma_request(CMD_READ_DMA, 0, 1, |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 499 | prdt, ARRAY_SIZE(prdt), NULL); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 500 | g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 501 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 502 | |
| 503 | /* Abort the request before it completes */ |
| 504 | status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 505 | prdt, ARRAY_SIZE(prdt), NULL); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 506 | g_assert_cmphex(status, ==, BM_STS_INTR); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 507 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 508 | free_pci_device(dev); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 509 | } |
| 510 | |
Kevin Wolf | d7b7e58 | 2013-07-22 14:26:25 +0200 | [diff] [blame] | 511 | static void test_bmdma_no_busmaster(void) |
| 512 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 513 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 514 | QPCIBar bmdma_bar, ide_bar; |
Kevin Wolf | d7b7e58 | 2013-07-22 14:26:25 +0200 | [diff] [blame] | 515 | uint8_t status; |
| 516 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 517 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 518 | |
Kevin Wolf | d7b7e58 | 2013-07-22 14:26:25 +0200 | [diff] [blame] | 519 | /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be |
| 520 | * able to access it anyway because the Bus Master bit in the PCI command |
| 521 | * register isn't set. This is complete nonsense, but it used to be pretty |
| 522 | * good at confusing and occasionally crashing qemu. */ |
| 523 | PrdtEntry prdt[4096] = { }; |
| 524 | |
| 525 | status = send_dma_request(CMD_READ_DMA | CMDF_NO_BM, 0, 512, |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 526 | prdt, ARRAY_SIZE(prdt), NULL); |
Kevin Wolf | d7b7e58 | 2013-07-22 14:26:25 +0200 | [diff] [blame] | 527 | |
| 528 | /* Not entirely clear what the expected result is, but this is what we get |
| 529 | * in practice. At least we want to be aware of any changes. */ |
| 530 | g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 531 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 532 | free_pci_device(dev); |
Kevin Wolf | d7b7e58 | 2013-07-22 14:26:25 +0200 | [diff] [blame] | 533 | } |
| 534 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 535 | static void test_bmdma_setup(void) |
| 536 | { |
| 537 | ide_test_start( |
Kevin Wolf | 572023f | 2018-06-13 11:01:30 +0200 | [diff] [blame] | 538 | "-drive file=%s,if=ide,cache=writeback,format=raw " |
| 539 | "-global ide-hd.serial=%s -global ide-hd.ver=%s", |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 540 | tmp_path, "testdisk", "version"); |
John Snow | baca2b9 | 2015-02-23 11:18:06 -0500 | [diff] [blame] | 541 | qtest_irq_intercept_in(global_qtest, "ioapic"); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 542 | } |
| 543 | |
| 544 | static void test_bmdma_teardown(void) |
| 545 | { |
| 546 | ide_test_quit(); |
| 547 | } |
| 548 | |
Kevin Wolf | 262f27b | 2013-05-15 15:00:39 +0200 | [diff] [blame] | 549 | static void string_cpu_to_be16(uint16_t *s, size_t bytes) |
| 550 | { |
| 551 | g_assert((bytes & 1) == 0); |
| 552 | bytes /= 2; |
| 553 | |
| 554 | while (bytes--) { |
| 555 | *s = cpu_to_be16(*s); |
| 556 | s++; |
| 557 | } |
| 558 | } |
| 559 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 560 | static void test_identify(void) |
| 561 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 562 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 563 | QPCIBar bmdma_bar, ide_bar; |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 564 | uint8_t data; |
| 565 | uint16_t buf[256]; |
| 566 | int i; |
| 567 | int ret; |
| 568 | |
| 569 | ide_test_start( |
Kevin Wolf | 572023f | 2018-06-13 11:01:30 +0200 | [diff] [blame] | 570 | "-drive file=%s,if=ide,cache=writeback,format=raw " |
| 571 | "-global ide-hd.serial=%s -global ide-hd.ver=%s", |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 572 | tmp_path, "testdisk", "version"); |
| 573 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 574 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 575 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 576 | /* IDENTIFY command on device 0*/ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 577 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 578 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_IDENTIFY); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 579 | |
| 580 | /* Read in the IDENTIFY buffer and check registers */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 581 | data = qpci_io_readb(dev, ide_bar, reg_device); |
Kevin Wolf | c27d565 | 2013-06-05 15:17:56 +0200 | [diff] [blame] | 582 | g_assert_cmpint(data & DEV, ==, 0); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 583 | |
| 584 | for (i = 0; i < 256; i++) { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 585 | data = qpci_io_readb(dev, ide_bar, reg_status); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 586 | assert_bit_set(data, DRDY | DRQ); |
| 587 | assert_bit_clear(data, BSY | DF | ERR); |
| 588 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 589 | buf[i] = qpci_io_readw(dev, ide_bar, reg_data); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 590 | } |
| 591 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 592 | data = qpci_io_readb(dev, ide_bar, reg_status); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 593 | assert_bit_set(data, DRDY); |
| 594 | assert_bit_clear(data, BSY | DF | ERR | DRQ); |
| 595 | |
| 596 | /* Check serial number/version in the buffer */ |
Kevin Wolf | 262f27b | 2013-05-15 15:00:39 +0200 | [diff] [blame] | 597 | string_cpu_to_be16(&buf[10], 20); |
| 598 | ret = memcmp(&buf[10], "testdisk ", 20); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 599 | g_assert(ret == 0); |
| 600 | |
Kevin Wolf | 262f27b | 2013-05-15 15:00:39 +0200 | [diff] [blame] | 601 | string_cpu_to_be16(&buf[23], 8); |
| 602 | ret = memcmp(&buf[23], "version ", 8); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 603 | g_assert(ret == 0); |
| 604 | |
| 605 | /* Write cache enabled bit */ |
| 606 | assert_bit_set(buf[85], 0x20); |
| 607 | |
| 608 | ide_test_quit(); |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 609 | free_pci_device(dev); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 610 | } |
| 611 | |
Evgeny Yakovlev | 2dd7e10 | 2016-07-18 22:39:51 +0300 | [diff] [blame] | 612 | /* |
| 613 | * Write sector 1 with random data to make IDE storage dirty |
| 614 | * Needed for flush tests so that flushes actually go though the block layer |
| 615 | */ |
| 616 | static void make_dirty(uint8_t device) |
| 617 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 618 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 619 | QPCIBar bmdma_bar, ide_bar; |
Evgeny Yakovlev | 2dd7e10 | 2016-07-18 22:39:51 +0300 | [diff] [blame] | 620 | uint8_t status; |
| 621 | size_t len = 512; |
| 622 | uintptr_t guest_buf; |
| 623 | void* buf; |
| 624 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 625 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 626 | |
Paolo Bonzini | eb5937b | 2018-11-29 12:37:04 +0100 | [diff] [blame] | 627 | guest_buf = guest_alloc(&guest_malloc, len); |
Evgeny Yakovlev | 2dd7e10 | 2016-07-18 22:39:51 +0300 | [diff] [blame] | 628 | buf = g_malloc(len); |
John Snow | 6048018 | 2017-02-08 12:05:33 -0500 | [diff] [blame] | 629 | memset(buf, rand() % 255 + 1, len); |
Evgeny Yakovlev | 2dd7e10 | 2016-07-18 22:39:51 +0300 | [diff] [blame] | 630 | g_assert(guest_buf); |
| 631 | g_assert(buf); |
| 632 | |
| 633 | memwrite(guest_buf, buf, len); |
| 634 | |
| 635 | PrdtEntry prdt[] = { |
| 636 | { |
| 637 | .addr = cpu_to_le32(guest_buf), |
| 638 | .size = cpu_to_le32(len | PRDT_EOT), |
| 639 | }, |
| 640 | }; |
| 641 | |
| 642 | status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, |
| 643 | ARRAY_SIZE(prdt), NULL); |
| 644 | g_assert_cmphex(status, ==, BM_STS_INTR); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 645 | assert_bit_clear(qpci_io_readb(dev, ide_bar, reg_status), DF | ERR); |
Evgeny Yakovlev | 2dd7e10 | 2016-07-18 22:39:51 +0300 | [diff] [blame] | 646 | |
| 647 | g_free(buf); |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 648 | free_pci_device(dev); |
Evgeny Yakovlev | 2dd7e10 | 2016-07-18 22:39:51 +0300 | [diff] [blame] | 649 | } |
| 650 | |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 651 | static void test_flush(void) |
| 652 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 653 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 654 | QPCIBar bmdma_bar, ide_bar; |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 655 | uint8_t data; |
| 656 | |
| 657 | ide_test_start( |
Kevin Wolf | b8e665e | 2014-11-20 16:27:09 +0100 | [diff] [blame] | 658 | "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw", |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 659 | tmp_path); |
| 660 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 661 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 662 | |
Evgeny Yakovlev | 2dd7e10 | 2016-07-18 22:39:51 +0300 | [diff] [blame] | 663 | qtest_irq_intercept_in(global_qtest, "ioapic"); |
| 664 | |
| 665 | /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ |
| 666 | make_dirty(0); |
| 667 | |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 668 | /* Delay the completion of the flush request until we explicitly do it */ |
Markus Armbruster | 5fb48d9 | 2015-10-01 10:59:55 +0200 | [diff] [blame] | 669 | g_free(hmp("qemu-io ide0-hd0 \"break flush_to_os A\"")); |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 670 | |
| 671 | /* FLUSH CACHE command on device 0*/ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 672 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 673 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 674 | |
| 675 | /* Check status while request is in flight*/ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 676 | data = qpci_io_readb(dev, ide_bar, reg_status); |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 677 | assert_bit_set(data, BSY | DRDY); |
| 678 | assert_bit_clear(data, DF | ERR | DRQ); |
| 679 | |
| 680 | /* Complete the command */ |
Markus Armbruster | 5fb48d9 | 2015-10-01 10:59:55 +0200 | [diff] [blame] | 681 | g_free(hmp("qemu-io ide0-hd0 \"resume A\"")); |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 682 | |
| 683 | /* Check registers */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 684 | data = qpci_io_readb(dev, ide_bar, reg_device); |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 685 | g_assert_cmpint(data & DEV, ==, 0); |
| 686 | |
Michael Roth | 22bfa16 | 2013-06-10 13:23:20 -0500 | [diff] [blame] | 687 | do { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 688 | data = qpci_io_readb(dev, ide_bar, reg_status); |
Michael Roth | 22bfa16 | 2013-06-10 13:23:20 -0500 | [diff] [blame] | 689 | } while (data & BSY); |
| 690 | |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 691 | assert_bit_set(data, DRDY); |
| 692 | assert_bit_clear(data, BSY | DF | ERR | DRQ); |
| 693 | |
| 694 | ide_test_quit(); |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 695 | free_pci_device(dev); |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 696 | } |
| 697 | |
John Snow | baca2b9 | 2015-02-23 11:18:06 -0500 | [diff] [blame] | 698 | static void test_retry_flush(const char *machine) |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 699 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 700 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 701 | QPCIBar bmdma_bar, ide_bar; |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 702 | uint8_t data; |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 703 | |
| 704 | prepare_blkdebug_script(debug_path, "flush_to_disk"); |
| 705 | |
| 706 | ide_test_start( |
Kevin Wolf | b8e665e | 2014-11-20 16:27:09 +0100 | [diff] [blame] | 707 | "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw," |
| 708 | "rerror=stop,werror=stop", |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 709 | debug_path, tmp_path); |
| 710 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 711 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 712 | |
Evgeny Yakovlev | 2dd7e10 | 2016-07-18 22:39:51 +0300 | [diff] [blame] | 713 | qtest_irq_intercept_in(global_qtest, "ioapic"); |
| 714 | |
| 715 | /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */ |
| 716 | make_dirty(0); |
| 717 | |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 718 | /* FLUSH CACHE command on device 0*/ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 719 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 720 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 721 | |
| 722 | /* Check status while request is in flight*/ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 723 | data = qpci_io_readb(dev, ide_bar, reg_status); |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 724 | assert_bit_set(data, BSY | DRDY); |
| 725 | assert_bit_clear(data, DF | ERR | DRQ); |
| 726 | |
John Snow | 8fe941f | 2015-04-28 15:27:51 -0400 | [diff] [blame] | 727 | qmp_eventwait("STOP"); |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 728 | |
| 729 | /* Complete the command */ |
Markus Armbruster | 62fff69 | 2018-08-06 08:53:32 +0200 | [diff] [blame] | 730 | qmp_discard_response("{'execute':'cont' }"); |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 731 | |
| 732 | /* Check registers */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 733 | data = qpci_io_readb(dev, ide_bar, reg_device); |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 734 | g_assert_cmpint(data & DEV, ==, 0); |
| 735 | |
| 736 | do { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 737 | data = qpci_io_readb(dev, ide_bar, reg_status); |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 738 | } while (data & BSY); |
| 739 | |
| 740 | assert_bit_set(data, DRDY); |
| 741 | assert_bit_clear(data, BSY | DF | ERR | DRQ); |
| 742 | |
| 743 | ide_test_quit(); |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 744 | free_pci_device(dev); |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 745 | } |
| 746 | |
Kevin Wolf | f7f3ff1 | 2014-08-12 18:29:41 +0200 | [diff] [blame] | 747 | static void test_flush_nodev(void) |
| 748 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 749 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 750 | QPCIBar bmdma_bar, ide_bar; |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 751 | |
Kevin Wolf | f7f3ff1 | 2014-08-12 18:29:41 +0200 | [diff] [blame] | 752 | ide_test_start(""); |
| 753 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 754 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 755 | |
Kevin Wolf | f7f3ff1 | 2014-08-12 18:29:41 +0200 | [diff] [blame] | 756 | /* FLUSH CACHE command on device 0*/ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 757 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 758 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); |
Kevin Wolf | f7f3ff1 | 2014-08-12 18:29:41 +0200 | [diff] [blame] | 759 | |
| 760 | /* Just testing that qemu doesn't crash... */ |
| 761 | |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 762 | free_pci_device(dev); |
Kevin Wolf | f7f3ff1 | 2014-08-12 18:29:41 +0200 | [diff] [blame] | 763 | ide_test_quit(); |
| 764 | } |
| 765 | |
Kevin Wolf | ce317e8 | 2017-08-09 17:02:12 +0100 | [diff] [blame] | 766 | static void test_flush_empty_drive(void) |
| 767 | { |
| 768 | QPCIDevice *dev; |
| 769 | QPCIBar bmdma_bar, ide_bar; |
| 770 | |
| 771 | ide_test_start("-device ide-cd,bus=ide.0"); |
| 772 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
| 773 | |
| 774 | /* FLUSH CACHE command on device 0 */ |
| 775 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 776 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_FLUSH_CACHE); |
| 777 | |
| 778 | /* Just testing that qemu doesn't crash... */ |
| 779 | |
| 780 | free_pci_device(dev); |
| 781 | ide_test_quit(); |
| 782 | } |
| 783 | |
Markus Armbruster | 041088c | 2015-12-02 21:20:33 +0100 | [diff] [blame] | 784 | static void test_pci_retry_flush(void) |
John Snow | baca2b9 | 2015-02-23 11:18:06 -0500 | [diff] [blame] | 785 | { |
| 786 | test_retry_flush("pc"); |
| 787 | } |
| 788 | |
Markus Armbruster | 041088c | 2015-12-02 21:20:33 +0100 | [diff] [blame] | 789 | static void test_isa_retry_flush(void) |
John Snow | baca2b9 | 2015-02-23 11:18:06 -0500 | [diff] [blame] | 790 | { |
| 791 | test_retry_flush("isapc"); |
| 792 | } |
| 793 | |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 794 | typedef struct Read10CDB { |
| 795 | uint8_t opcode; |
| 796 | uint8_t flags; |
| 797 | uint32_t lba; |
| 798 | uint8_t reserved; |
| 799 | uint16_t nblocks; |
| 800 | uint8_t control; |
| 801 | uint16_t padding; |
| 802 | } __attribute__((__packed__)) Read10CDB; |
| 803 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 804 | static void send_scsi_cdb_read10(QPCIDevice *dev, QPCIBar ide_bar, |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 805 | uint64_t lba, int nblocks) |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 806 | { |
| 807 | Read10CDB pkt = { .padding = 0 }; |
| 808 | int i; |
| 809 | |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 810 | g_assert_cmpint(lba, <=, UINT32_MAX); |
| 811 | g_assert_cmpint(nblocks, <=, UINT16_MAX); |
| 812 | g_assert_cmpint(nblocks, >=, 0); |
| 813 | |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 814 | /* Construct SCSI CDB packet */ |
| 815 | pkt.opcode = 0x28; |
| 816 | pkt.lba = cpu_to_be32(lba); |
| 817 | pkt.nblocks = cpu_to_be16(nblocks); |
| 818 | |
| 819 | /* Send Packet */ |
| 820 | for (i = 0; i < sizeof(Read10CDB)/2; i++) { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 821 | qpci_io_writew(dev, ide_bar, reg_data, |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 822 | le16_to_cpu(((uint16_t *)&pkt)[i])); |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 823 | } |
| 824 | } |
| 825 | |
| 826 | static void nsleep(int64_t nsecs) |
| 827 | { |
| 828 | const struct timespec val = { .tv_nsec = nsecs }; |
| 829 | nanosleep(&val, NULL); |
| 830 | clock_set(nsecs); |
| 831 | } |
| 832 | |
| 833 | static uint8_t ide_wait_clear(uint8_t flag) |
| 834 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 835 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 836 | QPCIBar bmdma_bar, ide_bar; |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 837 | uint8_t data; |
John Snow | 9c73517 | 2015-11-24 14:36:11 -0500 | [diff] [blame] | 838 | time_t st; |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 839 | |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 840 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 841 | |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 842 | /* Wait with a 5 second timeout */ |
John Snow | 9c73517 | 2015-11-24 14:36:11 -0500 | [diff] [blame] | 843 | time(&st); |
| 844 | while (true) { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 845 | data = qpci_io_readb(dev, ide_bar, reg_status); |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 846 | if (!(data & flag)) { |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 847 | free_pci_device(dev); |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 848 | return data; |
| 849 | } |
John Snow | 9c73517 | 2015-11-24 14:36:11 -0500 | [diff] [blame] | 850 | if (difftime(time(NULL), st) > 5.0) { |
| 851 | break; |
| 852 | } |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 853 | nsleep(400); |
| 854 | } |
| 855 | g_assert_not_reached(); |
| 856 | } |
| 857 | |
| 858 | static void ide_wait_intr(int irq) |
| 859 | { |
John Snow | 9c73517 | 2015-11-24 14:36:11 -0500 | [diff] [blame] | 860 | time_t st; |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 861 | bool intr; |
| 862 | |
John Snow | 9c73517 | 2015-11-24 14:36:11 -0500 | [diff] [blame] | 863 | time(&st); |
| 864 | while (true) { |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 865 | intr = get_irq(irq); |
| 866 | if (intr) { |
| 867 | return; |
| 868 | } |
John Snow | 9c73517 | 2015-11-24 14:36:11 -0500 | [diff] [blame] | 869 | if (difftime(time(NULL), st) > 5.0) { |
| 870 | break; |
| 871 | } |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 872 | nsleep(400); |
| 873 | } |
| 874 | |
| 875 | g_assert_not_reached(); |
| 876 | } |
| 877 | |
| 878 | static void cdrom_pio_impl(int nblocks) |
| 879 | { |
David Gibson | 9c268f8 | 2016-10-21 10:46:37 +1100 | [diff] [blame] | 880 | QPCIDevice *dev; |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 881 | QPCIBar bmdma_bar, ide_bar; |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 882 | FILE *fh; |
| 883 | int patt_blocks = MAX(16, nblocks); |
| 884 | size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks; |
| 885 | char *pattern = g_malloc(patt_len); |
| 886 | size_t rxsize = ATAPI_BLOCK_SIZE * nblocks; |
| 887 | uint16_t *rx = g_malloc0(rxsize); |
| 888 | int i, j; |
| 889 | uint8_t data; |
| 890 | uint16_t limit; |
John Snow | 543f8f1 | 2017-05-31 15:28:36 -0400 | [diff] [blame] | 891 | size_t ret; |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 892 | |
| 893 | /* Prepopulate the CDROM with an interesting pattern */ |
| 894 | generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE); |
| 895 | fh = fopen(tmp_path, "w+"); |
John Snow | 543f8f1 | 2017-05-31 15:28:36 -0400 | [diff] [blame] | 896 | ret = fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh); |
| 897 | g_assert_cmpint(ret, ==, patt_blocks); |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 898 | fclose(fh); |
| 899 | |
| 900 | ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 " |
| 901 | "-device ide-cd,drive=sr0,bus=ide.0", tmp_path); |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 902 | dev = get_pci_device(&bmdma_bar, &ide_bar); |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 903 | qtest_irq_intercept_in(global_qtest, "ioapic"); |
| 904 | |
| 905 | /* PACKET command on device 0 */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 906 | qpci_io_writeb(dev, ide_bar, reg_device, 0); |
| 907 | qpci_io_writeb(dev, ide_bar, reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF); |
| 908 | qpci_io_writeb(dev, ide_bar, reg_lba_high, (BYTE_COUNT_LIMIT >> 8 & 0xFF)); |
| 909 | qpci_io_writeb(dev, ide_bar, reg_command, CMD_PACKET); |
Peter Lieven | f348daf | 2015-11-20 15:29:02 +0100 | [diff] [blame] | 910 | /* HP0: Check_Status_A State */ |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 911 | nsleep(400); |
| 912 | data = ide_wait_clear(BSY); |
Peter Lieven | f348daf | 2015-11-20 15:29:02 +0100 | [diff] [blame] | 913 | /* HP1: Send_Packet State */ |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 914 | assert_bit_set(data, DRQ | DRDY); |
| 915 | assert_bit_clear(data, ERR | DF | BSY); |
| 916 | |
| 917 | /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */ |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 918 | send_scsi_cdb_read10(dev, ide_bar, 0, nblocks); |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 919 | |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 920 | /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes. |
| 921 | * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes. |
| 922 | * We allow an odd limit only when the remaining transfer size is |
| 923 | * less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only |
| 924 | * request n blocks, so our request size is always even. |
| 925 | * For this reason, we assume there is never a hanging byte to fetch. */ |
| 926 | g_assert(!(rxsize & 1)); |
| 927 | limit = BYTE_COUNT_LIMIT & ~1; |
| 928 | for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) { |
| 929 | size_t offset = i * (limit / 2); |
| 930 | size_t rem = (rxsize / 2) - offset; |
John Snow | a421f3c | 2015-11-20 17:53:55 -0500 | [diff] [blame] | 931 | |
| 932 | /* HP3: INTRQ_Wait */ |
| 933 | ide_wait_intr(IDE_PRIMARY_IRQ); |
| 934 | |
| 935 | /* HP2: Check_Status_B (and clear IRQ) */ |
Peter Lieven | f348daf | 2015-11-20 15:29:02 +0100 | [diff] [blame] | 936 | data = ide_wait_clear(BSY); |
| 937 | assert_bit_set(data, DRQ | DRDY); |
| 938 | assert_bit_clear(data, ERR | DF | BSY); |
John Snow | a421f3c | 2015-11-20 17:53:55 -0500 | [diff] [blame] | 939 | |
Peter Lieven | f348daf | 2015-11-20 15:29:02 +0100 | [diff] [blame] | 940 | /* HP4: Transfer_Data */ |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 941 | for (j = 0; j < MIN((limit / 2), rem); j++) { |
David Gibson | b4ba67d | 2016-10-24 15:52:06 +1100 | [diff] [blame] | 942 | rx[offset + j] = cpu_to_le16(qpci_io_readw(dev, ide_bar, |
| 943 | reg_data)); |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 944 | } |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 945 | } |
John Snow | a421f3c | 2015-11-20 17:53:55 -0500 | [diff] [blame] | 946 | |
| 947 | /* Check for final completion IRQ */ |
| 948 | ide_wait_intr(IDE_PRIMARY_IRQ); |
| 949 | |
| 950 | /* Sanity check final state */ |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 951 | data = ide_wait_clear(DRQ); |
| 952 | assert_bit_set(data, DRDY); |
| 953 | assert_bit_clear(data, DRQ | ERR | DF | BSY); |
| 954 | |
| 955 | g_assert_cmpint(memcmp(pattern, rx, rxsize), ==, 0); |
| 956 | g_free(pattern); |
| 957 | g_free(rx); |
| 958 | test_bmdma_teardown(); |
Marc-André Lureau | f5aa4bd | 2017-02-03 16:10:45 +0400 | [diff] [blame] | 959 | free_pci_device(dev); |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 960 | } |
| 961 | |
| 962 | static void test_cdrom_pio(void) |
| 963 | { |
| 964 | cdrom_pio_impl(1); |
| 965 | } |
| 966 | |
| 967 | static void test_cdrom_pio_large(void) |
| 968 | { |
| 969 | /* Test a few loops of the PIO DRQ mechanism. */ |
| 970 | cdrom_pio_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE); |
| 971 | } |
| 972 | |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 973 | |
| 974 | static void test_cdrom_dma(void) |
| 975 | { |
| 976 | static const size_t len = ATAPI_BLOCK_SIZE; |
John Snow | 543f8f1 | 2017-05-31 15:28:36 -0400 | [diff] [blame] | 977 | size_t ret; |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 978 | char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16); |
| 979 | char *rx = g_malloc0(len); |
| 980 | uintptr_t guest_buf; |
| 981 | PrdtEntry prdt[1]; |
| 982 | FILE *fh; |
| 983 | |
| 984 | ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 " |
| 985 | "-device ide-cd,drive=sr0,bus=ide.0", tmp_path); |
| 986 | qtest_irq_intercept_in(global_qtest, "ioapic"); |
| 987 | |
Paolo Bonzini | eb5937b | 2018-11-29 12:37:04 +0100 | [diff] [blame] | 988 | guest_buf = guest_alloc(&guest_malloc, len); |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 989 | prdt[0].addr = cpu_to_le32(guest_buf); |
| 990 | prdt[0].size = cpu_to_le32(len | PRDT_EOT); |
| 991 | |
| 992 | generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE); |
| 993 | fh = fopen(tmp_path, "w+"); |
John Snow | 543f8f1 | 2017-05-31 15:28:36 -0400 | [diff] [blame] | 994 | ret = fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh); |
| 995 | g_assert_cmpint(ret, ==, 16); |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 996 | fclose(fh); |
| 997 | |
| 998 | send_dma_request(CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10); |
| 999 | |
| 1000 | /* Read back data from guest memory into local qtest memory */ |
| 1001 | memread(guest_buf, rx, len); |
| 1002 | g_assert_cmpint(memcmp(pattern, rx, len), ==, 0); |
| 1003 | |
| 1004 | g_free(pattern); |
| 1005 | g_free(rx); |
| 1006 | test_bmdma_teardown(); |
| 1007 | } |
| 1008 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 1009 | int main(int argc, char **argv) |
| 1010 | { |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 1011 | int fd; |
| 1012 | int ret; |
| 1013 | |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 1014 | /* Create temporary blkdebug instructions */ |
| 1015 | fd = mkstemp(debug_path); |
| 1016 | g_assert(fd >= 0); |
| 1017 | close(fd); |
| 1018 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 1019 | /* Create a temporary raw image */ |
| 1020 | fd = mkstemp(tmp_path); |
| 1021 | g_assert(fd >= 0); |
| 1022 | ret = ftruncate(fd, TEST_IMAGE_SIZE); |
| 1023 | g_assert(ret == 0); |
| 1024 | close(fd); |
| 1025 | |
| 1026 | /* Run the tests */ |
| 1027 | g_test_init(&argc, &argv, NULL); |
| 1028 | |
| 1029 | qtest_add_func("/ide/identify", test_identify); |
| 1030 | |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 1031 | qtest_add_func("/ide/bmdma/setup", test_bmdma_setup); |
| 1032 | qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw); |
Anton Nefedov | 29e1d47 | 2018-02-07 11:25:22 -0500 | [diff] [blame] | 1033 | qtest_add_func("/ide/bmdma/trim", test_bmdma_trim); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 1034 | qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt); |
Stefan Hajnoczi | 5873281 | 2015-07-20 12:21:18 -0400 | [diff] [blame] | 1035 | qtest_add_func("/ide/bmdma/one_sector_short_prdt", |
| 1036 | test_bmdma_one_sector_short_prdt); |
Kevin Wolf | 948eaed | 2013-03-13 13:30:24 +0100 | [diff] [blame] | 1037 | qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt); |
Kevin Wolf | d7b7e58 | 2013-07-22 14:26:25 +0200 | [diff] [blame] | 1038 | qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster); |
Kevin Wolf | b95739d | 2013-05-08 11:34:20 +0200 | [diff] [blame] | 1039 | qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown); |
| 1040 | |
Kevin Wolf | bd07684 | 2013-06-05 15:17:58 +0200 | [diff] [blame] | 1041 | qtest_add_func("/ide/flush", test_flush); |
John Snow | baca2b9 | 2015-02-23 11:18:06 -0500 | [diff] [blame] | 1042 | qtest_add_func("/ide/flush/nodev", test_flush_nodev); |
Kevin Wolf | ce317e8 | 2017-08-09 17:02:12 +0100 | [diff] [blame] | 1043 | qtest_add_func("/ide/flush/empty_drive", test_flush_empty_drive); |
John Snow | baca2b9 | 2015-02-23 11:18:06 -0500 | [diff] [blame] | 1044 | qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush); |
| 1045 | qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush); |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 1046 | |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 1047 | qtest_add_func("/ide/cdrom/pio", test_cdrom_pio); |
| 1048 | qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large); |
John Snow | 00ea63f | 2015-09-17 14:17:05 -0400 | [diff] [blame] | 1049 | qtest_add_func("/ide/cdrom/dma", test_cdrom_dma); |
John Snow | f7ba8d7 | 2015-09-17 14:17:04 -0400 | [diff] [blame] | 1050 | |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 1051 | ret = g_test_run(); |
| 1052 | |
| 1053 | /* Cleanup */ |
| 1054 | unlink(tmp_path); |
Paolo Bonzini | 14a92e5 | 2014-08-04 17:11:04 -0400 | [diff] [blame] | 1055 | unlink(debug_path); |
Kevin Wolf | acbe480 | 2013-05-08 11:18:41 +0200 | [diff] [blame] | 1056 | |
| 1057 | return ret; |
| 1058 | } |