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bellardfdf9b3e2006-04-27 21:07:38 +00001/*
2 * SH4 emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardfdf9b3e2006-04-27 21:07:38 +00004 * Copyright (c) 2005 Samuel Tardieu
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellardfdf9b3e2006-04-27 21:07:38 +000018 */
19#ifndef _CPU_SH4_H
20#define _CPU_SH4_H
21
22#include "config.h"
Stefan Weil9a78eea2010-10-22 23:03:33 +020023#include "qemu-common.h"
bellardfdf9b3e2006-04-27 21:07:38 +000024
25#define TARGET_LONG_BITS 32
bellardfdf9b3e2006-04-27 21:07:38 +000026
aurel320fd3ca32008-09-02 16:18:28 +000027/* CPU Subtypes */
28#define SH_CPU_SH7750 (1 << 0)
29#define SH_CPU_SH7750S (1 << 1)
30#define SH_CPU_SH7750R (1 << 2)
31#define SH_CPU_SH7751 (1 << 3)
32#define SH_CPU_SH7751R (1 << 4)
aurel32a9c43f82008-12-13 18:57:28 +000033#define SH_CPU_SH7785 (1 << 5)
aurel320fd3ca32008-09-02 16:18:28 +000034#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
35#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
36
Andreas Färber9349b4f2012-03-14 01:38:32 +010037#define CPUArchState struct CPUSH4State
pbrookc2764712009-03-07 15:24:59 +000038
Paolo Bonzini022c62c2012-12-17 18:19:49 +010039#include "exec/cpu-defs.h"
bellardfdf9b3e2006-04-27 21:07:38 +000040
Paolo Bonzini6b4c3052012-10-24 13:12:00 +020041#include "fpu/softfloat.h"
bellardeda9b092006-06-14 15:02:05 +000042
bellardfdf9b3e2006-04-27 21:07:38 +000043#define TARGET_PAGE_BITS 12 /* 4k XXXXX */
44
Richard Henderson52705892010-03-10 14:33:23 -080045#define TARGET_PHYS_ADDR_SPACE_BITS 32
46#define TARGET_VIRT_ADDR_SPACE_BITS 32
47
Aurelien Jarno5ed9a252015-05-25 01:28:56 +020048#define SR_MD 30
49#define SR_RB 29
50#define SR_BL 28
51#define SR_FD 15
52#define SR_M 9
53#define SR_Q 8
54#define SR_I3 7
55#define SR_I2 6
56#define SR_I1 5
57#define SR_I0 4
58#define SR_S 1
59#define SR_T 0
bellardfdf9b3e2006-04-27 21:07:38 +000060
Aurelien Jarno26ac1ea2011-01-14 20:39:18 +010061#define FPSCR_MASK (0x003fffff)
62#define FPSCR_FR (1 << 21)
63#define FPSCR_SZ (1 << 20)
64#define FPSCR_PR (1 << 19)
65#define FPSCR_DN (1 << 18)
66#define FPSCR_CAUSE_MASK (0x3f << 12)
67#define FPSCR_CAUSE_SHIFT (12)
68#define FPSCR_CAUSE_E (1 << 17)
69#define FPSCR_CAUSE_V (1 << 16)
70#define FPSCR_CAUSE_Z (1 << 15)
71#define FPSCR_CAUSE_O (1 << 14)
72#define FPSCR_CAUSE_U (1 << 13)
73#define FPSCR_CAUSE_I (1 << 12)
74#define FPSCR_ENABLE_MASK (0x1f << 7)
75#define FPSCR_ENABLE_SHIFT (7)
76#define FPSCR_ENABLE_V (1 << 11)
77#define FPSCR_ENABLE_Z (1 << 10)
78#define FPSCR_ENABLE_O (1 << 9)
79#define FPSCR_ENABLE_U (1 << 8)
80#define FPSCR_ENABLE_I (1 << 7)
81#define FPSCR_FLAG_MASK (0x1f << 2)
82#define FPSCR_FLAG_SHIFT (2)
83#define FPSCR_FLAG_V (1 << 6)
84#define FPSCR_FLAG_Z (1 << 5)
85#define FPSCR_FLAG_O (1 << 4)
86#define FPSCR_FLAG_U (1 << 3)
87#define FPSCR_FLAG_I (1 << 2)
88#define FPSCR_RM_MASK (0x03 << 0)
89#define FPSCR_RM_NEAREST (0 << 0)
90#define FPSCR_RM_ZERO (1 << 0)
91
ths823029f2007-12-02 06:10:04 +000092#define DELAY_SLOT (1 << 0)
bellardfdf9b3e2006-04-27 21:07:38 +000093#define DELAY_SLOT_CONDITIONAL (1 << 1)
ths823029f2007-12-02 06:10:04 +000094#define DELAY_SLOT_TRUE (1 << 2)
95#define DELAY_SLOT_CLEARME (1 << 3)
96/* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
97 * after the delay slot should be taken or not. It is calculated from SR_T.
98 *
99 * It is unclear if it is permitted to modify the SR_T flag in a delay slot.
100 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
101 */
bellardfdf9b3e2006-04-27 21:07:38 +0000102
bellardfdf9b3e2006-04-27 21:07:38 +0000103typedef struct tlb_t {
bellardfdf9b3e2006-04-27 21:07:38 +0000104 uint32_t vpn; /* virtual page number */
bellardfdf9b3e2006-04-27 21:07:38 +0000105 uint32_t ppn; /* physical page number */
Aurelien Jarnoaf090492010-02-03 02:32:49 +0100106 uint32_t size; /* mapped page size in bytes */
107 uint8_t asid; /* address space identifier */
108 uint8_t v:1; /* validity */
109 uint8_t sz:2; /* page size */
110 uint8_t sh:1; /* share status */
111 uint8_t c:1; /* cacheability */
112 uint8_t pr:2; /* protection key */
113 uint8_t d:1; /* dirty */
114 uint8_t wt:1; /* write through */
115 uint8_t sa:3; /* space attribute (PCMCIA) */
116 uint8_t tc:1; /* timing control */
bellardfdf9b3e2006-04-27 21:07:38 +0000117} tlb_t;
118
119#define UTLB_SIZE 64
120#define ITLB_SIZE 4
121
j_mayer6ebbf392007-10-14 07:07:08 +0000122#define NB_MMU_MODES 2
Richard Henderson07f3c162015-08-30 09:28:52 -0700123#define TARGET_INSN_START_EXTRA_WORDS 1
j_mayer6ebbf392007-10-14 07:07:08 +0000124
aurel3271968fa2008-12-13 18:57:37 +0000125enum sh_features {
126 SH_FEATURE_SH4A = 1,
aurel32c2432a42009-02-07 15:18:14 +0000127 SH_FEATURE_BCR3_AND_BCR4 = 2,
aurel3271968fa2008-12-13 18:57:37 +0000128};
129
edgar_igl852d4812009-04-01 23:10:46 +0000130typedef struct memory_content {
131 uint32_t address;
132 uint32_t value;
133 struct memory_content *next;
134} memory_content;
135
bellardfdf9b3e2006-04-27 21:07:38 +0000136typedef struct CPUSH4State {
137 uint32_t flags; /* general execution flags */
138 uint32_t gregs[24]; /* general registers */
thse04ea3d2007-06-25 13:53:11 +0000139 float32 fregs[32]; /* floating point registers */
Aurelien Jarno34086942015-05-25 01:28:56 +0200140 uint32_t sr; /* status register (with T split out) */
Aurelien Jarno1d565b22015-05-25 01:28:56 +0200141 uint32_t sr_m; /* M bit of status register */
142 uint32_t sr_q; /* Q bit of status register */
Aurelien Jarno34086942015-05-25 01:28:56 +0200143 uint32_t sr_t; /* T bit of status register */
bellardfdf9b3e2006-04-27 21:07:38 +0000144 uint32_t ssr; /* saved status register */
145 uint32_t spc; /* saved program counter */
146 uint32_t gbr; /* global base register */
147 uint32_t vbr; /* vector base register */
148 uint32_t sgr; /* saved global register 15 */
149 uint32_t dbr; /* debug base register */
150 uint32_t pc; /* program counter */
151 uint32_t delayed_pc; /* target of delayed jump */
152 uint32_t mach; /* multiply and accumulate high */
153 uint32_t macl; /* multiply and accumulate low */
154 uint32_t pr; /* procedure register */
155 uint32_t fpscr; /* floating point status/control register */
156 uint32_t fpul; /* floating point communication register */
157
aurel3217b086f2008-09-01 22:12:14 +0000158 /* float point status register */
thsea6cf6b2007-06-22 11:12:01 +0000159 float_status fp_status;
bellardeda9b092006-06-14 15:02:05 +0000160
bellardfdf9b3e2006-04-27 21:07:38 +0000161 /* Those belong to the specific unit (SH7750) but are handled here */
162 uint32_t mmucr; /* MMU control register */
163 uint32_t pteh; /* page table entry high register */
164 uint32_t ptel; /* page table entry low register */
165 uint32_t ptea; /* page table entry assistance register */
166 uint32_t ttb; /* tranlation table base register */
167 uint32_t tea; /* TLB exception address register */
168 uint32_t tra; /* TRAPA exception register */
169 uint32_t expevt; /* exception event register */
170 uint32_t intevt; /* interrupt event register */
171
Aurelien Jarno4f6493f2011-01-14 20:39:18 +0100172 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
173 tlb_t utlb[UTLB_SIZE]; /* unified translation table */
174
175 uint32_t ldst;
176
177 CPU_COMMON
178
Andreas Färberf0c3c502013-08-26 21:22:53 +0200179 /* Fields from here on are preserved over CPU reset. */
Aurelien Jarno4f6493f2011-01-14 20:39:18 +0100180 int id; /* CPU model */
aurel320fd3ca32008-09-02 16:18:28 +0000181
Bobby Bingham21c04612013-11-24 14:03:05 -0600182 /* The features that we should emulate. See sh_features above. */
183 uint32_t features;
184
thse96e2042007-12-02 06:18:24 +0000185 void *intc_handle;
Aurelien Jarnoefac4152011-02-24 12:31:41 +0100186 int in_sleep; /* SR_BL ignored during sleep */
edgar_igl852d4812009-04-01 23:10:46 +0000187 memory_content *movcal_backup;
188 memory_content **movcal_backup_tail;
bellardfdf9b3e2006-04-27 21:07:38 +0000189} CPUSH4State;
190
Andreas Färber339894b2012-02-11 17:26:17 +0100191#include "cpu-qom.h"
192
Andreas Färberaa7408e2013-01-20 01:30:32 +0100193void sh4_translate_init(void);
Andreas Färber445e9572012-05-04 18:35:09 +0200194SuperHCPU *cpu_sh4_init(const char *cpu_model);
Peter Crosthwaiteea3e9842015-06-18 10:24:55 -0700195int cpu_sh4_exec(CPUState *s);
ths5fafdf22007-09-16 21:08:06 +0000196int cpu_sh4_signal_handler(int host_signum, void *pinfo,
ths5a7b5422007-01-31 12:16:51 +0000197 void *puc);
Andreas Färber75104542013-08-26 03:01:33 +0200198int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
199 int mmu_idx);
aurel3242083222008-12-11 22:42:50 +0000200
Stefan Weil9a78eea2010-10-22 23:03:33 +0200201void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
Paul Brook3c7b48b2010-03-01 04:11:28 +0000202#if !defined(CONFIG_USER_ONLY)
Aurelien Jarnoe0bcb9c2010-02-02 19:39:11 +0100203void cpu_sh4_invalidate_tlb(CPUSH4State *s);
Aurelien Jarnobc656a22011-01-26 02:16:39 +0100204uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
Avi Kivitya8170e52012-10-23 12:30:10 +0200205 hwaddr addr);
206void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
Aurelien Jarno9f973092011-01-26 02:07:50 +0100207 uint32_t mem_value);
Aurelien Jarnobc656a22011-01-26 02:16:39 +0100208uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
Avi Kivitya8170e52012-10-23 12:30:10 +0200209 hwaddr addr);
210void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
Aurelien Jarno9f973092011-01-26 02:07:50 +0100211 uint32_t mem_value);
Aurelien Jarnobc656a22011-01-26 02:16:39 +0100212uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
Avi Kivitya8170e52012-10-23 12:30:10 +0200213 hwaddr addr);
214void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
Aurelien Jarno9f973092011-01-26 02:07:50 +0100215 uint32_t mem_value);
Aurelien Jarnobc656a22011-01-26 02:16:39 +0100216uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
Avi Kivitya8170e52012-10-23 12:30:10 +0200217 hwaddr addr);
218void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
Aurelien Jarno9f973092011-01-26 02:07:50 +0100219 uint32_t mem_value);
Paul Brook3c7b48b2010-03-01 04:11:28 +0000220#endif
bellardfdf9b3e2006-04-27 21:07:38 +0000221
edgar_igl852d4812009-04-01 23:10:46 +0000222int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
223
aurel32ef7ec1c2009-03-03 06:12:03 +0000224void cpu_load_tlb(CPUSH4State * env);
225
Eduardo Habkost2994fd92015-02-26 17:37:49 -0300226#define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model))
Andreas Färber445e9572012-05-04 18:35:09 +0200227
ths9467d442007-06-03 21:02:38 +0000228#define cpu_exec cpu_sh4_exec
ths9467d442007-06-03 21:02:38 +0000229#define cpu_signal_handler cpu_sh4_signal_handler
aurel320fd3ca32008-09-02 16:18:28 +0000230#define cpu_list sh4_cpu_list
ths9467d442007-06-03 21:02:38 +0000231
j_mayer6ebbf392007-10-14 07:07:08 +0000232/* MMU modes definitions */
233#define MMU_MODE0_SUFFIX _kernel
234#define MMU_MODE1_SUFFIX _user
235#define MMU_USER_IDX 1
Benjamin Herrenschmidt97ed5cc2015-08-17 17:34:10 +1000236static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
j_mayer6ebbf392007-10-14 07:07:08 +0000237{
Aurelien Jarno5ed9a252015-05-25 01:28:56 +0200238 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
j_mayer6ebbf392007-10-14 07:07:08 +0000239}
240
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100241#include "exec/cpu-all.h"
bellardfdf9b3e2006-04-27 21:07:38 +0000242
243/* Memory access type */
244enum {
245 /* Privilege */
246 ACCESS_PRIV = 0x01,
247 /* Direction */
248 ACCESS_WRITE = 0x02,
249 /* Type of instruction */
250 ACCESS_CODE = 0x10,
251 ACCESS_INT = 0x20
252};
253
254/* MMU control register */
255#define MMUCR 0x1F000010
256#define MMUCR_AT (1<<0)
Aurelien Jarnoe0bcb9c2010-02-02 19:39:11 +0100257#define MMUCR_TI (1<<2)
bellardfdf9b3e2006-04-27 21:07:38 +0000258#define MMUCR_SV (1<<8)
aurel32ea2b5422008-05-09 18:45:55 +0000259#define MMUCR_URC_BITS (6)
260#define MMUCR_URC_OFFSET (10)
261#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
262#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
263static inline int cpu_mmucr_urc (uint32_t mmucr)
264{
265 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
266}
267
268/* PTEH : Page Translation Entry High register */
269#define PTEH_ASID_BITS (8)
270#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
271#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
272#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
273#define PTEH_VPN_BITS (22)
274#define PTEH_VPN_OFFSET (10)
275#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
276#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
277static inline int cpu_pteh_vpn (uint32_t pteh)
278{
279 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
280}
281
282/* PTEL : Page Translation Entry Low register */
283#define PTEL_V (1 << 8)
284#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
285#define PTEL_C (1 << 3)
286#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
287#define PTEL_D (1 << 2)
288#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
289#define PTEL_SH (1 << 1)
290#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
291#define PTEL_WT (1 << 0)
292#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
293
294#define PTEL_SZ_HIGH_OFFSET (7)
295#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
296#define PTEL_SZ_LOW_OFFSET (4)
297#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
298static inline int cpu_ptel_sz (uint32_t ptel)
299{
300 int sz;
301 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
302 sz <<= 1;
303 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
304 return sz;
305}
306
307#define PTEL_PPN_BITS (19)
308#define PTEL_PPN_OFFSET (10)
309#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
310#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
311static inline int cpu_ptel_ppn (uint32_t ptel)
312{
313 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
314}
315
316#define PTEL_PR_BITS (2)
317#define PTEL_PR_OFFSET (5)
318#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
319#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
320static inline int cpu_ptel_pr (uint32_t ptel)
321{
322 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
323}
324
325/* PTEA : Page Translation Entry Assistance register */
326#define PTEA_SA_BITS (3)
327#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
328#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
329#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
330#define PTEA_TC (1 << 3)
331#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
bellardfdf9b3e2006-04-27 21:07:38 +0000332
edgar_igl852d4812009-04-01 23:10:46 +0000333#define TB_FLAG_PENDING_MOVCA (1 << 4)
334
Aurelien Jarno34086942015-05-25 01:28:56 +0200335static inline target_ulong cpu_read_sr(CPUSH4State *env)
336{
Aurelien Jarno1d565b22015-05-25 01:28:56 +0200337 return env->sr | (env->sr_m << SR_M) |
338 (env->sr_q << SR_Q) |
339 (env->sr_t << SR_T);
Aurelien Jarno34086942015-05-25 01:28:56 +0200340}
341
342static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
343{
Aurelien Jarno1d565b22015-05-25 01:28:56 +0200344 env->sr_m = (sr >> SR_M) & 1;
345 env->sr_q = (sr >> SR_Q) & 1;
346 env->sr_t = (sr >> SR_T) & 1;
347 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
Aurelien Jarno34086942015-05-25 01:28:56 +0200348}
349
Andreas Färber73e57162012-03-14 01:38:22 +0100350static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
aliguori6b917542008-11-18 19:46:41 +0000351 target_ulong *cs_base, int *flags)
352{
353 *pc = env->pc;
354 *cs_base = 0;
355 *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
356 | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
357 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
Aurelien Jarno5ed9a252015-05-25 01:28:56 +0200358 | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
359 | (env->sr & (1u << SR_FD)) /* Bit 15 */
edgar_igl852d4812009-04-01 23:10:46 +0000360 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
aliguori6b917542008-11-18 19:46:41 +0000361}
362
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100363#include "exec/exec-all.h"
Blue Swirlf081c762011-05-21 07:10:23 +0000364
bellardfdf9b3e2006-04-27 21:07:38 +0000365#endif /* _CPU_SH4_H */