Markus Armbruster | 2a6a407 | 2016-06-29 13:47:03 +0200 | [diff] [blame] | 1 | #ifndef QEMU_ELF_H |
| 2 | #define QEMU_ELF_H |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 3 | |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 4 | /* 32-bit ELF base types. */ |
| 5 | typedef uint32_t Elf32_Addr; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 6 | typedef uint16_t Elf32_Half; |
| 7 | typedef uint32_t Elf32_Off; |
| 8 | typedef int32_t Elf32_Sword; |
| 9 | typedef uint32_t Elf32_Word; |
| 10 | |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 11 | /* 64-bit ELF base types. */ |
| 12 | typedef uint64_t Elf64_Addr; |
| 13 | typedef uint16_t Elf64_Half; |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 14 | typedef int16_t Elf64_SHalf; |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 15 | typedef uint64_t Elf64_Off; |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 16 | typedef int32_t Elf64_Sword; |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 17 | typedef uint32_t Elf64_Word; |
| 18 | typedef uint64_t Elf64_Xword; |
| 19 | typedef int64_t Elf64_Sxword; |
| 20 | |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 21 | /* These constants are for the segment types stored in the image headers */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 22 | #define PT_NULL 0 |
| 23 | #define PT_LOAD 1 |
| 24 | #define PT_DYNAMIC 2 |
| 25 | #define PT_INTERP 3 |
| 26 | #define PT_NOTE 4 |
| 27 | #define PT_SHLIB 5 |
| 28 | #define PT_PHDR 6 |
| 29 | #define PT_LOOS 0x60000000 |
| 30 | #define PT_HIOS 0x6fffffff |
| 31 | #define PT_LOPROC 0x70000000 |
| 32 | #define PT_HIPROC 0x7fffffff |
Stefan Markovic | a325197 | 2018-10-05 16:38:46 +0200 | [diff] [blame] | 33 | |
Richard Henderson | 872f3d0 | 2022-08-10 23:00:52 -0700 | [diff] [blame] | 34 | #define PT_GNU_STACK (PT_LOOS + 0x474e551) |
Richard Henderson | 069175b | 2020-10-21 10:37:40 -0700 | [diff] [blame] | 35 | #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553) |
| 36 | |
Stefan Markovic | a325197 | 2018-10-05 16:38:46 +0200 | [diff] [blame] | 37 | #define PT_MIPS_REGINFO 0x70000000 |
| 38 | #define PT_MIPS_RTPROC 0x70000001 |
| 39 | #define PT_MIPS_OPTIONS 0x70000002 |
| 40 | #define PT_MIPS_ABIFLAGS 0x70000003 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 41 | |
| 42 | /* Flags in the e_flags field of the header */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 43 | /* MIPS architecture level. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 44 | #define EF_MIPS_ARCH 0xf0000000 |
YunQiang Su | 45506bd | 2018-02-20 18:33:07 +0100 | [diff] [blame] | 45 | |
| 46 | /* Legal values for MIPS architecture level. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 47 | #define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ |
| 48 | #define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ |
| 49 | #define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ |
| 50 | #define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ |
| 51 | #define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ |
| 52 | #define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ |
| 53 | #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ |
| 54 | #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32r2 code. */ |
| 55 | #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64r2 code. */ |
| 56 | #define EF_MIPS_ARCH_32R6 0x90000000 /* MIPS32r6 code. */ |
| 57 | #define EF_MIPS_ARCH_64R6 0xa0000000 /* MIPS64r6 code. */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 58 | |
| 59 | /* The ABI of a file. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 60 | #define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ |
| 61 | #define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 62 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 63 | #define EF_MIPS_NOREORDER 0x00000001 |
| 64 | #define EF_MIPS_PIC 0x00000002 |
| 65 | #define EF_MIPS_CPIC 0x00000004 |
| 66 | #define EF_MIPS_ABI2 0x00000020 |
| 67 | #define EF_MIPS_OPTIONS_FIRST 0x00000080 |
| 68 | #define EF_MIPS_32BITMODE 0x00000100 |
| 69 | #define EF_MIPS_ABI 0x0000f000 |
| 70 | #define EF_MIPS_FP64 0x00000200 |
| 71 | #define EF_MIPS_NAN2008 0x00000400 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 72 | |
Aleksandar Markovic | c20eafa | 2018-08-02 16:15:58 +0200 | [diff] [blame] | 73 | /* MIPS machine variant */ |
| 74 | #define EF_MIPS_MACH_NONE 0x00000000 /* A standard MIPS implementation */ |
| 75 | #define EF_MIPS_MACH_3900 0x00810000 /* Toshiba R3900 */ |
| 76 | #define EF_MIPS_MACH_4010 0x00820000 /* LSI R4010 */ |
| 77 | #define EF_MIPS_MACH_4100 0x00830000 /* NEC VR4100 */ |
| 78 | #define EF_MIPS_MACH_4650 0x00850000 /* MIPS R4650 */ |
| 79 | #define EF_MIPS_MACH_4120 0x00870000 /* NEC VR4120 */ |
| 80 | #define EF_MIPS_MACH_4111 0x00880000 /* NEC VR4111/VR4181 */ |
| 81 | #define EF_MIPS_MACH_SB1 0x008a0000 /* Broadcom SB-1 */ |
| 82 | #define EF_MIPS_MACH_OCTEON 0x008b0000 /* Cavium Networks Octeon */ |
| 83 | #define EF_MIPS_MACH_XLR 0x008c0000 /* RMI Xlr */ |
| 84 | #define EF_MIPS_MACH_OCTEON2 0x008d0000 /* Cavium Networks Octeon2 */ |
| 85 | #define EF_MIPS_MACH_OCTEON3 0x008e0000 /* Cavium Networks Octeon3 */ |
| 86 | #define EF_MIPS_MACH_5400 0x00910000 /* NEC VR5400 */ |
Fredrik Noring | f0a997c | 2018-10-18 18:08:46 +0200 | [diff] [blame] | 87 | #define EF_MIPS_MACH_5900 0x00920000 /* Toshiba/Sony R5900 */ |
Aleksandar Markovic | c20eafa | 2018-08-02 16:15:58 +0200 | [diff] [blame] | 88 | #define EF_MIPS_MACH_5500 0x00980000 /* NEC VR5500 */ |
Fredrik Noring | f0a997c | 2018-10-18 18:08:46 +0200 | [diff] [blame] | 89 | #define EF_MIPS_MACH_9000 0x00990000 /* PMC-Sierra RM9000 */ |
Aleksandar Markovic | c20eafa | 2018-08-02 16:15:58 +0200 | [diff] [blame] | 90 | #define EF_MIPS_MACH_LS2E 0x00a00000 /* ST Microelectronics Loongson 2E */ |
| 91 | #define EF_MIPS_MACH_LS2F 0x00a10000 /* ST Microelectronics Loongson 2F */ |
| 92 | #define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson 3A */ |
| 93 | #define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection mask */ |
| 94 | |
Stefan Markovic | 3f8e8ac | 2018-10-26 15:28:07 +0200 | [diff] [blame] | 95 | #define MIPS_ABI_FP_UNKNOWN (-1) /* Unknown FP ABI (internal) */ |
| 96 | |
Stefan Markovic | 967a110 | 2018-10-05 16:58:45 +0200 | [diff] [blame] | 97 | #define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter */ |
| 98 | #define MIPS_ABI_FP_DOUBLE 0x1 /* -mdouble-float */ |
| 99 | #define MIPS_ABI_FP_SINGLE 0x2 /* -msingle-float */ |
| 100 | #define MIPS_ABI_FP_SOFT 0x3 /* -msoft-float */ |
| 101 | #define MIPS_ABI_FP_OLD_64 0x4 /* -mips32r2 -mfp64 */ |
| 102 | #define MIPS_ABI_FP_XX 0x5 /* -mfpxx */ |
| 103 | #define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 */ |
| 104 | #define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spreg */ |
Aleksandar Markovic | c20eafa | 2018-08-02 16:15:58 +0200 | [diff] [blame] | 105 | |
Stefan Markovic | e461558 | 2018-10-05 17:06:35 +0200 | [diff] [blame] | 106 | typedef struct mips_elf_abiflags_v0 { |
| 107 | uint16_t version; /* Version of flags structure */ |
| 108 | uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */ |
| 109 | uint8_t isa_rev; /* The revision of ISA: */ |
| 110 | /* - 0 for MIPS V and below, */ |
| 111 | /* - 1-n otherwise. */ |
| 112 | uint8_t gpr_size; /* The size of general purpose registers */ |
| 113 | uint8_t cpr1_size; /* The size of co-processor 1 registers */ |
| 114 | uint8_t cpr2_size; /* The size of co-processor 2 registers */ |
| 115 | uint8_t fp_abi; /* The floating-point ABI */ |
| 116 | uint32_t isa_ext; /* Mask of processor-specific extensions */ |
| 117 | uint32_t ases; /* Mask of ASEs used */ |
| 118 | uint32_t flags1; /* Mask of general flags */ |
| 119 | uint32_t flags2; |
| 120 | } Mips_elf_abiflags_v0; |
| 121 | |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 122 | /* These constants define the different elf file types */ |
| 123 | #define ET_NONE 0 |
| 124 | #define ET_REL 1 |
| 125 | #define ET_EXEC 2 |
| 126 | #define ET_DYN 3 |
| 127 | #define ET_CORE 4 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 128 | #define ET_LOPROC 0xff00 |
| 129 | #define ET_HIPROC 0xffff |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 130 | |
| 131 | /* These constants define the various ELF target machines */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 132 | #define EM_NONE 0 |
| 133 | #define EM_M32 1 |
| 134 | #define EM_SPARC 2 |
| 135 | #define EM_386 3 |
| 136 | #define EM_68K 4 |
| 137 | #define EM_88K 5 |
| 138 | #define EM_486 6 /* Perhaps disused */ |
| 139 | #define EM_860 7 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 140 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 141 | #define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 142 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 143 | #define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 144 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 145 | #define EM_PARISC 15 /* HPPA */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 146 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 147 | #define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 148 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 149 | #define EM_PPC 20 /* PowerPC */ |
| 150 | #define EM_PPC64 21 /* PowerPC64 */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 151 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 152 | #define EM_ARM 40 /* ARM */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 153 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 154 | #define EM_SH 42 /* SuperH */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 155 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 156 | #define EM_SPARCV9 43 /* SPARC v9 64-bit */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 157 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 158 | #define EM_TRICORE 44 /* Infineon TriCore */ |
Bastian Koppelmann | 48e06fe | 2014-09-01 12:59:46 +0100 | [diff] [blame] | 159 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 160 | #define EM_IA_64 50 /* HP/Intel IA-64 */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 161 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 162 | #define EM_X86_64 62 /* AMD x86-64 */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 163 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 164 | #define EM_S390 22 /* IBM S/390 */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 165 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 166 | #define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 167 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 168 | #define EM_AVR 83 /* AVR 8-bit microcontroller */ |
Philippe Mathieu-Daudé | 7dd8f6f | 2020-01-24 01:51:25 +0100 | [diff] [blame] | 169 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 170 | #define EM_V850 87 /* NEC v850 */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 171 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 172 | #define EM_H8_300H 47 /* Hitachi H8/300H */ |
| 173 | #define EM_H8S 48 /* Hitachi H8S */ |
| 174 | #define EM_LATTICEMICO32 138 /* LatticeMico32 */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 175 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 176 | #define EM_OPENRISC 92 /* OpenCores OpenRISC */ |
Jia Liu | e67db06 | 2012-07-20 15:50:39 +0800 | [diff] [blame] | 177 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 178 | #define EM_HEXAGON 164 /* Qualcomm Hexagon */ |
Markus Armbruster | 4369223 | 2021-05-03 10:40:34 +0200 | [diff] [blame] | 179 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 180 | #define EM_RX 173 /* Renesas RX family */ |
Yoshinori Sato | d06edec | 2020-08-14 22:14:38 +0900 | [diff] [blame] | 181 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 182 | #define EM_RISCV 243 /* RISC-V */ |
Michael Clark | f71a8ea | 2018-03-03 01:31:09 +1300 | [diff] [blame] | 183 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 184 | #define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */ |
Aleksandar Rikalo | 2a94de0 | 2018-08-13 17:34:05 +0200 | [diff] [blame] | 185 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 186 | #define EM_LOONGARCH 258 /* LoongArch */ |
WANG Xuerui | e788cd2 | 2021-12-21 13:40:35 +0800 | [diff] [blame] | 187 | |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 188 | /* |
| 189 | * This is an interim value that we will use until the committee comes |
| 190 | * up with a final number. |
| 191 | */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 192 | #define EM_ALPHA 0x9026 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 193 | |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 194 | /* Bogus old v850 magic number, used by old tools. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 195 | #define EM_CYGNUS_V850 0x9080 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 196 | |
| 197 | /* |
| 198 | * This is the old interim value for S/390 architecture |
| 199 | */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 200 | #define EM_S390_OLD 0xA390 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 201 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 202 | #define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */ |
Marek Vasut | a0a839b | 2017-01-18 23:01:42 +0100 | [diff] [blame] | 203 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 204 | #define EM_MICROBLAZE 189 |
| 205 | #define EM_MICROBLAZE_OLD 0xBAAB |
Edgar E. Iglesias | b779e29 | 2009-05-20 21:31:33 +0200 | [diff] [blame] | 206 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 207 | #define EM_XTENSA 94 /* Tensilica Xtensa */ |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 208 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 209 | #define EM_AARCH64 183 |
Claudio Fontana | 1d25677 | 2013-06-12 16:20:22 +0100 | [diff] [blame] | 210 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 211 | #define EF_AVR_MACH 0x7F /* Mask for AVR e_flags to get core type */ |
Philippe Mathieu-Daudé | 7dd8f6f | 2020-01-24 01:51:25 +0100 | [diff] [blame] | 212 | |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 213 | /* This is the info that is needed to parse the dynamic section of the file */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 214 | #define DT_NULL 0 |
| 215 | #define DT_NEEDED 1 |
| 216 | #define DT_PLTRELSZ 2 |
| 217 | #define DT_PLTGOT 3 |
| 218 | #define DT_HASH 4 |
| 219 | #define DT_STRTAB 5 |
| 220 | #define DT_SYMTAB 6 |
| 221 | #define DT_RELA 7 |
| 222 | #define DT_RELASZ 8 |
| 223 | #define DT_RELAENT 9 |
| 224 | #define DT_STRSZ 10 |
| 225 | #define DT_SYMENT 11 |
| 226 | #define DT_INIT 12 |
| 227 | #define DT_FINI 13 |
| 228 | #define DT_SONAME 14 |
| 229 | #define DT_RPATH 15 |
| 230 | #define DT_SYMBOLIC 16 |
| 231 | #define DT_REL 17 |
| 232 | #define DT_RELSZ 18 |
| 233 | #define DT_RELENT 19 |
| 234 | #define DT_PLTREL 20 |
| 235 | #define DT_DEBUG 21 |
| 236 | #define DT_TEXTREL 22 |
| 237 | #define DT_JMPREL 23 |
| 238 | #define DT_BINDNOW 24 |
| 239 | #define DT_INIT_ARRAY 25 |
| 240 | #define DT_FINI_ARRAY 26 |
| 241 | #define DT_INIT_ARRAYSZ 27 |
| 242 | #define DT_FINI_ARRAYSZ 28 |
| 243 | #define DT_RUNPATH 29 |
| 244 | #define DT_FLAGS 30 |
| 245 | #define DT_LOOS 0x6000000d |
| 246 | #define DT_HIOS 0x6ffff000 |
| 247 | #define DT_LOPROC 0x70000000 |
| 248 | #define DT_HIPROC 0x7fffffff |
Richard Henderson | e167d46 | 2010-07-27 10:25:28 -0700 | [diff] [blame] | 249 | |
| 250 | /* DT_ entries which fall between DT_VALRNGLO and DT_VALRNDHI use |
| 251 | the d_val field of the Elf*_Dyn structure. I.e. they contain scalars. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 252 | #define DT_VALRNGLO 0x6ffffd00 |
| 253 | #define DT_VALRNGHI 0x6ffffdff |
Richard Henderson | e167d46 | 2010-07-27 10:25:28 -0700 | [diff] [blame] | 254 | |
| 255 | /* DT_ entries which fall between DT_ADDRRNGLO and DT_ADDRRNGHI use |
| 256 | the d_ptr field of the Elf*_Dyn structure. I.e. they contain pointers. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 257 | #define DT_ADDRRNGLO 0x6ffffe00 |
| 258 | #define DT_ADDRRNGHI 0x6ffffeff |
Richard Henderson | e167d46 | 2010-07-27 10:25:28 -0700 | [diff] [blame] | 259 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 260 | #define DT_VERSYM 0x6ffffff0 |
| 261 | #define DT_RELACOUNT 0x6ffffff9 |
| 262 | #define DT_RELCOUNT 0x6ffffffa |
| 263 | #define DT_FLAGS_1 0x6ffffffb |
| 264 | #define DT_VERDEF 0x6ffffffc |
| 265 | #define DT_VERDEFNUM 0x6ffffffd |
| 266 | #define DT_VERNEED 0x6ffffffe |
| 267 | #define DT_VERNEEDNUM 0x6fffffff |
Richard Henderson | e167d46 | 2010-07-27 10:25:28 -0700 | [diff] [blame] | 268 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 269 | #define DT_MIPS_RLD_VERSION 0x70000001 |
| 270 | #define DT_MIPS_TIME_STAMP 0x70000002 |
| 271 | #define DT_MIPS_ICHECKSUM 0x70000003 |
| 272 | #define DT_MIPS_IVERSION 0x70000004 |
| 273 | #define DT_MIPS_FLAGS 0x70000005 |
| 274 | #define RHF_NONE 0 |
| 275 | #define RHF_HARDWAY 1 |
| 276 | #define RHF_NOTPOT 2 |
| 277 | #define DT_MIPS_BASE_ADDRESS 0x70000006 |
| 278 | #define DT_MIPS_CONFLICT 0x70000008 |
| 279 | #define DT_MIPS_LIBLIST 0x70000009 |
| 280 | #define DT_MIPS_LOCAL_GOTNO 0x7000000a |
| 281 | #define DT_MIPS_CONFLICTNO 0x7000000b |
| 282 | #define DT_MIPS_LIBLISTNO 0x70000010 |
| 283 | #define DT_MIPS_SYMTABNO 0x70000011 |
| 284 | #define DT_MIPS_UNREFEXTNO 0x70000012 |
| 285 | #define DT_MIPS_GOTSYM 0x70000013 |
| 286 | #define DT_MIPS_HIPAGENO 0x70000014 |
| 287 | #define DT_MIPS_RLD_MAP 0x70000016 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 288 | |
| 289 | /* This info is needed when parsing the symbol table */ |
| 290 | #define STB_LOCAL 0 |
| 291 | #define STB_GLOBAL 1 |
| 292 | #define STB_WEAK 2 |
| 293 | |
| 294 | #define STT_NOTYPE 0 |
| 295 | #define STT_OBJECT 1 |
| 296 | #define STT_FUNC 2 |
| 297 | #define STT_SECTION 3 |
| 298 | #define STT_FILE 4 |
| 299 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 300 | #define ELF_ST_BIND(x) ((x) >> 4) |
| 301 | #define ELF_ST_TYPE(x) (((unsigned int) x) & 0xf) |
Richard Henderson | 813da62 | 2012-03-19 12:25:11 -0700 | [diff] [blame] | 302 | #define ELF_ST_INFO(bind, type) (((bind) << 4) | ((type) & 0xf)) |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 303 | #define ELF32_ST_BIND(x) ELF_ST_BIND(x) |
| 304 | #define ELF32_ST_TYPE(x) ELF_ST_TYPE(x) |
| 305 | #define ELF64_ST_BIND(x) ELF_ST_BIND(x) |
| 306 | #define ELF64_ST_TYPE(x) ELF_ST_TYPE(x) |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 307 | |
| 308 | /* Symbolic values for the entries in the auxiliary table |
| 309 | put on the initial stack */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 310 | #define AT_NULL 0 /* end of vector */ |
| 311 | #define AT_IGNORE 1 /* entry should be ignored */ |
| 312 | #define AT_EXECFD 2 /* file descriptor of program */ |
| 313 | #define AT_PHDR 3 /* program headers for program */ |
| 314 | #define AT_PHENT 4 /* size of program header entry */ |
| 315 | #define AT_PHNUM 5 /* number of program headers */ |
| 316 | #define AT_PAGESZ 6 /* system page size */ |
| 317 | #define AT_BASE 7 /* base address of interpreter */ |
| 318 | #define AT_FLAGS 8 /* flags */ |
| 319 | #define AT_ENTRY 9 /* entry point of program */ |
| 320 | #define AT_NOTELF 10 /* program is not ELF */ |
| 321 | #define AT_UID 11 /* real uid */ |
| 322 | #define AT_EUID 12 /* effective uid */ |
| 323 | #define AT_GID 13 /* real gid */ |
| 324 | #define AT_EGID 14 /* effective gid */ |
| 325 | #define AT_PLATFORM 15 /* string identifying CPU for optimizations */ |
| 326 | #define AT_HWCAP 16 /* arch dependent hints at CPU capabilities */ |
| 327 | #define AT_CLKTCK 17 /* frequency at which times() increments */ |
| 328 | #define AT_FPUCW 18 /* info about fpu initialization by kernel */ |
| 329 | #define AT_DCACHEBSIZE 19 /* data cache block size */ |
| 330 | #define AT_ICACHEBSIZE 20 /* instruction cache block size */ |
| 331 | #define AT_UCACHEBSIZE 21 /* unified cache block size */ |
| 332 | #define AT_IGNOREPPC 22 /* ppc only; entry should be ignored */ |
| 333 | #define AT_SECURE 23 /* boolean, was exec suid-like? */ |
| 334 | #define AT_BASE_PLATFORM 24 /* string identifying real platforms */ |
| 335 | #define AT_RANDOM 25 /* address of 16 random bytes */ |
| 336 | #define AT_HWCAP2 26 /* extension of AT_HWCAP */ |
| 337 | #define AT_EXECFN 31 /* filename of the executable */ |
| 338 | #define AT_SYSINFO 32 /* address of kernel entry point */ |
| 339 | #define AT_SYSINFO_EHDR 33 /* address of kernel vdso */ |
| 340 | #define AT_L1I_CACHESHAPE 34 /* shapes of the caches: */ |
| 341 | #define AT_L1D_CACHESHAPE 35 /* bits 0-3: cache associativity. */ |
| 342 | #define AT_L2_CACHESHAPE 36 /* bits 4-7: log2 of line size. */ |
| 343 | #define AT_L3_CACHESHAPE 37 /* val&~255: cache size. */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 344 | |
| 345 | typedef struct dynamic{ |
| 346 | Elf32_Sword d_tag; |
| 347 | union{ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 348 | Elf32_Sword d_val; |
| 349 | Elf32_Addr d_ptr; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 350 | } d_un; |
| 351 | } Elf32_Dyn; |
| 352 | |
| 353 | typedef struct { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 354 | Elf64_Sxword d_tag; /* entry tag value */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 355 | union { |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 356 | Elf64_Xword d_val; |
| 357 | Elf64_Addr d_ptr; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 358 | } d_un; |
| 359 | } Elf64_Dyn; |
| 360 | |
| 361 | /* The following are used with relocations */ |
| 362 | #define ELF32_R_SYM(x) ((x) >> 8) |
| 363 | #define ELF32_R_TYPE(x) ((x) & 0xff) |
| 364 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 365 | #define ELF64_R_SYM(i) ((i) >> 32) |
| 366 | #define ELF64_R_TYPE(i) ((i) & 0xffffffff) |
bellard | 74ccb34 | 2006-07-18 21:23:34 +0000 | [diff] [blame] | 367 | #define ELF64_R_TYPE_DATA(i) (((ELF64_R_TYPE(i) >> 8) ^ 0x00800000) - 0x00800000) |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 368 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 369 | #define R_386_NONE 0 |
| 370 | #define R_386_32 1 |
| 371 | #define R_386_PC32 2 |
| 372 | #define R_386_GOT32 3 |
| 373 | #define R_386_PLT32 4 |
| 374 | #define R_386_COPY 5 |
| 375 | #define R_386_GLOB_DAT 6 |
| 376 | #define R_386_JMP_SLOT 7 |
| 377 | #define R_386_RELATIVE 8 |
| 378 | #define R_386_GOTOFF 9 |
| 379 | #define R_386_GOTPC 10 |
| 380 | #define R_386_NUM 11 |
Richard Henderson | f75b56c | 2010-02-06 11:47:58 -0800 | [diff] [blame] | 381 | /* Not a dynamic reloc, so not included in R_386_NUM. Used in TCG. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 382 | #define R_386_PC8 23 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 383 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 384 | #define R_MIPS_NONE 0 |
| 385 | #define R_MIPS_16 1 |
| 386 | #define R_MIPS_32 2 |
| 387 | #define R_MIPS_REL32 3 |
| 388 | #define R_MIPS_26 4 |
| 389 | #define R_MIPS_HI16 5 |
| 390 | #define R_MIPS_LO16 6 |
| 391 | #define R_MIPS_GPREL16 7 |
| 392 | #define R_MIPS_LITERAL 8 |
| 393 | #define R_MIPS_GOT16 9 |
| 394 | #define R_MIPS_PC16 10 |
| 395 | #define R_MIPS_CALL16 11 |
| 396 | #define R_MIPS_GPREL32 12 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 397 | /* The remaining relocs are defined on Irix, although they are not |
| 398 | in the MIPS ELF ABI. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 399 | #define R_MIPS_UNUSED1 13 |
| 400 | #define R_MIPS_UNUSED2 14 |
| 401 | #define R_MIPS_UNUSED3 15 |
| 402 | #define R_MIPS_SHIFT5 16 |
| 403 | #define R_MIPS_SHIFT6 17 |
| 404 | #define R_MIPS_64 18 |
| 405 | #define R_MIPS_GOT_DISP 19 |
| 406 | #define R_MIPS_GOT_PAGE 20 |
| 407 | #define R_MIPS_GOT_OFST 21 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 408 | /* |
| 409 | * The following two relocation types are specified in the MIPS ABI |
| 410 | * conformance guide version 1.2 but not yet in the psABI. |
| 411 | */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 412 | #define R_MIPS_GOTHI16 22 |
| 413 | #define R_MIPS_GOTLO16 23 |
| 414 | #define R_MIPS_SUB 24 |
| 415 | #define R_MIPS_INSERT_A 25 |
| 416 | #define R_MIPS_INSERT_B 26 |
| 417 | #define R_MIPS_DELETE 27 |
| 418 | #define R_MIPS_HIGHER 28 |
| 419 | #define R_MIPS_HIGHEST 29 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 420 | /* |
| 421 | * The following two relocation types are specified in the MIPS ABI |
| 422 | * conformance guide version 1.2 but not yet in the psABI. |
| 423 | */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 424 | #define R_MIPS_CALLHI16 30 |
| 425 | #define R_MIPS_CALLLO16 31 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 426 | /* |
| 427 | * This range is reserved for vendor specific relocations. |
| 428 | */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 429 | #define R_MIPS_LOVENDOR 100 |
| 430 | #define R_MIPS_HIVENDOR 127 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 431 | |
| 432 | |
Richard Henderson | cb1977d | 2012-03-24 10:47:39 -0700 | [diff] [blame] | 433 | /* SUN SPARC specific definitions. */ |
| 434 | |
| 435 | /* Values for Elf64_Ehdr.e_flags. */ |
| 436 | |
| 437 | #define EF_SPARCV9_MM 3 |
| 438 | #define EF_SPARCV9_TSO 0 |
| 439 | #define EF_SPARCV9_PSO 1 |
| 440 | #define EF_SPARCV9_RMO 2 |
| 441 | #define EF_SPARC_LEDATA 0x800000 /* little endian data */ |
| 442 | #define EF_SPARC_EXT_MASK 0xFFFF00 |
| 443 | #define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ |
| 444 | #define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ |
| 445 | #define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ |
| 446 | #define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ |
| 447 | |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 448 | /* |
| 449 | * Sparc ELF relocation types |
| 450 | */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 451 | #define R_SPARC_NONE 0 |
| 452 | #define R_SPARC_8 1 |
| 453 | #define R_SPARC_16 2 |
| 454 | #define R_SPARC_32 3 |
| 455 | #define R_SPARC_DISP8 4 |
| 456 | #define R_SPARC_DISP16 5 |
| 457 | #define R_SPARC_DISP32 6 |
| 458 | #define R_SPARC_WDISP30 7 |
| 459 | #define R_SPARC_WDISP22 8 |
| 460 | #define R_SPARC_HI22 9 |
| 461 | #define R_SPARC_22 10 |
| 462 | #define R_SPARC_13 11 |
| 463 | #define R_SPARC_LO10 12 |
| 464 | #define R_SPARC_GOT10 13 |
| 465 | #define R_SPARC_GOT13 14 |
| 466 | #define R_SPARC_GOT22 15 |
| 467 | #define R_SPARC_PC10 16 |
| 468 | #define R_SPARC_PC22 17 |
| 469 | #define R_SPARC_WPLT30 18 |
| 470 | #define R_SPARC_COPY 19 |
| 471 | #define R_SPARC_GLOB_DAT 20 |
| 472 | #define R_SPARC_JMP_SLOT 21 |
| 473 | #define R_SPARC_RELATIVE 22 |
| 474 | #define R_SPARC_UA32 23 |
| 475 | #define R_SPARC_PLT32 24 |
| 476 | #define R_SPARC_HIPLT22 25 |
| 477 | #define R_SPARC_LOPLT10 26 |
| 478 | #define R_SPARC_PCPLT32 27 |
| 479 | #define R_SPARC_PCPLT22 28 |
| 480 | #define R_SPARC_PCPLT10 29 |
| 481 | #define R_SPARC_10 30 |
| 482 | #define R_SPARC_11 31 |
| 483 | #define R_SPARC_64 32 |
| 484 | #define R_SPARC_OLO10 33 |
| 485 | #define R_SPARC_HH22 34 |
| 486 | #define R_SPARC_HM10 35 |
| 487 | #define R_SPARC_LM22 36 |
| 488 | #define R_SPARC_WDISP16 40 |
| 489 | #define R_SPARC_WDISP19 41 |
| 490 | #define R_SPARC_7 43 |
| 491 | #define R_SPARC_5 44 |
| 492 | #define R_SPARC_6 45 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 493 | |
Richard Henderson | 41d9ea8 | 2013-06-07 07:26:20 -0700 | [diff] [blame] | 494 | /* Bits present in AT_HWCAP for ARM. */ |
| 495 | |
| 496 | #define HWCAP_ARM_SWP (1 << 0) |
| 497 | #define HWCAP_ARM_HALF (1 << 1) |
| 498 | #define HWCAP_ARM_THUMB (1 << 2) |
| 499 | #define HWCAP_ARM_26BIT (1 << 3) |
| 500 | #define HWCAP_ARM_FAST_MULT (1 << 4) |
| 501 | #define HWCAP_ARM_FPA (1 << 5) |
| 502 | #define HWCAP_ARM_VFP (1 << 6) |
| 503 | #define HWCAP_ARM_EDSP (1 << 7) |
| 504 | #define HWCAP_ARM_JAVA (1 << 8) |
| 505 | #define HWCAP_ARM_IWMMXT (1 << 9) |
| 506 | #define HWCAP_ARM_CRUNCH (1 << 10) |
| 507 | #define HWCAP_ARM_THUMBEE (1 << 11) |
| 508 | #define HWCAP_ARM_NEON (1 << 12) |
| 509 | #define HWCAP_ARM_VFPv3 (1 << 13) |
| 510 | #define HWCAP_ARM_VFPv3D16 (1 << 14) /* also set for VFPv4-D16 */ |
| 511 | #define HWCAP_ARM_TLS (1 << 15) |
| 512 | #define HWCAP_ARM_VFPv4 (1 << 16) |
| 513 | #define HWCAP_ARM_IDIVA (1 << 17) |
| 514 | #define HWCAP_ARM_IDIVT (1 << 18) |
| 515 | #define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) |
| 516 | #define HWCAP_VFPD32 (1 << 19) /* set if VFP has 32 regs */ |
| 517 | #define HWCAP_LPAE (1 << 20) |
| 518 | |
Richard Henderson | cd629de | 2013-06-04 11:37:17 -0700 | [diff] [blame] | 519 | /* Bits present in AT_HWCAP for PowerPC. */ |
| 520 | |
| 521 | #define PPC_FEATURE_32 0x80000000 |
| 522 | #define PPC_FEATURE_64 0x40000000 |
| 523 | #define PPC_FEATURE_601_INSTR 0x20000000 |
| 524 | #define PPC_FEATURE_HAS_ALTIVEC 0x10000000 |
| 525 | #define PPC_FEATURE_HAS_FPU 0x08000000 |
| 526 | #define PPC_FEATURE_HAS_MMU 0x04000000 |
| 527 | #define PPC_FEATURE_HAS_4xxMAC 0x02000000 |
| 528 | #define PPC_FEATURE_UNIFIED_CACHE 0x01000000 |
| 529 | #define PPC_FEATURE_HAS_SPE 0x00800000 |
| 530 | #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 |
| 531 | #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 |
| 532 | #define PPC_FEATURE_NO_TB 0x00100000 |
| 533 | #define PPC_FEATURE_POWER4 0x00080000 |
| 534 | #define PPC_FEATURE_POWER5 0x00040000 |
| 535 | #define PPC_FEATURE_POWER5_PLUS 0x00020000 |
| 536 | #define PPC_FEATURE_CELL 0x00010000 |
| 537 | #define PPC_FEATURE_BOOKE 0x00008000 |
| 538 | #define PPC_FEATURE_SMT 0x00004000 |
| 539 | #define PPC_FEATURE_ICACHE_SNOOP 0x00002000 |
| 540 | #define PPC_FEATURE_ARCH_2_05 0x00001000 |
| 541 | #define PPC_FEATURE_PA6T 0x00000800 |
| 542 | #define PPC_FEATURE_HAS_DFP 0x00000400 |
| 543 | #define PPC_FEATURE_POWER6_EXT 0x00000200 |
| 544 | #define PPC_FEATURE_ARCH_2_06 0x00000100 |
| 545 | #define PPC_FEATURE_HAS_VSX 0x00000080 |
| 546 | |
| 547 | #define PPC_FEATURE_PSERIES_PERFMON_COMPAT \ |
| 548 | 0x00000040 |
| 549 | |
| 550 | #define PPC_FEATURE_TRUE_LE 0x00000002 |
| 551 | #define PPC_FEATURE_PPC_LE 0x00000001 |
| 552 | |
Anton Blanchard | 42bff47 | 2016-06-07 22:28:42 +1000 | [diff] [blame] | 553 | /* Bits present in AT_HWCAP2 for PowerPC. */ |
| 554 | |
| 555 | #define PPC_FEATURE2_ARCH_2_07 0x80000000 |
| 556 | #define PPC_FEATURE2_HAS_HTM 0x40000000 |
| 557 | #define PPC_FEATURE2_HAS_DSCR 0x20000000 |
| 558 | #define PPC_FEATURE2_HAS_EBB 0x10000000 |
| 559 | #define PPC_FEATURE2_HAS_ISEL 0x08000000 |
| 560 | #define PPC_FEATURE2_HAS_TAR 0x04000000 |
| 561 | #define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000 |
| 562 | #define PPC_FEATURE2_HTM_NOSC 0x01000000 |
| 563 | #define PPC_FEATURE2_ARCH_3_00 0x00800000 |
| 564 | #define PPC_FEATURE2_HAS_IEEE128 0x00400000 |
Lijun Pan | de55d3b | 2020-07-23 23:58:40 -0500 | [diff] [blame] | 565 | #define PPC_FEATURE2_ARCH_3_10 0x00040000 |
Anton Blanchard | 42bff47 | 2016-06-07 22:28:42 +1000 | [diff] [blame] | 566 | |
Richard Henderson | 90379ca | 2014-08-06 11:48:48 -0700 | [diff] [blame] | 567 | /* Bits present in AT_HWCAP for Sparc. */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 568 | |
Richard Henderson | 90379ca | 2014-08-06 11:48:48 -0700 | [diff] [blame] | 569 | #define HWCAP_SPARC_FLUSH 0x00000001 |
| 570 | #define HWCAP_SPARC_STBAR 0x00000002 |
| 571 | #define HWCAP_SPARC_SWAP 0x00000004 |
| 572 | #define HWCAP_SPARC_MULDIV 0x00000008 |
| 573 | #define HWCAP_SPARC_V9 0x00000010 |
| 574 | #define HWCAP_SPARC_ULTRA3 0x00000020 |
| 575 | #define HWCAP_SPARC_BLKINIT 0x00000040 |
| 576 | #define HWCAP_SPARC_N2 0x00000080 |
| 577 | #define HWCAP_SPARC_MUL32 0x00000100 |
| 578 | #define HWCAP_SPARC_DIV32 0x00000200 |
| 579 | #define HWCAP_SPARC_FSMULD 0x00000400 |
| 580 | #define HWCAP_SPARC_V8PLUS 0x00000800 |
| 581 | #define HWCAP_SPARC_POPC 0x00001000 |
| 582 | #define HWCAP_SPARC_VIS 0x00002000 |
| 583 | #define HWCAP_SPARC_VIS2 0x00004000 |
| 584 | #define HWCAP_SPARC_ASI_BLK_INIT 0x00008000 |
| 585 | #define HWCAP_SPARC_FMAF 0x00010000 |
| 586 | #define HWCAP_SPARC_VIS3 0x00020000 |
| 587 | #define HWCAP_SPARC_HPC 0x00040000 |
| 588 | #define HWCAP_SPARC_RANDOM 0x00080000 |
| 589 | #define HWCAP_SPARC_TRANS 0x00100000 |
| 590 | #define HWCAP_SPARC_FJFMAU 0x00200000 |
| 591 | #define HWCAP_SPARC_IMA 0x00400000 |
| 592 | #define HWCAP_SPARC_ASI_CACHE_SPARING 0x00800000 |
| 593 | #define HWCAP_SPARC_PAUSE 0x01000000 |
| 594 | #define HWCAP_SPARC_CBCOND 0x02000000 |
| 595 | #define HWCAP_SPARC_CRYPTO 0x04000000 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 596 | |
Richard Henderson | c9baa30 | 2013-06-07 07:43:33 -0700 | [diff] [blame] | 597 | /* Bits present in AT_HWCAP for s390. */ |
| 598 | |
Ilya Leoshkevich | 7f114a5 | 2023-06-27 17:13:33 +0200 | [diff] [blame] | 599 | #define HWCAP_S390_NR_ESAN3 0 |
| 600 | #define HWCAP_S390_NR_ZARCH 1 |
| 601 | #define HWCAP_S390_NR_STFLE 2 |
| 602 | #define HWCAP_S390_NR_MSA 3 |
| 603 | #define HWCAP_S390_NR_LDISP 4 |
| 604 | #define HWCAP_S390_NR_EIMM 5 |
| 605 | #define HWCAP_S390_NR_DFP 6 |
| 606 | #define HWCAP_S390_NR_HPAGE 7 |
| 607 | #define HWCAP_S390_NR_ETF3EH 8 |
| 608 | #define HWCAP_S390_NR_HIGH_GPRS 9 |
| 609 | #define HWCAP_S390_NR_TE 10 |
| 610 | #define HWCAP_S390_NR_VXRS 11 |
| 611 | #define HWCAP_S390_NR_VXRS_BCD 12 |
| 612 | #define HWCAP_S390_NR_VXRS_EXT 13 |
| 613 | #define HWCAP_S390_NR_GS 14 |
| 614 | #define HWCAP_S390_NR_VXRS_EXT2 15 |
| 615 | #define HWCAP_S390_NR_VXRS_PDE 16 |
| 616 | #define HWCAP_S390_NR_SORT 17 |
| 617 | #define HWCAP_S390_NR_DFLT 18 |
| 618 | #define HWCAP_S390_NR_VXRS_PDE2 19 |
| 619 | #define HWCAP_S390_NR_NNPA 20 |
| 620 | #define HWCAP_S390_NR_PCI_MIO 21 |
| 621 | #define HWCAP_S390_NR_SIE 22 |
| 622 | |
| 623 | #define HWCAP_S390_ESAN3 (1 << HWCAP_S390_NR_ESAN3) |
| 624 | #define HWCAP_S390_ZARCH (1 << HWCAP_S390_NR_ZARCH) |
| 625 | #define HWCAP_S390_STFLE (1 << HWCAP_S390_NR_STFLE) |
| 626 | #define HWCAP_S390_MSA (1 << HWCAP_S390_NR_MSA) |
| 627 | #define HWCAP_S390_LDISP (1 << HWCAP_S390_NR_LDISP) |
| 628 | #define HWCAP_S390_EIMM (1 << HWCAP_S390_NR_EIMM) |
| 629 | #define HWCAP_S390_DFP (1 << HWCAP_S390_NR_DFP) |
| 630 | #define HWCAP_S390_HPAGE (1 << HWCAP_S390_NR_HPAGE) |
| 631 | #define HWCAP_S390_ETF3EH (1 << HWCAP_S390_NR_ETF3EH) |
| 632 | #define HWCAP_S390_HIGH_GPRS (1 << HWCAP_S390_NR_HIGH_GPRS) |
| 633 | #define HWCAP_S390_TE (1 << HWCAP_S390_NR_TE) |
| 634 | #define HWCAP_S390_VXRS (1 << HWCAP_S390_NR_VXRS) |
| 635 | #define HWCAP_S390_VXRS_BCD (1 << HWCAP_S390_NR_VXRS_BCD) |
| 636 | #define HWCAP_S390_VXRS_EXT (1 << HWCAP_S390_NR_VXRS_EXT) |
| 637 | #define HWCAP_S390_GS (1 << HWCAP_S390_NR_GS) |
| 638 | #define HWCAP_S390_VXRS_EXT2 (1 << HWCAP_S390_NR_VXRS_EXT2) |
| 639 | #define HWCAP_S390_VXRS_PDE (1 << HWCAP_S390_NR_VXRS_PDE) |
| 640 | #define HWCAP_S390_SORT (1 << HWCAP_S390_NR_SORT) |
| 641 | #define HWCAP_S390_DFLT (1 << HWCAP_S390_NR_DFLT) |
| 642 | #define HWCAP_S390_VXRS_PDE2 (1 << HWCAP_S390_NR_VXRS_PDE2) |
| 643 | #define HWCAP_S390_NNPA (1 << HWCAP_S390_NR_NNPA) |
| 644 | #define HWCAP_S390_PCI_MIO (1 << HWCAP_S390_NR_PCI_MIO) |
| 645 | #define HWCAP_S390_SIE (1 << HWCAP_S390_NR_SIE) |
Richard Henderson | c9baa30 | 2013-06-07 07:43:33 -0700 | [diff] [blame] | 646 | |
Laurent Vivier | 33dff5f | 2018-02-20 18:33:06 +0100 | [diff] [blame] | 647 | /* M68K specific definitions. */ |
| 648 | /* We use the top 24 bits to encode information about the |
| 649 | architecture variant. */ |
| 650 | #define EF_M68K_CPU32 0x00810000 |
| 651 | #define EF_M68K_M68000 0x01000000 |
| 652 | #define EF_M68K_CFV4E 0x00008000 |
| 653 | #define EF_M68K_FIDO 0x02000000 |
| 654 | #define EF_M68K_ARCH_MASK \ |
| 655 | (EF_M68K_M68000 | EF_M68K_CPU32 | EF_M68K_CFV4E | EF_M68K_FIDO) |
| 656 | |
| 657 | /* We use the bottom 8 bits to encode information about the |
| 658 | coldfire variant. If we use any of these bits, the top 24 bits are |
| 659 | either 0 or EF_M68K_CFV4E. */ |
| 660 | #define EF_M68K_CF_ISA_MASK 0x0F /* Which ISA */ |
| 661 | #define EF_M68K_CF_ISA_A_NODIV 0x01 /* ISA A except for div */ |
| 662 | #define EF_M68K_CF_ISA_A 0x02 |
| 663 | #define EF_M68K_CF_ISA_A_PLUS 0x03 |
| 664 | #define EF_M68K_CF_ISA_B_NOUSP 0x04 /* ISA_B except for USP */ |
| 665 | #define EF_M68K_CF_ISA_B 0x05 |
| 666 | #define EF_M68K_CF_ISA_C 0x06 |
| 667 | #define EF_M68K_CF_ISA_C_NODIV 0x07 /* ISA C except for div */ |
| 668 | #define EF_M68K_CF_MAC_MASK 0x30 |
| 669 | #define EF_M68K_CF_MAC 0x10 /* MAC */ |
| 670 | #define EF_M68K_CF_EMAC 0x20 /* EMAC */ |
| 671 | #define EF_M68K_CF_EMAC_B 0x30 /* EMAC_B */ |
| 672 | #define EF_M68K_CF_FLOAT 0x40 /* Has float insns */ |
| 673 | #define EF_M68K_CF_MASK 0xFF |
| 674 | |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 675 | /* |
| 676 | * 68k ELF relocation types |
| 677 | */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 678 | #define R_68K_NONE 0 |
| 679 | #define R_68K_32 1 |
| 680 | #define R_68K_16 2 |
| 681 | #define R_68K_8 3 |
| 682 | #define R_68K_PC32 4 |
| 683 | #define R_68K_PC16 5 |
| 684 | #define R_68K_PC8 6 |
| 685 | #define R_68K_GOT32 7 |
| 686 | #define R_68K_GOT16 8 |
| 687 | #define R_68K_GOT8 9 |
| 688 | #define R_68K_GOT32O 10 |
| 689 | #define R_68K_GOT16O 11 |
| 690 | #define R_68K_GOT8O 12 |
| 691 | #define R_68K_PLT32 13 |
| 692 | #define R_68K_PLT16 14 |
| 693 | #define R_68K_PLT8 15 |
| 694 | #define R_68K_PLT32O 16 |
| 695 | #define R_68K_PLT16O 17 |
| 696 | #define R_68K_PLT8O 18 |
| 697 | #define R_68K_COPY 19 |
| 698 | #define R_68K_GLOB_DAT 20 |
| 699 | #define R_68K_JMP_SLOT 21 |
| 700 | #define R_68K_RELATIVE 22 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 701 | |
| 702 | /* |
| 703 | * Alpha ELF relocation types |
| 704 | */ |
| 705 | #define R_ALPHA_NONE 0 /* No reloc */ |
| 706 | #define R_ALPHA_REFLONG 1 /* Direct 32 bit */ |
| 707 | #define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ |
| 708 | #define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ |
| 709 | #define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ |
| 710 | #define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ |
| 711 | #define R_ALPHA_GPDISP 6 /* Add displacement to GP */ |
| 712 | #define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ |
| 713 | #define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ |
| 714 | #define R_ALPHA_SREL16 9 /* PC relative 16 bit */ |
| 715 | #define R_ALPHA_SREL32 10 /* PC relative 32 bit */ |
| 716 | #define R_ALPHA_SREL64 11 /* PC relative 64 bit */ |
| 717 | #define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ |
| 718 | #define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ |
| 719 | #define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ |
| 720 | #define R_ALPHA_COPY 24 /* Copy symbol at runtime */ |
| 721 | #define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ |
| 722 | #define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ |
| 723 | #define R_ALPHA_RELATIVE 27 /* Adjust by program base */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 724 | #define R_ALPHA_BRSGP 28 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 725 | #define R_ALPHA_TLSGD 29 |
| 726 | #define R_ALPHA_TLS_LDM 30 |
| 727 | #define R_ALPHA_DTPMOD64 31 |
| 728 | #define R_ALPHA_GOTDTPREL 32 |
| 729 | #define R_ALPHA_DTPREL64 33 |
| 730 | #define R_ALPHA_DTPRELHI 34 |
| 731 | #define R_ALPHA_DTPRELLO 35 |
| 732 | #define R_ALPHA_DTPREL16 36 |
| 733 | #define R_ALPHA_GOTTPREL 37 |
| 734 | #define R_ALPHA_TPREL64 38 |
| 735 | #define R_ALPHA_TPRELHI 39 |
| 736 | #define R_ALPHA_TPRELLO 40 |
| 737 | #define R_ALPHA_TPREL16 41 |
| 738 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 739 | #define SHF_ALPHA_GPREL 0x10000000 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 740 | |
| 741 | |
Doug Kwan | d90b94c | 2014-05-29 09:12:19 -0500 | [diff] [blame] | 742 | /* PowerPC specific definitions. */ |
| 743 | |
| 744 | /* Processor specific flags for the ELF header e_flags field. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 745 | #define EF_PPC64_ABI 0x3 |
Doug Kwan | d90b94c | 2014-05-29 09:12:19 -0500 | [diff] [blame] | 746 | |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 747 | /* PowerPC relocations defined by the ABIs */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 748 | #define R_PPC_NONE 0 |
| 749 | #define R_PPC_ADDR32 1 /* 32bit absolute address */ |
| 750 | #define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ |
| 751 | #define R_PPC_ADDR16 3 /* 16bit absolute address */ |
| 752 | #define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ |
| 753 | #define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ |
| 754 | #define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ |
| 755 | #define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ |
| 756 | #define R_PPC_ADDR14_BRTAKEN 8 |
| 757 | #define R_PPC_ADDR14_BRNTAKEN 9 |
| 758 | #define R_PPC_REL24 10 /* PC relative 26 bit */ |
| 759 | #define R_PPC_REL14 11 /* PC relative 16 bit */ |
| 760 | #define R_PPC_REL14_BRTAKEN 12 |
| 761 | #define R_PPC_REL14_BRNTAKEN 13 |
| 762 | #define R_PPC_GOT16 14 |
| 763 | #define R_PPC_GOT16_LO 15 |
| 764 | #define R_PPC_GOT16_HI 16 |
| 765 | #define R_PPC_GOT16_HA 17 |
| 766 | #define R_PPC_PLTREL24 18 |
| 767 | #define R_PPC_COPY 19 |
| 768 | #define R_PPC_GLOB_DAT 20 |
| 769 | #define R_PPC_JMP_SLOT 21 |
| 770 | #define R_PPC_RELATIVE 22 |
| 771 | #define R_PPC_LOCAL24PC 23 |
| 772 | #define R_PPC_UADDR32 24 |
| 773 | #define R_PPC_UADDR16 25 |
| 774 | #define R_PPC_REL32 26 |
| 775 | #define R_PPC_PLT32 27 |
| 776 | #define R_PPC_PLTREL32 28 |
| 777 | #define R_PPC_PLT16_LO 29 |
| 778 | #define R_PPC_PLT16_HI 30 |
| 779 | #define R_PPC_PLT16_HA 31 |
| 780 | #define R_PPC_SDAREL16 32 |
| 781 | #define R_PPC_SECTOFF 33 |
| 782 | #define R_PPC_SECTOFF_LO 34 |
| 783 | #define R_PPC_SECTOFF_HI 35 |
| 784 | #define R_PPC_SECTOFF_HA 36 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 785 | /* Keep this the last entry. */ |
malc | 3efa9a6 | 2009-07-18 13:10:12 +0400 | [diff] [blame] | 786 | #ifndef R_PPC_NUM |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 787 | #define R_PPC_NUM 37 |
malc | 3efa9a6 | 2009-07-18 13:10:12 +0400 | [diff] [blame] | 788 | #endif |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 789 | |
| 790 | /* ARM specific declarations */ |
| 791 | |
| 792 | /* Processor specific flags for the ELF header e_flags field. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 793 | #define EF_ARM_RELEXEC 0x01 |
| 794 | #define EF_ARM_HASENTRY 0x02 |
| 795 | #define EF_ARM_INTERWORK 0x04 |
| 796 | #define EF_ARM_APCS_26 0x08 |
| 797 | #define EF_ARM_APCS_FLOAT 0x10 |
| 798 | #define EF_ARM_PIC 0x20 |
| 799 | #define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use */ |
| 800 | #define EF_NEW_ABI 0x80 |
| 801 | #define EF_OLD_ABI 0x100 |
| 802 | #define EF_ARM_SOFT_FLOAT 0x200 |
| 803 | #define EF_ARM_VFP_FLOAT 0x400 |
Peter Maydell | ef8b0c0 | 2012-03-30 18:02:49 +0100 | [diff] [blame] | 804 | #define EF_ARM_MAVERICK_FLOAT 0x800 |
| 805 | |
| 806 | /* Other constants defined in the ARM ELF spec. version B-01. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 807 | #define EF_ARM_SYMSARESORTED 0x04 /* NB conflicts with EF_INTERWORK */ |
| 808 | #define EF_ARM_DYNSYMSUSESEGIDX 0x08 /* NB conflicts with EF_APCS26 */ |
| 809 | #define EF_ARM_MAPSYMSFIRST 0x10 /* NB conflicts with EF_APCS_FLOAT */ |
| 810 | #define EF_ARM_EABIMASK 0xFF000000 |
Peter Maydell | ef8b0c0 | 2012-03-30 18:02:49 +0100 | [diff] [blame] | 811 | |
| 812 | /* Constants defined in AAELF. */ |
| 813 | #define EF_ARM_BE8 0x00800000 |
| 814 | #define EF_ARM_LE8 0x00400000 |
| 815 | |
| 816 | #define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) |
| 817 | #define EF_ARM_EABI_UNKNOWN 0x00000000 |
| 818 | #define EF_ARM_EABI_VER1 0x01000000 |
| 819 | #define EF_ARM_EABI_VER2 0x02000000 |
| 820 | #define EF_ARM_EABI_VER3 0x03000000 |
| 821 | #define EF_ARM_EABI_VER4 0x04000000 |
| 822 | #define EF_ARM_EABI_VER5 0x05000000 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 823 | |
| 824 | /* Additional symbol types for Thumb */ |
| 825 | #define STT_ARM_TFUNC 0xd |
| 826 | |
| 827 | /* ARM-specific values for sh_flags */ |
| 828 | #define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ |
| 829 | #define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 830 | in the input to a link step */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 831 | |
| 832 | /* ARM-specific program header flags */ |
| 833 | #define PF_ARM_SB 0x10000000 /* Segment contains the location |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 834 | addressed by the static base */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 835 | |
| 836 | /* ARM relocs. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 837 | #define R_ARM_NONE 0 /* No reloc */ |
| 838 | #define R_ARM_PC24 1 /* PC relative 26 bit branch */ |
| 839 | #define R_ARM_ABS32 2 /* Direct 32 bit */ |
| 840 | #define R_ARM_REL32 3 /* PC relative 32 bit */ |
| 841 | #define R_ARM_PC13 4 |
| 842 | #define R_ARM_ABS16 5 /* Direct 16 bit */ |
| 843 | #define R_ARM_ABS12 6 /* Direct 12 bit */ |
| 844 | #define R_ARM_THM_ABS5 7 |
| 845 | #define R_ARM_ABS8 8 /* Direct 8 bit */ |
| 846 | #define R_ARM_SBREL32 9 |
| 847 | #define R_ARM_THM_PC22 10 |
| 848 | #define R_ARM_THM_PC8 11 |
| 849 | #define R_ARM_AMP_VCALL9 12 |
| 850 | #define R_ARM_SWI24 13 |
| 851 | #define R_ARM_THM_SWI8 14 |
| 852 | #define R_ARM_XPC25 15 |
| 853 | #define R_ARM_THM_XPC22 16 |
| 854 | #define R_ARM_COPY 20 /* Copy symbol at runtime */ |
| 855 | #define R_ARM_GLOB_DAT 21 /* Create GOT entry */ |
| 856 | #define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ |
| 857 | #define R_ARM_RELATIVE 23 /* Adjust by program base */ |
| 858 | #define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ |
| 859 | #define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ |
| 860 | #define R_ARM_GOT32 26 /* 32 bit GOT entry */ |
| 861 | #define R_ARM_PLT32 27 /* 32 bit PLT address */ |
pbrook | 4615218 | 2006-07-30 19:16:29 +0000 | [diff] [blame] | 862 | #define R_ARM_CALL 28 |
| 863 | #define R_ARM_JUMP24 29 |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 864 | #define R_ARM_GNU_VTENTRY 100 |
| 865 | #define R_ARM_GNU_VTINHERIT 101 |
| 866 | #define R_ARM_THM_PC11 102 /* thumb unconditional branch */ |
| 867 | #define R_ARM_THM_PC9 103 /* thumb conditional branch */ |
| 868 | #define R_ARM_RXPC25 249 |
| 869 | #define R_ARM_RSBREL32 250 |
| 870 | #define R_ARM_THM_RPC22 251 |
| 871 | #define R_ARM_RREL32 252 |
| 872 | #define R_ARM_RABS22 253 |
| 873 | #define R_ARM_RPC24 254 |
| 874 | #define R_ARM_RBASE 255 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 875 | /* Keep this the last entry. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 876 | #define R_ARM_NUM 256 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 877 | |
Claudio Fontana | 1d25677 | 2013-06-12 16:20:22 +0100 | [diff] [blame] | 878 | /* ARM Aarch64 relocation types */ |
| 879 | #define R_AARCH64_NONE 256 /* also accepts R_ARM_NONE (0) */ |
| 880 | /* static data relocations */ |
| 881 | #define R_AARCH64_ABS64 257 |
| 882 | #define R_AARCH64_ABS32 258 |
| 883 | #define R_AARCH64_ABS16 259 |
| 884 | #define R_AARCH64_PREL64 260 |
| 885 | #define R_AARCH64_PREL32 261 |
| 886 | #define R_AARCH64_PREL16 262 |
| 887 | /* static aarch64 group relocations */ |
| 888 | /* group relocs to create unsigned data value or address inline */ |
| 889 | #define R_AARCH64_MOVW_UABS_G0 263 |
| 890 | #define R_AARCH64_MOVW_UABS_G0_NC 264 |
| 891 | #define R_AARCH64_MOVW_UABS_G1 265 |
| 892 | #define R_AARCH64_MOVW_UABS_G1_NC 266 |
| 893 | #define R_AARCH64_MOVW_UABS_G2 267 |
| 894 | #define R_AARCH64_MOVW_UABS_G2_NC 268 |
| 895 | #define R_AARCH64_MOVW_UABS_G3 269 |
| 896 | /* group relocs to create signed data or offset value inline */ |
| 897 | #define R_AARCH64_MOVW_SABS_G0 270 |
| 898 | #define R_AARCH64_MOVW_SABS_G1 271 |
| 899 | #define R_AARCH64_MOVW_SABS_G2 272 |
| 900 | /* relocs to generate 19, 21, and 33 bit PC-relative addresses */ |
| 901 | #define R_AARCH64_LD_PREL_LO19 273 |
| 902 | #define R_AARCH64_ADR_PREL_LO21 274 |
| 903 | #define R_AARCH64_ADR_PREL_PG_HI21 275 |
| 904 | #define R_AARCH64_ADR_PREL_PG_HI21_NC 276 |
| 905 | #define R_AARCH64_ADD_ABS_LO12_NC 277 |
| 906 | #define R_AARCH64_LDST8_ABS_LO12_NC 278 |
| 907 | #define R_AARCH64_LDST16_ABS_LO12_NC 284 |
| 908 | #define R_AARCH64_LDST32_ABS_LO12_NC 285 |
| 909 | #define R_AARCH64_LDST64_ABS_LO12_NC 286 |
| 910 | #define R_AARCH64_LDST128_ABS_LO12_NC 299 |
| 911 | /* relocs for control-flow - all offsets as multiple of 4 */ |
| 912 | #define R_AARCH64_TSTBR14 279 |
| 913 | #define R_AARCH64_CONDBR19 280 |
| 914 | #define R_AARCH64_JUMP26 282 |
| 915 | #define R_AARCH64_CALL26 283 |
| 916 | /* group relocs to create pc-relative offset inline */ |
| 917 | #define R_AARCH64_MOVW_PREL_G0 287 |
| 918 | #define R_AARCH64_MOVW_PREL_G0_NC 288 |
| 919 | #define R_AARCH64_MOVW_PREL_G1 289 |
| 920 | #define R_AARCH64_MOVW_PREL_G1_NC 290 |
| 921 | #define R_AARCH64_MOVW_PREL_G2 291 |
| 922 | #define R_AARCH64_MOVW_PREL_G2_NC 292 |
| 923 | #define R_AARCH64_MOVW_PREL_G3 293 |
| 924 | /* group relocs to create a GOT-relative offset inline */ |
| 925 | #define R_AARCH64_MOVW_GOTOFF_G0 300 |
| 926 | #define R_AARCH64_MOVW_GOTOFF_G0_NC 301 |
| 927 | #define R_AARCH64_MOVW_GOTOFF_G1 302 |
| 928 | #define R_AARCH64_MOVW_GOTOFF_G1_NC 303 |
| 929 | #define R_AARCH64_MOVW_GOTOFF_G2 304 |
| 930 | #define R_AARCH64_MOVW_GOTOFF_G2_NC 305 |
| 931 | #define R_AARCH64_MOVW_GOTOFF_G3 306 |
| 932 | /* GOT-relative data relocs */ |
| 933 | #define R_AARCH64_GOTREL64 307 |
| 934 | #define R_AARCH64_GOTREL32 308 |
| 935 | /* GOT-relative instr relocs */ |
| 936 | #define R_AARCH64_GOT_LD_PREL19 309 |
| 937 | #define R_AARCH64_LD64_GOTOFF_LO15 310 |
| 938 | #define R_AARCH64_ADR_GOT_PAGE 311 |
| 939 | #define R_AARCH64_LD64_GOT_LO12_NC 312 |
| 940 | #define R_AARCH64_LD64_GOTPAGE_LO15 313 |
| 941 | /* General Dynamic TLS relocations */ |
| 942 | #define R_AARCH64_TLSGD_ADR_PREL21 512 |
| 943 | #define R_AARCH64_TLSGD_ADR_PAGE21 513 |
| 944 | #define R_AARCH64_TLSGD_ADD_LO12_NC 514 |
| 945 | #define R_AARCH64_TLSGD_MOVW_G1 515 |
| 946 | #define R_AARCH64_TLSGD_MOVW_G0_NC 516 |
| 947 | /* Local Dynamic TLS relocations */ |
| 948 | #define R_AARCH64_TLSLD_ADR_PREL21 517 |
| 949 | #define R_AARCH64_TLSLD_ADR_PAGE21 518 |
| 950 | #define R_AARCH64_TLSLD_ADD_LO12_NC 519 |
| 951 | #define R_AARCH64_TLSLD_MOVW_G1 520 |
| 952 | #define R_AARCH64_TLSLD_MOVW_G0_NC 521 |
| 953 | #define R_AARCH64_TLSLD_LD_PREL19 522 |
| 954 | #define R_AARCH64_TLSLD_MOVW_DTPREL_G2 523 |
| 955 | #define R_AARCH64_TLSLD_MOVW_DTPREL_G1 524 |
| 956 | #define R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 525 |
| 957 | #define R_AARCH64_TLSLD_MOVW_DTPREL_G0 526 |
| 958 | #define R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 527 |
| 959 | #define R_AARCH64_TLSLD_ADD_DTPREL_HI12 528 |
| 960 | #define R_AARCH64_TLSLD_ADD_DTPREL_LO12 529 |
| 961 | #define R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 530 |
| 962 | #define R_AARCH64_TLSLD_LDST8_DTPREL_LO12 531 |
| 963 | #define R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 532 |
| 964 | #define R_AARCH64_TLSLD_LDST16_DTPREL_LO12 533 |
| 965 | #define R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 534 |
| 966 | #define R_AARCH64_TLSLD_LDST32_DTPREL_LO12 535 |
| 967 | #define R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 536 |
| 968 | #define R_AARCH64_TLSLD_LDST64_DTPREL_LO12 537 |
| 969 | #define R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 538 |
| 970 | /* initial exec TLS relocations */ |
| 971 | #define R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 539 |
| 972 | #define R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 540 |
| 973 | #define R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 541 |
| 974 | #define R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 542 |
| 975 | #define R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 543 |
| 976 | /* local exec TLS relocations */ |
| 977 | #define R_AARCH64_TLSLE_MOVW_TPREL_G2 544 |
| 978 | #define R_AARCH64_TLSLE_MOVW_TPREL_G1 545 |
| 979 | #define R_AARCH64_TLSLE_MOVW_TPREL_G1_NC 546 |
| 980 | #define R_AARCH64_TLSLE_MOVW_TPREL_G0 547 |
| 981 | #define R_AARCH64_TLSLE_MOVW_TPREL_G0_NC 548 |
| 982 | #define R_AARCH64_TLSLE_ADD_TPREL_HI12 549 |
| 983 | #define R_AARCH64_TLSLE_ADD_TPREL_LO12 550 |
| 984 | #define R_AARCH64_TLSLE_ADD_TPREL_LO12_NC 551 |
| 985 | #define R_AARCH64_TLSLE_LDST8_TPREL_LO12 552 |
| 986 | #define R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 553 |
| 987 | #define R_AARCH64_TLSLE_LDST16_TPREL_LO12 554 |
| 988 | #define R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 555 |
| 989 | #define R_AARCH64_TLSLE_LDST32_TPREL_LO12 556 |
| 990 | #define R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 557 |
| 991 | #define R_AARCH64_TLSLE_LDST64_TPREL_LO12 558 |
| 992 | #define R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 559 |
| 993 | /* Dynamic Relocations */ |
| 994 | #define R_AARCH64_COPY 1024 |
| 995 | #define R_AARCH64_GLOB_DAT 1025 |
| 996 | #define R_AARCH64_JUMP_SLOT 1026 |
| 997 | #define R_AARCH64_RELATIVE 1027 |
| 998 | #define R_AARCH64_TLS_DTPREL64 1028 |
| 999 | #define R_AARCH64_TLS_DTPMOD64 1029 |
| 1000 | #define R_AARCH64_TLS_TPREL64 1030 |
| 1001 | #define R_AARCH64_TLS_DTPREL32 1031 |
| 1002 | #define R_AARCH64_TLS_DTPMOD32 1032 |
| 1003 | #define R_AARCH64_TLS_TPREL32 1033 |
| 1004 | |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1005 | /* s390 relocations defined by the ABIs */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1006 | #define R_390_NONE 0 /* No reloc. */ |
| 1007 | #define R_390_8 1 /* Direct 8 bit. */ |
| 1008 | #define R_390_12 2 /* Direct 12 bit. */ |
| 1009 | #define R_390_16 3 /* Direct 16 bit. */ |
| 1010 | #define R_390_32 4 /* Direct 32 bit. */ |
| 1011 | #define R_390_PC32 5 /* PC relative 32 bit. */ |
| 1012 | #define R_390_GOT12 6 /* 12 bit GOT offset. */ |
| 1013 | #define R_390_GOT32 7 /* 32 bit GOT offset. */ |
| 1014 | #define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ |
| 1015 | #define R_390_COPY 9 /* Copy symbol at runtime. */ |
| 1016 | #define R_390_GLOB_DAT 10 /* Create GOT entry. */ |
| 1017 | #define R_390_JMP_SLOT 11 /* Create PLT entry. */ |
| 1018 | #define R_390_RELATIVE 12 /* Adjust by program base. */ |
| 1019 | #define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ |
| 1020 | #define R_390_GOTPC 14 /* 32 bit PC rel. offset to GOT. */ |
| 1021 | #define R_390_GOT16 15 /* 16 bit GOT offset. */ |
| 1022 | #define R_390_PC16 16 /* PC relative 16 bit. */ |
| 1023 | #define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ |
| 1024 | #define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ |
| 1025 | #define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ |
| 1026 | #define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ |
| 1027 | #define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ |
| 1028 | #define R_390_64 22 /* Direct 64 bit. */ |
| 1029 | #define R_390_PC64 23 /* PC relative 64 bit. */ |
| 1030 | #define R_390_GOT64 24 /* 64 bit GOT offset. */ |
| 1031 | #define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ |
| 1032 | #define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ |
| 1033 | #define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ |
| 1034 | #define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ |
| 1035 | #define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ |
| 1036 | #define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ |
| 1037 | #define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ |
| 1038 | #define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ |
| 1039 | #define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ |
| 1040 | #define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ |
| 1041 | #define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ |
| 1042 | #define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ |
| 1043 | #define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ |
| 1044 | #define R_390_TLS_GDCALL 38 /* Tag for function call in general |
| 1045 | dynamic TLS code. */ |
| 1046 | #define R_390_TLS_LDCALL 39 /* Tag for function call in local |
| 1047 | dynamic TLS code. */ |
| 1048 | #define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic |
| 1049 | thread local data. */ |
| 1050 | #define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic |
| 1051 | thread local data. */ |
| 1052 | #define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS |
| 1053 | block offset. */ |
| 1054 | #define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS |
| 1055 | block offset. */ |
| 1056 | #define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS |
| 1057 | block offset. */ |
| 1058 | #define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic |
| 1059 | thread local data in LD code. */ |
| 1060 | #define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic |
| 1061 | thread local data in LD code. */ |
| 1062 | #define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for |
| 1063 | negated static TLS block offset. */ |
| 1064 | #define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for |
| 1065 | negated static TLS block offset. */ |
| 1066 | #define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for |
| 1067 | negated static TLS block offset. */ |
| 1068 | #define R_390_TLS_LE32 50 /* 32 bit negated offset relative to |
| 1069 | static TLS block. */ |
| 1070 | #define R_390_TLS_LE64 51 /* 64 bit negated offset relative to |
| 1071 | static TLS block. */ |
| 1072 | #define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS |
| 1073 | block. */ |
| 1074 | #define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS |
| 1075 | block. */ |
| 1076 | #define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ |
| 1077 | #define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ |
| 1078 | #define R_390_TLS_TPOFF 56 /* Negate offset in static TLS |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1079 | block. */ |
Richard Henderson | 28eef8a | 2017-07-31 19:16:02 -0700 | [diff] [blame] | 1080 | #define R_390_20 57 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1081 | /* Keep this the last entry. */ |
Richard Henderson | 28eef8a | 2017-07-31 19:16:02 -0700 | [diff] [blame] | 1082 | #define R_390_NUM 58 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1083 | |
| 1084 | /* x86-64 relocation types */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1085 | #define R_X86_64_NONE 0 /* No reloc */ |
| 1086 | #define R_X86_64_64 1 /* Direct 64 bit */ |
| 1087 | #define R_X86_64_PC32 2 /* PC relative 32 bit signed */ |
| 1088 | #define R_X86_64_GOT32 3 /* 32 bit GOT entry */ |
| 1089 | #define R_X86_64_PLT32 4 /* 32 bit PLT address */ |
| 1090 | #define R_X86_64_COPY 5 /* Copy symbol at runtime */ |
| 1091 | #define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ |
| 1092 | #define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ |
| 1093 | #define R_X86_64_RELATIVE 8 /* Adjust by program base */ |
| 1094 | #define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 1095 | offset to GOT */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1096 | #define R_X86_64_32 10 /* Direct 32 bit zero extended */ |
| 1097 | #define R_X86_64_32S 11 /* Direct 32 bit sign extended */ |
| 1098 | #define R_X86_64_16 12 /* Direct 16 bit zero extended */ |
| 1099 | #define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ |
| 1100 | #define R_X86_64_8 14 /* Direct 8 bit sign extended */ |
| 1101 | #define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1102 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1103 | #define R_X86_64_NUM 16 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1104 | |
| 1105 | /* Legal values for e_flags field of Elf64_Ehdr. */ |
| 1106 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1107 | #define EF_ALPHA_32BIT 1 /* All addresses are below 2GB */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1108 | |
| 1109 | /* HPPA specific definitions. */ |
| 1110 | |
| 1111 | /* Legal values for e_flags field of Elf32_Ehdr. */ |
| 1112 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1113 | #define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ |
| 1114 | #define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ |
| 1115 | #define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ |
| 1116 | #define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ |
| 1117 | #define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 1118 | prediction. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1119 | #define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ |
| 1120 | #define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1121 | |
| 1122 | /* Defined values for `e_flags & EF_PARISC_ARCH' are: */ |
| 1123 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1124 | #define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ |
| 1125 | #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ |
| 1126 | #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1127 | |
Michael Tokarev | d02d06f | 2023-08-23 09:53:15 +0300 | [diff] [blame] | 1128 | /* Additional section indices. */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1129 | |
Michael Tokarev | d02d06f | 2023-08-23 09:53:15 +0300 | [diff] [blame] | 1130 | #define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tentatively declared |
Paolo Bonzini | 7d37435 | 2018-12-13 23:37:37 +0100 | [diff] [blame] | 1131 | symbols in ANSI C. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1132 | #define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1133 | |
| 1134 | /* Legal values for sh_type field of Elf32_Shdr. */ |
| 1135 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1136 | #define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ |
| 1137 | #define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ |
| 1138 | #define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1139 | |
| 1140 | /* Legal values for sh_flags field of Elf32_Shdr. */ |
| 1141 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1142 | #define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ |
| 1143 | #define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ |
| 1144 | #define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1145 | |
| 1146 | /* Legal values for ST_TYPE subfield of st_info (symbol type). */ |
| 1147 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1148 | #define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1149 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1150 | #define STT_HP_OPAQUE (STT_LOOS + 0x1) |
| 1151 | #define STT_HP_STUB (STT_LOOS + 0x2) |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1152 | |
| 1153 | /* HPPA relocs. */ |
| 1154 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1155 | #define R_PARISC_NONE 0 /* No reloc. */ |
| 1156 | #define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ |
| 1157 | #define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ |
| 1158 | #define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ |
| 1159 | #define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ |
| 1160 | #define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ |
| 1161 | #define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ |
| 1162 | #define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ |
| 1163 | #define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ |
| 1164 | #define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ |
| 1165 | #define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ |
| 1166 | #define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ |
| 1167 | #define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ |
| 1168 | #define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ |
| 1169 | #define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ |
| 1170 | #define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ |
| 1171 | #define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ |
| 1172 | #define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ |
| 1173 | #define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ |
| 1174 | #define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ |
| 1175 | #define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ |
| 1176 | #define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ |
| 1177 | #define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ |
| 1178 | #define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ |
| 1179 | #define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ |
| 1180 | #define R_PARISC_FPTR64 64 /* 64 bits function address. */ |
| 1181 | #define R_PARISC_PLABEL32 65 /* 32 bits function address. */ |
| 1182 | #define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ |
| 1183 | #define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ |
| 1184 | #define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ |
| 1185 | #define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ |
| 1186 | #define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ |
| 1187 | #define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ |
| 1188 | #define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ |
| 1189 | #define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ |
| 1190 | #define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ |
| 1191 | #define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ |
| 1192 | #define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ |
| 1193 | #define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ |
| 1194 | #define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ |
| 1195 | #define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ |
| 1196 | #define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ |
| 1197 | #define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ |
| 1198 | #define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ |
| 1199 | #define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ |
| 1200 | #define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ |
| 1201 | #define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ |
| 1202 | #define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ |
| 1203 | #define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ |
| 1204 | #define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ |
| 1205 | #define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ |
| 1206 | #define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ |
| 1207 | #define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ |
| 1208 | #define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ |
| 1209 | #define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ |
| 1210 | #define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ |
| 1211 | #define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ |
| 1212 | #define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ |
| 1213 | #define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ |
| 1214 | #define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ |
| 1215 | #define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ |
| 1216 | #define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ |
| 1217 | #define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ |
| 1218 | #define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ |
| 1219 | #define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ |
| 1220 | #define R_PARISC_LORESERVE 128 |
| 1221 | #define R_PARISC_COPY 128 /* Copy relocation. */ |
| 1222 | #define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ |
| 1223 | #define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ |
| 1224 | #define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ |
| 1225 | #define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ |
| 1226 | #define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ |
| 1227 | #define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ |
| 1228 | #define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ |
| 1229 | #define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ |
| 1230 | #define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ |
| 1231 | #define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ |
| 1232 | #define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ |
| 1233 | #define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ |
| 1234 | #define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ |
| 1235 | #define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ |
| 1236 | #define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ |
| 1237 | #define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ |
| 1238 | #define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ |
| 1239 | #define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ |
| 1240 | #define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ |
| 1241 | #define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ |
| 1242 | #define R_PARISC_HIRESERVE 255 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1243 | |
| 1244 | /* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ |
| 1245 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1246 | #define PT_HP_TLS (PT_LOOS + 0x0) |
| 1247 | #define PT_HP_CORE_NONE (PT_LOOS + 0x1) |
| 1248 | #define PT_HP_CORE_VERSION (PT_LOOS + 0x2) |
| 1249 | #define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) |
| 1250 | #define PT_HP_CORE_COMM (PT_LOOS + 0x4) |
| 1251 | #define PT_HP_CORE_PROC (PT_LOOS + 0x5) |
| 1252 | #define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) |
| 1253 | #define PT_HP_CORE_STACK (PT_LOOS + 0x7) |
| 1254 | #define PT_HP_CORE_SHM (PT_LOOS + 0x8) |
| 1255 | #define PT_HP_CORE_MMF (PT_LOOS + 0x9) |
| 1256 | #define PT_HP_PARALLEL (PT_LOOS + 0x10) |
| 1257 | #define PT_HP_FASTBIND (PT_LOOS + 0x11) |
| 1258 | #define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) |
| 1259 | #define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) |
| 1260 | #define PT_HP_STACK (PT_LOOS + 0x14) |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1261 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1262 | #define PT_PARISC_ARCHEXT 0x70000000 |
| 1263 | #define PT_PARISC_UNWIND 0x70000001 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1264 | |
| 1265 | /* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ |
| 1266 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1267 | #define PF_PARISC_SBP 0x08000000 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1268 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1269 | #define PF_HP_PAGE_SIZE 0x00100000 |
| 1270 | #define PF_HP_FAR_SHARED 0x00200000 |
| 1271 | #define PF_HP_NEAR_SHARED 0x00400000 |
| 1272 | #define PF_HP_CODE 0x01000000 |
| 1273 | #define PF_HP_MODIFY 0x02000000 |
| 1274 | #define PF_HP_LAZYSWAP 0x04000000 |
| 1275 | #define PF_HP_SBP 0x08000000 |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1276 | |
bellard | 0d33019 | 2003-04-29 21:10:09 +0000 | [diff] [blame] | 1277 | /* IA-64 specific declarations. */ |
| 1278 | |
| 1279 | /* Processor specific flags for the Ehdr e_flags field. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1280 | #define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ |
| 1281 | #define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ |
| 1282 | #define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ |
bellard | 0d33019 | 2003-04-29 21:10:09 +0000 | [diff] [blame] | 1283 | |
| 1284 | /* Processor specific values for the Phdr p_type field. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1285 | #define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ |
| 1286 | #define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ |
bellard | 0d33019 | 2003-04-29 21:10:09 +0000 | [diff] [blame] | 1287 | |
| 1288 | /* Processor specific flags for the Phdr p_flags field. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1289 | #define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ |
bellard | 0d33019 | 2003-04-29 21:10:09 +0000 | [diff] [blame] | 1290 | |
| 1291 | /* Processor specific values for the Shdr sh_type field. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1292 | #define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ |
| 1293 | #define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ |
bellard | 0d33019 | 2003-04-29 21:10:09 +0000 | [diff] [blame] | 1294 | |
| 1295 | /* Processor specific flags for the Shdr sh_flags field. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1296 | #define SHF_IA_64_SHORT 0x10000000 /* section near gp */ |
| 1297 | #define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ |
bellard | 0d33019 | 2003-04-29 21:10:09 +0000 | [diff] [blame] | 1298 | |
| 1299 | /* Processor specific values for the Dyn d_tag field. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1300 | #define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) |
| 1301 | #define DT_IA_64_NUM 1 |
bellard | 0d33019 | 2003-04-29 21:10:09 +0000 | [diff] [blame] | 1302 | |
| 1303 | /* IA-64 relocations. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1304 | #define R_IA64_NONE 0x00 /* none */ |
| 1305 | #define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ |
| 1306 | #define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ |
| 1307 | #define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ |
| 1308 | #define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ |
| 1309 | #define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ |
| 1310 | #define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ |
| 1311 | #define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ |
| 1312 | #define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ |
| 1313 | #define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ |
| 1314 | #define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ |
| 1315 | #define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ |
| 1316 | #define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ |
| 1317 | #define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ |
| 1318 | #define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ |
| 1319 | #define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ |
| 1320 | #define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ |
| 1321 | #define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ |
| 1322 | #define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ |
| 1323 | #define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ |
| 1324 | #define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ |
| 1325 | #define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ |
| 1326 | #define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ |
| 1327 | #define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ |
| 1328 | #define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ |
| 1329 | #define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ |
| 1330 | #define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ |
| 1331 | #define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ |
| 1332 | #define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ |
| 1333 | #define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ |
| 1334 | #define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ |
| 1335 | #define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ |
| 1336 | #define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ |
| 1337 | #define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ |
| 1338 | #define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ |
| 1339 | #define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ |
| 1340 | #define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ |
| 1341 | #define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ |
| 1342 | #define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ |
| 1343 | #define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ |
| 1344 | #define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ |
| 1345 | #define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ |
| 1346 | #define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ |
| 1347 | #define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ |
| 1348 | #define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ |
| 1349 | #define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ |
| 1350 | #define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ |
| 1351 | #define R_IA64_REL32MSB 0x6c /* data 4 + REL */ |
| 1352 | #define R_IA64_REL32LSB 0x6d /* data 4 + REL */ |
| 1353 | #define R_IA64_REL64MSB 0x6e /* data 8 + REL */ |
| 1354 | #define R_IA64_REL64LSB 0x6f /* data 8 + REL */ |
| 1355 | #define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ |
| 1356 | #define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ |
| 1357 | #define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ |
| 1358 | #define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ |
| 1359 | #define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ |
| 1360 | #define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ |
| 1361 | #define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ |
| 1362 | #define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ |
| 1363 | #define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ |
| 1364 | #define R_IA64_COPY 0x84 /* copy relocation */ |
| 1365 | #define R_IA64_SUB 0x85 /* Addend and symbol difference */ |
| 1366 | #define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ |
| 1367 | #define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ |
| 1368 | #define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ |
| 1369 | #define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ |
| 1370 | #define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ |
| 1371 | #define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ |
| 1372 | #define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ |
| 1373 | #define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ |
| 1374 | #define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ |
| 1375 | #define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ |
| 1376 | #define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ |
| 1377 | #define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ |
| 1378 | #define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ |
| 1379 | #define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ |
| 1380 | #define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ |
| 1381 | #define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ |
| 1382 | #define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ |
| 1383 | #define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ |
| 1384 | #define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1385 | |
Alistair Francis | 6d06fdd | 2018-12-19 19:16:22 +0000 | [diff] [blame] | 1386 | /* RISC-V relocations. */ |
| 1387 | #define R_RISCV_NONE 0 |
| 1388 | #define R_RISCV_32 1 |
| 1389 | #define R_RISCV_64 2 |
| 1390 | #define R_RISCV_RELATIVE 3 |
| 1391 | #define R_RISCV_COPY 4 |
| 1392 | #define R_RISCV_JUMP_SLOT 5 |
| 1393 | #define R_RISCV_TLS_DTPMOD32 6 |
| 1394 | #define R_RISCV_TLS_DTPMOD64 7 |
| 1395 | #define R_RISCV_TLS_DTPREL32 8 |
| 1396 | #define R_RISCV_TLS_DTPREL64 9 |
| 1397 | #define R_RISCV_TLS_TPREL32 10 |
| 1398 | #define R_RISCV_TLS_TPREL64 11 |
| 1399 | #define R_RISCV_BRANCH 16 |
| 1400 | #define R_RISCV_JAL 17 |
| 1401 | #define R_RISCV_CALL 18 |
| 1402 | #define R_RISCV_CALL_PLT 19 |
| 1403 | #define R_RISCV_GOT_HI20 20 |
| 1404 | #define R_RISCV_TLS_GOT_HI20 21 |
| 1405 | #define R_RISCV_TLS_GD_HI20 22 |
| 1406 | #define R_RISCV_PCREL_HI20 23 |
| 1407 | #define R_RISCV_PCREL_LO12_I 24 |
| 1408 | #define R_RISCV_PCREL_LO12_S 25 |
| 1409 | #define R_RISCV_HI20 26 |
| 1410 | #define R_RISCV_LO12_I 27 |
| 1411 | #define R_RISCV_LO12_S 28 |
| 1412 | #define R_RISCV_TPREL_HI20 29 |
| 1413 | #define R_RISCV_TPREL_LO12_I 30 |
| 1414 | #define R_RISCV_TPREL_LO12_S 31 |
| 1415 | #define R_RISCV_TPREL_ADD 32 |
| 1416 | #define R_RISCV_ADD8 33 |
| 1417 | #define R_RISCV_ADD16 34 |
| 1418 | #define R_RISCV_ADD32 35 |
| 1419 | #define R_RISCV_ADD64 36 |
| 1420 | #define R_RISCV_SUB8 37 |
| 1421 | #define R_RISCV_SUB16 38 |
| 1422 | #define R_RISCV_SUB32 39 |
| 1423 | #define R_RISCV_SUB64 40 |
| 1424 | #define R_RISCV_GNU_VTINHERIT 41 |
| 1425 | #define R_RISCV_GNU_VTENTRY 42 |
| 1426 | #define R_RISCV_ALIGN 43 |
| 1427 | #define R_RISCV_RVC_BRANCH 44 |
| 1428 | #define R_RISCV_RVC_JUMP 45 |
| 1429 | #define R_RISCV_RVC_LUI 46 |
| 1430 | #define R_RISCV_GPREL_I 47 |
| 1431 | #define R_RISCV_GPREL_S 48 |
| 1432 | #define R_RISCV_TPREL_I 49 |
| 1433 | #define R_RISCV_TPREL_S 50 |
| 1434 | #define R_RISCV_RELAX 51 |
| 1435 | #define R_RISCV_SUB6 52 |
| 1436 | #define R_RISCV_SET6 53 |
| 1437 | #define R_RISCV_SET8 54 |
| 1438 | #define R_RISCV_SET16 55 |
| 1439 | #define R_RISCV_SET32 56 |
| 1440 | |
Michael Clark | c02b78c | 2019-03-16 01:20:37 +0000 | [diff] [blame] | 1441 | /* RISC-V ELF Flags. */ |
| 1442 | #define EF_RISCV_RVC 0x0001 |
| 1443 | #define EF_RISCV_FLOAT_ABI 0x0006 |
| 1444 | #define EF_RISCV_FLOAT_ABI_SOFT 0x0000 |
| 1445 | #define EF_RISCV_FLOAT_ABI_SINGLE 0x0002 |
| 1446 | #define EF_RISCV_FLOAT_ABI_DOUBLE 0x0004 |
| 1447 | #define EF_RISCV_FLOAT_ABI_QUAD 0x0006 |
| 1448 | #define EF_RISCV_RVE 0x0008 |
| 1449 | #define EF_RISCV_TSO 0x0010 |
| 1450 | |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1451 | typedef struct elf32_rel { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1452 | Elf32_Addr r_offset; |
| 1453 | Elf32_Word r_info; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1454 | } Elf32_Rel; |
| 1455 | |
| 1456 | typedef struct elf64_rel { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1457 | Elf64_Addr r_offset; /* Location at which to apply the action */ |
| 1458 | Elf64_Xword r_info; /* index and type of relocation */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1459 | } Elf64_Rel; |
| 1460 | |
| 1461 | typedef struct elf32_rela{ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1462 | Elf32_Addr r_offset; |
| 1463 | Elf32_Word r_info; |
| 1464 | Elf32_Sword r_addend; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1465 | } Elf32_Rela; |
| 1466 | |
| 1467 | typedef struct elf64_rela { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1468 | Elf64_Addr r_offset; /* Location at which to apply the action */ |
| 1469 | Elf64_Xword r_info; /* index and type of relocation */ |
| 1470 | Elf64_Sxword r_addend; /* Constant addend used to compute value */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1471 | } Elf64_Rela; |
| 1472 | |
| 1473 | typedef struct elf32_sym{ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1474 | Elf32_Word st_name; |
| 1475 | Elf32_Addr st_value; |
| 1476 | Elf32_Word st_size; |
| 1477 | unsigned char st_info; |
| 1478 | unsigned char st_other; |
| 1479 | Elf32_Half st_shndx; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1480 | } Elf32_Sym; |
| 1481 | |
| 1482 | typedef struct elf64_sym { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1483 | Elf64_Word st_name; /* Symbol name, index in string tbl */ |
| 1484 | unsigned char st_info; /* Type and binding attributes */ |
| 1485 | unsigned char st_other; /* No defined meaning, 0 */ |
| 1486 | Elf64_Half st_shndx; /* Associated section index */ |
| 1487 | Elf64_Addr st_value; /* Value of the symbol */ |
| 1488 | Elf64_Xword st_size; /* Associated symbol size */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1489 | } Elf64_Sym; |
| 1490 | |
| 1491 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1492 | #define EI_NIDENT 16 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1493 | |
Wen Congyang | 783e9b4 | 2012-05-07 12:10:47 +0800 | [diff] [blame] | 1494 | /* Special value for e_phnum. This indicates that the real number of |
| 1495 | program headers is too large to fit into e_phnum. Instead the real |
| 1496 | value is in the field sh_info of section 0. */ |
| 1497 | #define PN_XNUM 0xffff |
| 1498 | |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1499 | typedef struct elf32_hdr{ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1500 | unsigned char e_ident[EI_NIDENT]; |
| 1501 | Elf32_Half e_type; |
| 1502 | Elf32_Half e_machine; |
| 1503 | Elf32_Word e_version; |
| 1504 | Elf32_Addr e_entry; /* Entry point */ |
| 1505 | Elf32_Off e_phoff; |
| 1506 | Elf32_Off e_shoff; |
| 1507 | Elf32_Word e_flags; |
| 1508 | Elf32_Half e_ehsize; |
| 1509 | Elf32_Half e_phentsize; |
| 1510 | Elf32_Half e_phnum; |
| 1511 | Elf32_Half e_shentsize; |
| 1512 | Elf32_Half e_shnum; |
| 1513 | Elf32_Half e_shstrndx; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1514 | } Elf32_Ehdr; |
| 1515 | |
| 1516 | typedef struct elf64_hdr { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1517 | unsigned char e_ident[16]; /* ELF "magic number" */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1518 | Elf64_Half e_type; |
| 1519 | Elf64_Half e_machine; |
| 1520 | Elf64_Word e_version; |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1521 | Elf64_Addr e_entry; /* Entry point virtual address */ |
| 1522 | Elf64_Off e_phoff; /* Program header table file offset */ |
| 1523 | Elf64_Off e_shoff; /* Section header table file offset */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1524 | Elf64_Word e_flags; |
| 1525 | Elf64_Half e_ehsize; |
| 1526 | Elf64_Half e_phentsize; |
| 1527 | Elf64_Half e_phnum; |
| 1528 | Elf64_Half e_shentsize; |
| 1529 | Elf64_Half e_shnum; |
| 1530 | Elf64_Half e_shstrndx; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1531 | } Elf64_Ehdr; |
| 1532 | |
| 1533 | /* These constants define the permissions on sections in the program |
| 1534 | header, p_flags. */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1535 | #define PF_R 0x4 |
| 1536 | #define PF_W 0x2 |
| 1537 | #define PF_X 0x1 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1538 | |
| 1539 | typedef struct elf32_phdr{ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1540 | Elf32_Word p_type; |
| 1541 | Elf32_Off p_offset; |
| 1542 | Elf32_Addr p_vaddr; |
| 1543 | Elf32_Addr p_paddr; |
| 1544 | Elf32_Word p_filesz; |
| 1545 | Elf32_Word p_memsz; |
| 1546 | Elf32_Word p_flags; |
| 1547 | Elf32_Word p_align; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1548 | } Elf32_Phdr; |
| 1549 | |
| 1550 | typedef struct elf64_phdr { |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1551 | Elf64_Word p_type; |
| 1552 | Elf64_Word p_flags; |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1553 | Elf64_Off p_offset; /* Segment file offset */ |
| 1554 | Elf64_Addr p_vaddr; /* Segment virtual address */ |
| 1555 | Elf64_Addr p_paddr; /* Segment physical address */ |
| 1556 | Elf64_Xword p_filesz; /* Segment size in file */ |
| 1557 | Elf64_Xword p_memsz; /* Segment size in memory */ |
| 1558 | Elf64_Xword p_align; /* Segment alignment, file & memory */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1559 | } Elf64_Phdr; |
| 1560 | |
| 1561 | /* sh_type */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1562 | #define SHT_NULL 0 |
| 1563 | #define SHT_PROGBITS 1 |
| 1564 | #define SHT_SYMTAB 2 |
| 1565 | #define SHT_STRTAB 3 |
| 1566 | #define SHT_RELA 4 |
| 1567 | #define SHT_HASH 5 |
| 1568 | #define SHT_DYNAMIC 6 |
| 1569 | #define SHT_NOTE 7 |
| 1570 | #define SHT_NOBITS 8 |
| 1571 | #define SHT_REL 9 |
| 1572 | #define SHT_SHLIB 10 |
| 1573 | #define SHT_DYNSYM 11 |
| 1574 | #define SHT_NUM 12 |
| 1575 | #define SHT_LOPROC 0x70000000 |
| 1576 | #define SHT_HIPROC 0x7fffffff |
| 1577 | #define SHT_LOUSER 0x80000000 |
| 1578 | #define SHT_HIUSER 0xffffffff |
| 1579 | #define SHT_MIPS_LIST 0x70000000 |
| 1580 | #define SHT_MIPS_CONFLICT 0x70000002 |
| 1581 | #define SHT_MIPS_GPTAB 0x70000003 |
| 1582 | #define SHT_MIPS_UCODE 0x70000004 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1583 | |
| 1584 | /* sh_flags */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1585 | #define SHF_WRITE 0x1 |
| 1586 | #define SHF_ALLOC 0x2 |
| 1587 | #define SHF_EXECINSTR 0x4 |
| 1588 | #define SHF_MASKPROC 0xf0000000 |
| 1589 | #define SHF_MIPS_GPREL 0x10000000 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1590 | |
| 1591 | /* special section indexes */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1592 | #define SHN_UNDEF 0 |
| 1593 | #define SHN_LORESERVE 0xff00 |
| 1594 | #define SHN_LOPROC 0xff00 |
| 1595 | #define SHN_HIPROC 0xff1f |
| 1596 | #define SHN_ABS 0xfff1 |
| 1597 | #define SHN_COMMON 0xfff2 |
| 1598 | #define SHN_HIRESERVE 0xffff |
| 1599 | #define SHN_MIPS_ACCOMON 0xff00 |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1600 | |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1601 | typedef struct elf32_shdr { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1602 | Elf32_Word sh_name; |
| 1603 | Elf32_Word sh_type; |
| 1604 | Elf32_Word sh_flags; |
| 1605 | Elf32_Addr sh_addr; |
| 1606 | Elf32_Off sh_offset; |
| 1607 | Elf32_Word sh_size; |
| 1608 | Elf32_Word sh_link; |
| 1609 | Elf32_Word sh_info; |
| 1610 | Elf32_Word sh_addralign; |
| 1611 | Elf32_Word sh_entsize; |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1612 | } Elf32_Shdr; |
| 1613 | |
| 1614 | typedef struct elf64_shdr { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1615 | Elf64_Word sh_name; /* Section name, index in string tbl */ |
| 1616 | Elf64_Word sh_type; /* Type of section */ |
| 1617 | Elf64_Xword sh_flags; /* Miscellaneous section attributes */ |
| 1618 | Elf64_Addr sh_addr; /* Section virtual addr at execution */ |
| 1619 | Elf64_Off sh_offset; /* Section file offset */ |
| 1620 | Elf64_Xword sh_size; /* Size of section in bytes */ |
| 1621 | Elf64_Word sh_link; /* Index of another section */ |
| 1622 | Elf64_Word sh_info; /* Additional section information */ |
| 1623 | Elf64_Xword sh_addralign; /* Section alignment */ |
| 1624 | Elf64_Xword sh_entsize; /* Entry size if section holds table */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1625 | } Elf64_Shdr; |
| 1626 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1627 | #define EI_MAG0 0 /* e_ident[] indexes */ |
| 1628 | #define EI_MAG1 1 |
| 1629 | #define EI_MAG2 2 |
| 1630 | #define EI_MAG3 3 |
| 1631 | #define EI_CLASS 4 |
| 1632 | #define EI_DATA 5 |
| 1633 | #define EI_VERSION 6 |
| 1634 | #define EI_OSABI 7 |
| 1635 | #define EI_PAD 8 |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 1636 | |
| 1637 | #define ELFOSABI_NONE 0 /* UNIX System V ABI */ |
| 1638 | #define ELFOSABI_SYSV 0 /* Alias. */ |
| 1639 | #define ELFOSABI_HPUX 1 /* HP-UX */ |
| 1640 | #define ELFOSABI_NETBSD 2 /* NetBSD. */ |
| 1641 | #define ELFOSABI_LINUX 3 /* Linux. */ |
| 1642 | #define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ |
| 1643 | #define ELFOSABI_AIX 7 /* IBM AIX. */ |
| 1644 | #define ELFOSABI_IRIX 8 /* SGI Irix. */ |
| 1645 | #define ELFOSABI_FREEBSD 9 /* FreeBSD. */ |
| 1646 | #define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ |
| 1647 | #define ELFOSABI_MODESTO 11 /* Novell Modesto. */ |
| 1648 | #define ELFOSABI_OPENBSD 12 /* OpenBSD. */ |
Christophe Lyon | cf58aff | 2018-04-30 10:03:42 +0200 | [diff] [blame] | 1649 | #define ELFOSABI_ARM_FDPIC 65 /* ARM FDPIC */ |
Max Filippov | d2796be | 2023-02-04 22:12:30 -0800 | [diff] [blame] | 1650 | #define ELFOSABI_XTENSA_FDPIC 65 /* Xtensa FDPIC */ |
Mika Westerberg | edf8e2a | 2009-04-07 09:57:11 +0300 | [diff] [blame] | 1651 | #define ELFOSABI_ARM 97 /* ARM */ |
| 1652 | #define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1653 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1654 | #define ELFMAG0 0x7f /* EI_MAG */ |
| 1655 | #define ELFMAG1 'E' |
| 1656 | #define ELFMAG2 'L' |
| 1657 | #define ELFMAG3 'F' |
| 1658 | #define ELFMAG "\177ELF" |
| 1659 | #define SELFMAG 4 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1660 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1661 | #define ELFCLASSNONE 0 /* EI_CLASS */ |
| 1662 | #define ELFCLASS32 1 |
| 1663 | #define ELFCLASS64 2 |
| 1664 | #define ELFCLASSNUM 3 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1665 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1666 | #define ELFDATANONE 0 /* e_ident[EI_DATA] */ |
| 1667 | #define ELFDATA2LSB 1 |
| 1668 | #define ELFDATA2MSB 2 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1669 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1670 | #define EV_NONE 0 /* e_version, EI_VERSION */ |
| 1671 | #define EV_CURRENT 1 |
| 1672 | #define EV_NUM 2 |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1673 | |
| 1674 | /* Notes used in ET_CORE */ |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1675 | #define NT_PRSTATUS 1 |
| 1676 | #define NT_FPREGSET 2 |
| 1677 | #define NT_PRFPREG 2 |
| 1678 | #define NT_PRPSINFO 3 |
| 1679 | #define NT_TASKSTRUCT 4 |
| 1680 | #define NT_AUXV 6 |
| 1681 | #define NT_PRXFPREG 0x46e62b7f /* copied from gdb5.1/include/elf/common.h */ |
| 1682 | #define NT_S390_PV_CPU_DATA 0x30e /* s390 protvirt cpu dump data */ |
| 1683 | #define NT_S390_RI_CB 0x30d /* s390 runtime instrumentation */ |
| 1684 | #define NT_S390_GS_CB 0x30b /* s390 guarded storage registers */ |
| 1685 | #define NT_S390_VXRS_HIGH 0x30a /* s390 vector registers 16-31 */ |
| 1686 | #define NT_S390_VXRS_LOW 0x309 /* s390 vector registers 0-15 (lower half) */ |
| 1687 | #define NT_S390_PREFIX 0x305 /* s390 prefix register */ |
| 1688 | #define NT_S390_CTRS 0x304 /* s390 control registers */ |
| 1689 | #define NT_S390_TODPREG 0x303 /* s390 TOD programmable register */ |
| 1690 | #define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */ |
| 1691 | #define NT_S390_TIMER 0x301 /* s390 timer register */ |
| 1692 | #define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ |
| 1693 | #define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ |
| 1694 | #define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ |
| 1695 | #define NT_ARM_VFP 0x400 /* ARM VFP/NEON registers */ |
| 1696 | #define NT_ARM_TLS 0x401 /* ARM TLS register */ |
| 1697 | #define NT_ARM_HW_BREAK 0x402 /* ARM hardware breakpoint registers */ |
| 1698 | #define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */ |
| 1699 | #define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */ |
| 1700 | #define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension regs */ |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1701 | |
Richard Henderson | 069175b | 2020-10-21 10:37:40 -0700 | [diff] [blame] | 1702 | /* Defined note types for GNU systems. */ |
| 1703 | |
| 1704 | #define NT_GNU_PROPERTY_TYPE_0 5 /* Program property */ |
| 1705 | |
| 1706 | /* Values used in GNU .note.gnu.property notes (NT_GNU_PROPERTY_TYPE_0). */ |
| 1707 | |
| 1708 | #define GNU_PROPERTY_STACK_SIZE 1 |
| 1709 | #define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2 |
| 1710 | |
| 1711 | #define GNU_PROPERTY_LOPROC 0xc0000000 |
| 1712 | #define GNU_PROPERTY_HIPROC 0xdfffffff |
| 1713 | #define GNU_PROPERTY_LOUSER 0xe0000000 |
| 1714 | #define GNU_PROPERTY_HIUSER 0xffffffff |
| 1715 | |
| 1716 | #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 |
| 1717 | #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1u << 0) |
| 1718 | #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1u << 1) |
| 1719 | |
Liam Merwick | ab96908 | 2019-01-15 12:18:06 +0000 | [diff] [blame] | 1720 | /* |
| 1721 | * Physical entry point into the kernel. |
| 1722 | * |
| 1723 | * 32bit entry point into the kernel. When requested to launch the |
| 1724 | * guest kernel, use this entry point to launch the guest in 32-bit |
| 1725 | * protected mode with paging disabled. |
| 1726 | * |
| 1727 | * [ Corresponding definition in Linux kernel: include/xen/interface/elfnote.h ] |
| 1728 | */ |
| 1729 | #define XEN_ELFNOTE_PHYS32_ENTRY 18 /* 0x12 */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1730 | |
| 1731 | /* Note header in a PT_NOTE section */ |
| 1732 | typedef struct elf32_note { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1733 | Elf32_Word n_namesz; /* Name size */ |
| 1734 | Elf32_Word n_descsz; /* Content size */ |
| 1735 | Elf32_Word n_type; /* Content type */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1736 | } Elf32_Nhdr; |
| 1737 | |
| 1738 | /* Note header in a PT_NOTE section */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1739 | typedef struct elf64_note { |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1740 | Elf64_Word n_namesz; /* Name size */ |
| 1741 | Elf64_Word n_descsz; /* Content size */ |
| 1742 | Elf64_Word n_type; /* Content type */ |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1743 | } Elf64_Nhdr; |
| 1744 | |
Mike Frysinger | 1af02e8 | 2011-02-07 01:05:50 -0500 | [diff] [blame] | 1745 | |
| 1746 | /* This data structure represents a PT_LOAD segment. */ |
| 1747 | struct elf32_fdpic_loadseg { |
| 1748 | /* Core address to which the segment is mapped. */ |
| 1749 | Elf32_Addr addr; |
| 1750 | /* VMA recorded in the program header. */ |
| 1751 | Elf32_Addr p_vaddr; |
| 1752 | /* Size of this segment in memory. */ |
| 1753 | Elf32_Word p_memsz; |
| 1754 | }; |
| 1755 | struct elf32_fdpic_loadmap { |
| 1756 | /* Protocol version number, must be zero. */ |
| 1757 | Elf32_Half version; |
| 1758 | /* Number of segments in this map. */ |
| 1759 | Elf32_Half nsegs; |
| 1760 | /* The actual memory map. */ |
| 1761 | struct elf32_fdpic_loadseg segs[/*nsegs*/]; |
| 1762 | }; |
| 1763 | |
blueswir1 | eb38c52 | 2008-09-06 17:47:39 +0000 | [diff] [blame] | 1764 | #ifdef ELF_CLASS |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1765 | #if ELF_CLASS == ELFCLASS32 |
| 1766 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1767 | #define elfhdr elf32_hdr |
| 1768 | #define elf_phdr elf32_phdr |
| 1769 | #define elf_note elf32_note |
| 1770 | #define elf_shdr elf32_shdr |
| 1771 | #define elf_sym elf32_sym |
| 1772 | #define elf_addr_t Elf32_Off |
| 1773 | #define elf_rela elf32_rela |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1774 | |
| 1775 | #ifdef ELF_USES_RELOCA |
| 1776 | # define ELF_RELOC Elf32_Rela |
| 1777 | #else |
| 1778 | # define ELF_RELOC Elf32_Rel |
| 1779 | #endif |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1780 | |
| 1781 | #else |
| 1782 | |
Yeqi Fu | 48805df | 2023-03-15 11:26:49 +0800 | [diff] [blame] | 1783 | #define elfhdr elf64_hdr |
| 1784 | #define elf_phdr elf64_phdr |
| 1785 | #define elf_note elf64_note |
| 1786 | #define elf_shdr elf64_shdr |
| 1787 | #define elf_sym elf64_sym |
| 1788 | #define elf_addr_t Elf64_Off |
| 1789 | #define elf_rela elf64_rela |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1790 | |
bellard | 8857052 | 2003-04-07 21:32:32 +0000 | [diff] [blame] | 1791 | #ifdef ELF_USES_RELOCA |
| 1792 | # define ELF_RELOC Elf64_Rela |
| 1793 | #else |
| 1794 | # define ELF_RELOC Elf64_Rel |
| 1795 | #endif |
| 1796 | |
| 1797 | #endif /* ELF_CLASS */ |
| 1798 | |
| 1799 | #ifndef ElfW |
| 1800 | # if ELF_CLASS == ELFCLASS32 |
| 1801 | # define ElfW(x) Elf32_ ## x |
| 1802 | # define ELFW(x) ELF32_ ## x |
| 1803 | # else |
| 1804 | # define ElfW(x) Elf64_ ## x |
| 1805 | # define ELFW(x) ELF64_ ## x |
| 1806 | # endif |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1807 | #endif |
| 1808 | |
blueswir1 | eb38c52 | 2008-09-06 17:47:39 +0000 | [diff] [blame] | 1809 | #endif /* ELF_CLASS */ |
| 1810 | |
bellard | 31e31b8 | 2003-02-18 22:55:36 +0000 | [diff] [blame] | 1811 | |
Markus Armbruster | 2a6a407 | 2016-06-29 13:47:03 +0200 | [diff] [blame] | 1812 | #endif /* QEMU_ELF_H */ |