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bellardb9adb4a2003-04-29 20:41:16 +00001/* General "disassemble this chunk" code. Used for debugging. */
bellard5bbe9292003-06-09 19:38:38 +00002#include "config.h"
Paolo Bonzini76cad712012-10-24 11:12:21 +02003#include "disas/bfd.h"
bellardb9adb4a2003-04-29 20:41:16 +00004#include "elf.h"
bellardaa0aa4f2003-06-09 15:23:31 +00005#include <errno.h>
bellardb9adb4a2003-04-29 20:41:16 +00006
bellardc6105c02003-10-27 21:13:58 +00007#include "cpu.h"
Paolo Bonzini76cad712012-10-24 11:12:21 +02008#include "disas/disas.h"
bellardc6105c02003-10-27 21:13:58 +00009
Blue Swirlf4359b92012-09-08 12:40:00 +000010typedef struct CPUDebug {
11 struct disassemble_info info;
12 CPUArchState *env;
13} CPUDebug;
14
bellardb9adb4a2003-04-29 20:41:16 +000015/* Filled in by elfload.c. Simplistic, but will do for now. */
bellarde80cfcf2004-12-19 23:18:01 +000016struct syminfo *syminfos = NULL;
bellardb9adb4a2003-04-29 20:41:16 +000017
bellardaa0aa4f2003-06-09 15:23:31 +000018/* Get LENGTH bytes from info's buffer, at target address memaddr.
19 Transfer them to myaddr. */
20int
pbrook3a742b72008-10-22 15:55:18 +000021buffer_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length,
22 struct disassemble_info *info)
bellardaa0aa4f2003-06-09 15:23:31 +000023{
bellardc6105c02003-10-27 21:13:58 +000024 if (memaddr < info->buffer_vma
25 || memaddr + length > info->buffer_vma + info->buffer_length)
26 /* Out of bounds. Use EIO because GDB uses it. */
27 return EIO;
28 memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length);
29 return 0;
bellardaa0aa4f2003-06-09 15:23:31 +000030}
31
bellardc6105c02003-10-27 21:13:58 +000032/* Get LENGTH bytes from info's buffer, at target address memaddr.
33 Transfer them to myaddr. */
34static int
bellardc27004e2005-01-03 23:35:10 +000035target_read_memory (bfd_vma memaddr,
36 bfd_byte *myaddr,
37 int length,
38 struct disassemble_info *info)
bellardc6105c02003-10-27 21:13:58 +000039{
Blue Swirlf4359b92012-09-08 12:40:00 +000040 CPUDebug *s = container_of(info, CPUDebug, info);
41
42 cpu_memory_rw_debug(s->env, memaddr, myaddr, length, 0);
bellardc6105c02003-10-27 21:13:58 +000043 return 0;
44}
bellardc6105c02003-10-27 21:13:58 +000045
bellardaa0aa4f2003-06-09 15:23:31 +000046/* Print an error message. We can assume that this is in response to
47 an error return from buffer_read_memory. */
48void
pbrook3a742b72008-10-22 15:55:18 +000049perror_memory (int status, bfd_vma memaddr, struct disassemble_info *info)
bellardaa0aa4f2003-06-09 15:23:31 +000050{
51 if (status != EIO)
52 /* Can't happen. */
53 (*info->fprintf_func) (info->stream, "Unknown error %d\n", status);
54 else
55 /* Actually, address between memaddr and memaddr + len was
56 out of bounds. */
57 (*info->fprintf_func) (info->stream,
bellard26a76462006-06-25 18:15:32 +000058 "Address 0x%" PRIx64 " is out of bounds.\n", memaddr);
bellardaa0aa4f2003-06-09 15:23:31 +000059}
60
Jim Meyeringa31f0532012-05-09 05:12:04 +000061/* This could be in a separate file, to save minuscule amounts of space
bellardaa0aa4f2003-06-09 15:23:31 +000062 in statically linked executables. */
63
64/* Just print the address is hex. This is included for completeness even
65 though both GDB and objdump provide their own (to print symbolic
66 addresses). */
67
68void
pbrook3a742b72008-10-22 15:55:18 +000069generic_print_address (bfd_vma addr, struct disassemble_info *info)
bellardaa0aa4f2003-06-09 15:23:31 +000070{
bellard26a76462006-06-25 18:15:32 +000071 (*info->fprintf_func) (info->stream, "0x%" PRIx64, addr);
bellardaa0aa4f2003-06-09 15:23:31 +000072}
73
Peter Maydell636bd282012-06-25 04:55:55 +000074/* Print address in hex, truncated to the width of a target virtual address. */
75static void
76generic_print_target_address(bfd_vma addr, struct disassemble_info *info)
77{
78 uint64_t mask = ~0ULL >> (64 - TARGET_VIRT_ADDR_SPACE_BITS);
79 generic_print_address(addr & mask, info);
80}
81
82/* Print address in hex, truncated to the width of a host virtual address. */
83static void
84generic_print_host_address(bfd_vma addr, struct disassemble_info *info)
85{
86 uint64_t mask = ~0ULL >> (64 - (sizeof(void *) * 8));
87 generic_print_address(addr & mask, info);
88}
89
bellardaa0aa4f2003-06-09 15:23:31 +000090/* Just return the given address. */
91
92int
pbrook3a742b72008-10-22 15:55:18 +000093generic_symbol_at_address (bfd_vma addr, struct disassemble_info *info)
bellardaa0aa4f2003-06-09 15:23:31 +000094{
95 return 1;
96}
97
Aurelien Jarno903ec552010-03-29 02:12:51 +020098bfd_vma bfd_getl64 (const bfd_byte *addr)
99{
100 unsigned long long v;
101
102 v = (unsigned long long) addr[0];
103 v |= (unsigned long long) addr[1] << 8;
104 v |= (unsigned long long) addr[2] << 16;
105 v |= (unsigned long long) addr[3] << 24;
106 v |= (unsigned long long) addr[4] << 32;
107 v |= (unsigned long long) addr[5] << 40;
108 v |= (unsigned long long) addr[6] << 48;
109 v |= (unsigned long long) addr[7] << 56;
110 return (bfd_vma) v;
111}
112
bellardaa0aa4f2003-06-09 15:23:31 +0000113bfd_vma bfd_getl32 (const bfd_byte *addr)
114{
115 unsigned long v;
116
117 v = (unsigned long) addr[0];
118 v |= (unsigned long) addr[1] << 8;
119 v |= (unsigned long) addr[2] << 16;
120 v |= (unsigned long) addr[3] << 24;
121 return (bfd_vma) v;
122}
123
124bfd_vma bfd_getb32 (const bfd_byte *addr)
125{
126 unsigned long v;
127
128 v = (unsigned long) addr[0] << 24;
129 v |= (unsigned long) addr[1] << 16;
130 v |= (unsigned long) addr[2] << 8;
131 v |= (unsigned long) addr[3];
132 return (bfd_vma) v;
133}
134
bellard6af0bf92005-07-02 14:58:51 +0000135bfd_vma bfd_getl16 (const bfd_byte *addr)
136{
137 unsigned long v;
138
139 v = (unsigned long) addr[0];
140 v |= (unsigned long) addr[1] << 8;
141 return (bfd_vma) v;
142}
143
144bfd_vma bfd_getb16 (const bfd_byte *addr)
145{
146 unsigned long v;
147
148 v = (unsigned long) addr[0] << 24;
149 v |= (unsigned long) addr[1] << 16;
150 return (bfd_vma) v;
151}
152
bellardc2d551f2005-04-27 20:15:00 +0000153#ifdef TARGET_ARM
154static int
155print_insn_thumb1(bfd_vma pc, disassemble_info *info)
156{
157 return print_insn_arm(pc | 1, info);
158}
159#endif
160
thse91c8a72007-06-03 13:35:16 +0000161/* Disassemble this for me please... (debugging). 'flags' has the following
bellardc2d551f2005-04-27 20:15:00 +0000162 values:
Frediano Ziglioe99722f2011-08-25 09:14:38 +0200163 i386 - 1 means 16 bit code, 2 means 64 bit code
Paul Brookd8fd2952012-03-30 18:02:50 +0100164 arm - bit 0 = thumb, bit 1 = reverse endian
bellard6a00d602005-11-21 23:25:50 +0000165 ppc - nonzero means little endian
bellardc2d551f2005-04-27 20:15:00 +0000166 other targets - unused
167 */
Blue Swirlf4359b92012-09-08 12:40:00 +0000168void target_disas(FILE *out, CPUArchState *env, target_ulong code,
169 target_ulong size, int flags)
bellardb9adb4a2003-04-29 20:41:16 +0000170{
bellardc27004e2005-01-03 23:35:10 +0000171 target_ulong pc;
bellardb9adb4a2003-04-29 20:41:16 +0000172 int count;
Blue Swirlf4359b92012-09-08 12:40:00 +0000173 CPUDebug s;
bellardb9adb4a2003-04-29 20:41:16 +0000174 int (*print_insn)(bfd_vma pc, disassemble_info *info);
175
Blue Swirlf4359b92012-09-08 12:40:00 +0000176 INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
bellardb9adb4a2003-04-29 20:41:16 +0000177
Blue Swirlf4359b92012-09-08 12:40:00 +0000178 s.env = env;
179 s.info.read_memory_func = target_read_memory;
180 s.info.buffer_vma = code;
181 s.info.buffer_length = size;
182 s.info.print_address_func = generic_print_target_address;
bellardc27004e2005-01-03 23:35:10 +0000183
184#ifdef TARGET_WORDS_BIGENDIAN
Blue Swirlf4359b92012-09-08 12:40:00 +0000185 s.info.endian = BFD_ENDIAN_BIG;
bellardc27004e2005-01-03 23:35:10 +0000186#else
Blue Swirlf4359b92012-09-08 12:40:00 +0000187 s.info.endian = BFD_ENDIAN_LITTLE;
bellardc6105c02003-10-27 21:13:58 +0000188#endif
bellardc27004e2005-01-03 23:35:10 +0000189#if defined(TARGET_I386)
Blue Swirlf4359b92012-09-08 12:40:00 +0000190 if (flags == 2) {
191 s.info.mach = bfd_mach_x86_64;
192 } else if (flags == 1) {
193 s.info.mach = bfd_mach_i386_i8086;
194 } else {
195 s.info.mach = bfd_mach_i386_i386;
196 }
bellardc27004e2005-01-03 23:35:10 +0000197 print_insn = print_insn_i386;
198#elif defined(TARGET_ARM)
Paul Brookd8fd2952012-03-30 18:02:50 +0100199 if (flags & 1) {
200 print_insn = print_insn_thumb1;
201 } else {
202 print_insn = print_insn_arm;
203 }
204 if (flags & 2) {
205#ifdef TARGET_WORDS_BIGENDIAN
Blue Swirlf4359b92012-09-08 12:40:00 +0000206 s.info.endian = BFD_ENDIAN_LITTLE;
Paul Brookd8fd2952012-03-30 18:02:50 +0100207#else
Blue Swirlf4359b92012-09-08 12:40:00 +0000208 s.info.endian = BFD_ENDIAN_BIG;
Paul Brookd8fd2952012-03-30 18:02:50 +0100209#endif
210 }
bellardc27004e2005-01-03 23:35:10 +0000211#elif defined(TARGET_SPARC)
212 print_insn = print_insn_sparc;
bellard34751872005-07-02 14:31:34 +0000213#ifdef TARGET_SPARC64
Blue Swirlf4359b92012-09-08 12:40:00 +0000214 s.info.mach = bfd_mach_sparc_v9b;
ths3b46e622007-09-17 08:09:54 +0000215#endif
bellardc27004e2005-01-03 23:35:10 +0000216#elif defined(TARGET_PPC)
Blue Swirlf4359b92012-09-08 12:40:00 +0000217 if (flags >> 16) {
218 s.info.endian = BFD_ENDIAN_LITTLE;
219 }
j_mayer237c0af2007-09-29 12:01:46 +0000220 if (flags & 0xFFFF) {
221 /* If we have a precise definitions of the instructions set, use it */
Blue Swirlf4359b92012-09-08 12:40:00 +0000222 s.info.mach = flags & 0xFFFF;
j_mayer237c0af2007-09-29 12:01:46 +0000223 } else {
bellarda2458622005-07-23 22:39:53 +0000224#ifdef TARGET_PPC64
Blue Swirlf4359b92012-09-08 12:40:00 +0000225 s.info.mach = bfd_mach_ppc64;
bellarda2458622005-07-23 22:39:53 +0000226#else
Blue Swirlf4359b92012-09-08 12:40:00 +0000227 s.info.mach = bfd_mach_ppc;
bellarda2458622005-07-23 22:39:53 +0000228#endif
j_mayer237c0af2007-09-29 12:01:46 +0000229 }
Aurelien Jarno88770fe2013-04-20 08:56:14 +0000230 s.info.disassembler_options = (char *)"any";
bellardc27004e2005-01-03 23:35:10 +0000231 print_insn = print_insn_ppc;
pbrooke6e59062006-10-22 00:18:54 +0000232#elif defined(TARGET_M68K)
233 print_insn = print_insn_m68k;
bellard6af0bf92005-07-02 14:58:51 +0000234#elif defined(TARGET_MIPS)
bellard76b30302005-12-17 01:10:04 +0000235#ifdef TARGET_WORDS_BIGENDIAN
bellard6af0bf92005-07-02 14:58:51 +0000236 print_insn = print_insn_big_mips;
bellard76b30302005-12-17 01:10:04 +0000237#else
238 print_insn = print_insn_little_mips;
239#endif
bellardfdf9b3e2006-04-27 21:07:38 +0000240#elif defined(TARGET_SH4)
Blue Swirlf4359b92012-09-08 12:40:00 +0000241 s.info.mach = bfd_mach_sh4;
bellardfdf9b3e2006-04-27 21:07:38 +0000242 print_insn = print_insn_sh;
j_mayereddf68a2007-04-05 07:22:49 +0000243#elif defined(TARGET_ALPHA)
Blue Swirlf4359b92012-09-08 12:40:00 +0000244 s.info.mach = bfd_mach_alpha_ev6;
j_mayereddf68a2007-04-05 07:22:49 +0000245 print_insn = print_insn_alpha;
thsa25fd132007-10-08 12:46:58 +0000246#elif defined(TARGET_CRIS)
Edgar E. Iglesiasb09cd072011-01-10 22:31:09 +0100247 if (flags != 32) {
Blue Swirlf4359b92012-09-08 12:40:00 +0000248 s.info.mach = bfd_mach_cris_v0_v10;
Edgar E. Iglesiasb09cd072011-01-10 22:31:09 +0100249 print_insn = print_insn_crisv10;
250 } else {
Blue Swirlf4359b92012-09-08 12:40:00 +0000251 s.info.mach = bfd_mach_cris_v32;
Edgar E. Iglesiasb09cd072011-01-10 22:31:09 +0100252 print_insn = print_insn_crisv32;
253 }
Ulrich Hechtdb500602011-03-29 15:29:32 +0200254#elif defined(TARGET_S390X)
Blue Swirlf4359b92012-09-08 12:40:00 +0000255 s.info.mach = bfd_mach_s390_64;
Ulrich Hechtdb500602011-03-29 15:29:32 +0200256 print_insn = print_insn_s390;
Edgar E. Iglesiase90e3902009-05-20 20:07:38 +0200257#elif defined(TARGET_MICROBLAZE)
Blue Swirlf4359b92012-09-08 12:40:00 +0000258 s.info.mach = bfd_arch_microblaze;
Edgar E. Iglesiase90e3902009-05-20 20:07:38 +0200259 print_insn = print_insn_microblaze;
Anthony Greenbd86a882013-03-18 15:49:23 -0400260#elif defined(TARGET_MOXIE)
261 s.info.mach = bfd_arch_moxie;
262 print_insn = print_insn_moxie;
Michael Walle79368f42012-03-31 19:54:20 +0200263#elif defined(TARGET_LM32)
Blue Swirlf4359b92012-09-08 12:40:00 +0000264 s.info.mach = bfd_mach_lm32;
Michael Walle79368f42012-03-31 19:54:20 +0200265 print_insn = print_insn_lm32;
bellardc27004e2005-01-03 23:35:10 +0000266#else
bellardb8076a72005-04-07 22:20:31 +0000267 fprintf(out, "0x" TARGET_FMT_lx
268 ": Asm output not supported on this arch\n", code);
bellardc27004e2005-01-03 23:35:10 +0000269 return;
270#endif
271
blueswir17e000c22009-02-13 21:44:41 +0000272 for (pc = code; size > 0; pc += count, size -= count) {
bellardfa15e032005-01-31 23:32:31 +0000273 fprintf(out, "0x" TARGET_FMT_lx ": ", pc);
Blue Swirlf4359b92012-09-08 12:40:00 +0000274 count = print_insn(pc, &s.info);
bellardc27004e2005-01-03 23:35:10 +0000275#if 0
276 {
277 int i;
278 uint8_t b;
279 fprintf(out, " {");
280 for(i = 0; i < count; i++) {
Blue Swirlf4359b92012-09-08 12:40:00 +0000281 target_read_memory(pc + i, &b, 1, &s.info);
bellardc27004e2005-01-03 23:35:10 +0000282 fprintf(out, " %02x", b);
283 }
284 fprintf(out, " }");
285 }
286#endif
287 fprintf(out, "\n");
288 if (count < 0)
289 break;
malc754d00a2009-04-21 22:26:22 +0000290 if (size < count) {
291 fprintf(out,
292 "Disassembler disagrees with translator over instruction "
293 "decoding\n"
294 "Please report this to qemu-devel@nongnu.org\n");
295 break;
296 }
bellardc27004e2005-01-03 23:35:10 +0000297 }
298}
299
300/* Disassemble this for me please... (debugging). */
301void disas(FILE *out, void *code, unsigned long size)
302{
Stefan Weilb0b0f1c2012-04-12 15:44:35 +0200303 uintptr_t pc;
bellardc27004e2005-01-03 23:35:10 +0000304 int count;
Blue Swirlf4359b92012-09-08 12:40:00 +0000305 CPUDebug s;
bellardc27004e2005-01-03 23:35:10 +0000306 int (*print_insn)(bfd_vma pc, disassemble_info *info);
307
Blue Swirlf4359b92012-09-08 12:40:00 +0000308 INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
309 s.info.print_address_func = generic_print_host_address;
bellardc6105c02003-10-27 21:13:58 +0000310
Blue Swirlf4359b92012-09-08 12:40:00 +0000311 s.info.buffer = code;
312 s.info.buffer_vma = (uintptr_t)code;
313 s.info.buffer_length = size;
bellardb9adb4a2003-04-29 20:41:16 +0000314
Juan Quintelae2542fe2009-07-27 16:13:06 +0200315#ifdef HOST_WORDS_BIGENDIAN
Blue Swirlf4359b92012-09-08 12:40:00 +0000316 s.info.endian = BFD_ENDIAN_BIG;
bellardb9adb4a2003-04-29 20:41:16 +0000317#else
Blue Swirlf4359b92012-09-08 12:40:00 +0000318 s.info.endian = BFD_ENDIAN_LITTLE;
bellardb9adb4a2003-04-29 20:41:16 +0000319#endif
Stefan Weil5826e512011-10-05 20:03:53 +0200320#if defined(CONFIG_TCG_INTERPRETER)
321 print_insn = print_insn_tci;
322#elif defined(__i386__)
Blue Swirlf4359b92012-09-08 12:40:00 +0000323 s.info.mach = bfd_mach_i386_i386;
bellardc27004e2005-01-03 23:35:10 +0000324 print_insn = print_insn_i386;
bellardbc51c5c2004-03-17 23:46:04 +0000325#elif defined(__x86_64__)
Blue Swirlf4359b92012-09-08 12:40:00 +0000326 s.info.mach = bfd_mach_x86_64;
bellardc27004e2005-01-03 23:35:10 +0000327 print_insn = print_insn_i386;
malce58ffeb2009-01-14 18:39:49 +0000328#elif defined(_ARCH_PPC)
Richard Henderson66d4f6a2013-01-31 11:16:21 -0800329 s.info.disassembler_options = (char *)"any";
bellardc27004e2005-01-03 23:35:10 +0000330 print_insn = print_insn_ppc;
bellarda993ba82003-05-11 12:25:45 +0000331#elif defined(__alpha__)
bellardc27004e2005-01-03 23:35:10 +0000332 print_insn = print_insn_alpha;
bellardaa0aa4f2003-06-09 15:23:31 +0000333#elif defined(__sparc__)
bellardc27004e2005-01-03 23:35:10 +0000334 print_insn = print_insn_sparc;
Blue Swirlf4359b92012-09-08 12:40:00 +0000335 s.info.mach = bfd_mach_sparc_v9b;
ths5fafdf22007-09-16 21:08:06 +0000336#elif defined(__arm__)
bellardc27004e2005-01-03 23:35:10 +0000337 print_insn = print_insn_arm;
bellard6af0bf92005-07-02 14:58:51 +0000338#elif defined(__MIPSEB__)
339 print_insn = print_insn_big_mips;
340#elif defined(__MIPSEL__)
341 print_insn = print_insn_little_mips;
bellard48024e42005-11-06 16:52:11 +0000342#elif defined(__m68k__)
343 print_insn = print_insn_m68k;
ths8f860bb2007-07-31 23:44:21 +0000344#elif defined(__s390__)
345 print_insn = print_insn_s390;
aurel32f54b3f92008-04-12 20:14:54 +0000346#elif defined(__hppa__)
347 print_insn = print_insn_hppa;
Aurelien Jarno903ec552010-03-29 02:12:51 +0200348#elif defined(__ia64__)
349 print_insn = print_insn_ia64;
bellardb9adb4a2003-04-29 20:41:16 +0000350#else
bellardb8076a72005-04-07 22:20:31 +0000351 fprintf(out, "0x%lx: Asm output not supported on this arch\n",
352 (long) code);
bellardc27004e2005-01-03 23:35:10 +0000353 return;
bellardb9adb4a2003-04-29 20:41:16 +0000354#endif
Stefan Weilb0b0f1c2012-04-12 15:44:35 +0200355 for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) {
356 fprintf(out, "0x%08" PRIxPTR ": ", pc);
Blue Swirlf4359b92012-09-08 12:40:00 +0000357 count = print_insn(pc, &s.info);
bellardb9adb4a2003-04-29 20:41:16 +0000358 fprintf(out, "\n");
359 if (count < 0)
360 break;
361 }
362}
363
364/* Look up symbol for debugging purpose. Returns "" if unknown. */
bellardc27004e2005-01-03 23:35:10 +0000365const char *lookup_symbol(target_ulong orig_addr)
bellardb9adb4a2003-04-29 20:41:16 +0000366{
pbrook49918a72008-10-22 15:11:31 +0000367 const char *symbol = "";
bellarde80cfcf2004-12-19 23:18:01 +0000368 struct syminfo *s;
ths3b46e622007-09-17 08:09:54 +0000369
bellarde80cfcf2004-12-19 23:18:01 +0000370 for (s = syminfos; s; s = s->next) {
pbrook49918a72008-10-22 15:11:31 +0000371 symbol = s->lookup_symbol(s, orig_addr);
372 if (symbol[0] != '\0') {
373 break;
374 }
bellardb9adb4a2003-04-29 20:41:16 +0000375 }
pbrook49918a72008-10-22 15:11:31 +0000376
377 return symbol;
bellardb9adb4a2003-04-29 20:41:16 +0000378}
bellard9307c4c2004-04-04 12:57:25 +0000379
380#if !defined(CONFIG_USER_ONLY)
381
Paolo Bonzini83c90892012-12-17 18:19:49 +0100382#include "monitor/monitor.h"
bellard3d2cfdf2004-08-01 21:49:07 +0000383
bellard9307c4c2004-04-04 12:57:25 +0000384static int monitor_disas_is_physical;
385
386static int
blueswir1a5f1b962008-08-17 20:21:51 +0000387monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
388 struct disassemble_info *info)
bellard9307c4c2004-04-04 12:57:25 +0000389{
Blue Swirlf4359b92012-09-08 12:40:00 +0000390 CPUDebug *s = container_of(info, CPUDebug, info);
391
bellard9307c4c2004-04-04 12:57:25 +0000392 if (monitor_disas_is_physical) {
Stefan Weil54f7b4a2011-04-10 18:23:39 +0200393 cpu_physical_memory_read(memaddr, myaddr, length);
bellard9307c4c2004-04-04 12:57:25 +0000394 } else {
Blue Swirlf4359b92012-09-08 12:40:00 +0000395 cpu_memory_rw_debug(s->env, memaddr,myaddr, length, 0);
bellard9307c4c2004-04-04 12:57:25 +0000396 }
397 return 0;
398}
399
Stefan Weil8b7968f2010-09-23 21:28:05 +0200400static int GCC_FMT_ATTR(2, 3)
401monitor_fprintf(FILE *stream, const char *fmt, ...)
bellard3d2cfdf2004-08-01 21:49:07 +0000402{
403 va_list ap;
404 va_start(ap, fmt);
aliguori376253e2009-03-05 23:01:23 +0000405 monitor_vprintf((Monitor *)stream, fmt, ap);
bellard3d2cfdf2004-08-01 21:49:07 +0000406 va_end(ap);
407 return 0;
408}
409
Andreas Färber9349b4f2012-03-14 01:38:32 +0100410void monitor_disas(Monitor *mon, CPUArchState *env,
bellard6a00d602005-11-21 23:25:50 +0000411 target_ulong pc, int nb_insn, int is_physical, int flags)
bellard9307c4c2004-04-04 12:57:25 +0000412{
bellard9307c4c2004-04-04 12:57:25 +0000413 int count, i;
Blue Swirlf4359b92012-09-08 12:40:00 +0000414 CPUDebug s;
bellard9307c4c2004-04-04 12:57:25 +0000415 int (*print_insn)(bfd_vma pc, disassemble_info *info);
416
Blue Swirlf4359b92012-09-08 12:40:00 +0000417 INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf);
bellard9307c4c2004-04-04 12:57:25 +0000418
Blue Swirlf4359b92012-09-08 12:40:00 +0000419 s.env = env;
bellard9307c4c2004-04-04 12:57:25 +0000420 monitor_disas_is_physical = is_physical;
Blue Swirlf4359b92012-09-08 12:40:00 +0000421 s.info.read_memory_func = monitor_read_memory;
422 s.info.print_address_func = generic_print_target_address;
bellard9307c4c2004-04-04 12:57:25 +0000423
Blue Swirlf4359b92012-09-08 12:40:00 +0000424 s.info.buffer_vma = pc;
bellard9307c4c2004-04-04 12:57:25 +0000425
426#ifdef TARGET_WORDS_BIGENDIAN
Blue Swirlf4359b92012-09-08 12:40:00 +0000427 s.info.endian = BFD_ENDIAN_BIG;
bellard9307c4c2004-04-04 12:57:25 +0000428#else
Blue Swirlf4359b92012-09-08 12:40:00 +0000429 s.info.endian = BFD_ENDIAN_LITTLE;
bellard9307c4c2004-04-04 12:57:25 +0000430#endif
431#if defined(TARGET_I386)
Blue Swirlf4359b92012-09-08 12:40:00 +0000432 if (flags == 2) {
433 s.info.mach = bfd_mach_x86_64;
434 } else if (flags == 1) {
435 s.info.mach = bfd_mach_i386_i8086;
436 } else {
437 s.info.mach = bfd_mach_i386_i386;
438 }
bellard9307c4c2004-04-04 12:57:25 +0000439 print_insn = print_insn_i386;
440#elif defined(TARGET_ARM)
441 print_insn = print_insn_arm;
thscbd669d2007-12-25 00:26:36 +0000442#elif defined(TARGET_ALPHA)
443 print_insn = print_insn_alpha;
bellard9307c4c2004-04-04 12:57:25 +0000444#elif defined(TARGET_SPARC)
445 print_insn = print_insn_sparc;
blueswir1682c4f12007-04-09 15:14:57 +0000446#ifdef TARGET_SPARC64
Blue Swirlf4359b92012-09-08 12:40:00 +0000447 s.info.mach = bfd_mach_sparc_v9b;
blueswir1682c4f12007-04-09 15:14:57 +0000448#endif
bellard9307c4c2004-04-04 12:57:25 +0000449#elif defined(TARGET_PPC)
bellarda2458622005-07-23 22:39:53 +0000450#ifdef TARGET_PPC64
Blue Swirlf4359b92012-09-08 12:40:00 +0000451 s.info.mach = bfd_mach_ppc64;
bellarda2458622005-07-23 22:39:53 +0000452#else
Blue Swirlf4359b92012-09-08 12:40:00 +0000453 s.info.mach = bfd_mach_ppc;
bellarda2458622005-07-23 22:39:53 +0000454#endif
bellard9307c4c2004-04-04 12:57:25 +0000455 print_insn = print_insn_ppc;
pbrooke6e59062006-10-22 00:18:54 +0000456#elif defined(TARGET_M68K)
457 print_insn = print_insn_m68k;
bellard6af0bf92005-07-02 14:58:51 +0000458#elif defined(TARGET_MIPS)
bellard76b30302005-12-17 01:10:04 +0000459#ifdef TARGET_WORDS_BIGENDIAN
bellard6af0bf92005-07-02 14:58:51 +0000460 print_insn = print_insn_big_mips;
bellard76b30302005-12-17 01:10:04 +0000461#else
462 print_insn = print_insn_little_mips;
463#endif
Magnus Dammb4e1f072009-11-13 18:54:22 +0900464#elif defined(TARGET_SH4)
Blue Swirlf4359b92012-09-08 12:40:00 +0000465 s.info.mach = bfd_mach_sh4;
Magnus Dammb4e1f072009-11-13 18:54:22 +0900466 print_insn = print_insn_sh;
Ulrich Hechtdb500602011-03-29 15:29:32 +0200467#elif defined(TARGET_S390X)
Blue Swirlf4359b92012-09-08 12:40:00 +0000468 s.info.mach = bfd_mach_s390_64;
Ulrich Hechtdb500602011-03-29 15:29:32 +0200469 print_insn = print_insn_s390;
Anthony Greenbd86a882013-03-18 15:49:23 -0400470#elif defined(TARGET_MOXIE)
471 s.info.mach = bfd_arch_moxie;
472 print_insn = print_insn_moxie;
Michael Walle79368f42012-03-31 19:54:20 +0200473#elif defined(TARGET_LM32)
Blue Swirlf4359b92012-09-08 12:40:00 +0000474 s.info.mach = bfd_mach_lm32;
Michael Walle79368f42012-03-31 19:54:20 +0200475 print_insn = print_insn_lm32;
bellard9307c4c2004-04-04 12:57:25 +0000476#else
aliguori376253e2009-03-05 23:01:23 +0000477 monitor_printf(mon, "0x" TARGET_FMT_lx
478 ": Asm output not supported on this arch\n", pc);
bellard9307c4c2004-04-04 12:57:25 +0000479 return;
480#endif
481
482 for(i = 0; i < nb_insn; i++) {
aliguori376253e2009-03-05 23:01:23 +0000483 monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc);
Blue Swirlf4359b92012-09-08 12:40:00 +0000484 count = print_insn(pc, &s.info);
aliguori376253e2009-03-05 23:01:23 +0000485 monitor_printf(mon, "\n");
bellard9307c4c2004-04-04 12:57:25 +0000486 if (count < 0)
487 break;
488 pc += count;
489 }
490}
491#endif