Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 1 | /* |
| 2 | * PowerPC emulation helpers for QEMU. |
| 3 | * |
| 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
Peter Maydell | 0d75590 | 2016-01-26 18:16:58 +0000 | [diff] [blame] | 19 | #include "qemu/osdep.h" |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 20 | #include "cpu.h" |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 21 | #include "exec/helper-proto.h" |
Benjamin Herrenschmidt | a13f0a9 | 2016-07-27 16:56:35 +1000 | [diff] [blame] | 22 | #include "exec/exec-all.h" |
Paolo Bonzini | 63c9155 | 2016-03-15 13:18:37 +0100 | [diff] [blame] | 23 | #include "qemu/log.h" |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 24 | |
| 25 | /*****************************************************************************/ |
| 26 | /* SPR accesses */ |
| 27 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 28 | target_ulong helper_load_tbl(CPUPPCState *env) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 29 | { |
| 30 | return (target_ulong)cpu_ppc_load_tbl(env); |
| 31 | } |
| 32 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 33 | target_ulong helper_load_tbu(CPUPPCState *env) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 34 | { |
| 35 | return cpu_ppc_load_tbu(env); |
| 36 | } |
| 37 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 38 | target_ulong helper_load_atbl(CPUPPCState *env) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 39 | { |
| 40 | return (target_ulong)cpu_ppc_load_atbl(env); |
| 41 | } |
| 42 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 43 | target_ulong helper_load_atbu(CPUPPCState *env) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 44 | { |
| 45 | return cpu_ppc_load_atbu(env); |
| 46 | } |
| 47 | |
| 48 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 49 | target_ulong helper_load_purr(CPUPPCState *env) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 50 | { |
| 51 | return (target_ulong)cpu_ppc_load_purr(env); |
| 52 | } |
| 53 | #endif |
| 54 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 55 | target_ulong helper_load_601_rtcl(CPUPPCState *env) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 56 | { |
| 57 | return cpu_ppc601_load_rtcl(env); |
| 58 | } |
| 59 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 60 | target_ulong helper_load_601_rtcu(CPUPPCState *env) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 61 | { |
| 62 | return cpu_ppc601_load_rtcu(env); |
| 63 | } |
| 64 | |
| 65 | #if !defined(CONFIG_USER_ONLY) |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 66 | void helper_store_tbl(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 67 | { |
| 68 | cpu_ppc_store_tbl(env, val); |
| 69 | } |
| 70 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 71 | void helper_store_tbu(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 72 | { |
| 73 | cpu_ppc_store_tbu(env, val); |
| 74 | } |
| 75 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 76 | void helper_store_atbl(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 77 | { |
| 78 | cpu_ppc_store_atbl(env, val); |
| 79 | } |
| 80 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 81 | void helper_store_atbu(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 82 | { |
| 83 | cpu_ppc_store_atbu(env, val); |
| 84 | } |
| 85 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 86 | void helper_store_601_rtcl(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 87 | { |
| 88 | cpu_ppc601_store_rtcl(env, val); |
| 89 | } |
| 90 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 91 | void helper_store_601_rtcu(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 92 | { |
| 93 | cpu_ppc601_store_rtcu(env, val); |
| 94 | } |
| 95 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 96 | target_ulong helper_load_decr(CPUPPCState *env) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 97 | { |
| 98 | return cpu_ppc_load_decr(env); |
| 99 | } |
| 100 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 101 | void helper_store_decr(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 102 | { |
| 103 | cpu_ppc_store_decr(env, val); |
| 104 | } |
| 105 | |
Benjamin Herrenschmidt | 4b236b6 | 2016-06-27 08:55:19 +0200 | [diff] [blame] | 106 | target_ulong helper_load_hdecr(CPUPPCState *env) |
| 107 | { |
| 108 | return cpu_ppc_load_hdecr(env); |
| 109 | } |
| 110 | |
| 111 | void helper_store_hdecr(CPUPPCState *env, target_ulong val) |
| 112 | { |
| 113 | cpu_ppc_store_hdecr(env, val); |
| 114 | } |
| 115 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 116 | target_ulong helper_load_40x_pit(CPUPPCState *env) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 117 | { |
| 118 | return load_40x_pit(env); |
| 119 | } |
| 120 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 121 | void helper_store_40x_pit(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 122 | { |
| 123 | store_40x_pit(env, val); |
| 124 | } |
| 125 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 126 | void helper_store_booke_tcr(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 127 | { |
| 128 | store_booke_tcr(env, val); |
| 129 | } |
| 130 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 131 | void helper_store_booke_tsr(CPUPPCState *env, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 132 | { |
| 133 | store_booke_tsr(env, val); |
| 134 | } |
| 135 | #endif |
| 136 | |
| 137 | /*****************************************************************************/ |
| 138 | /* Embedded PowerPC specific helpers */ |
| 139 | |
| 140 | /* XXX: to be improved to check access rights when in user-mode */ |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 141 | target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 142 | { |
| 143 | uint32_t val = 0; |
| 144 | |
| 145 | if (unlikely(env->dcr_env == NULL)) { |
Paolo Bonzini | 48880da | 2015-11-13 13:34:23 +0100 | [diff] [blame] | 146 | qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); |
Benjamin Herrenschmidt | a13f0a9 | 2016-07-27 16:56:35 +1000 | [diff] [blame] | 147 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 148 | POWERPC_EXCP_INVAL | |
| 149 | POWERPC_EXCP_INVAL_INVAL, GETPC()); |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 150 | } else if (unlikely(ppc_dcr_read(env->dcr_env, |
| 151 | (uint32_t)dcrn, &val) != 0)) { |
Paolo Bonzini | 48880da | 2015-11-13 13:34:23 +0100 | [diff] [blame] | 152 | qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n", |
| 153 | (uint32_t)dcrn, (uint32_t)dcrn); |
Benjamin Herrenschmidt | a13f0a9 | 2016-07-27 16:56:35 +1000 | [diff] [blame] | 154 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 155 | POWERPC_EXCP_INVAL | |
| 156 | POWERPC_EXCP_PRIV_REG, GETPC()); |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 157 | } |
| 158 | return val; |
| 159 | } |
| 160 | |
Blue Swirl | d0f1562 | 2012-05-30 04:23:36 +0000 | [diff] [blame] | 161 | void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val) |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 162 | { |
| 163 | if (unlikely(env->dcr_env == NULL)) { |
Paolo Bonzini | 48880da | 2015-11-13 13:34:23 +0100 | [diff] [blame] | 164 | qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); |
Benjamin Herrenschmidt | a13f0a9 | 2016-07-27 16:56:35 +1000 | [diff] [blame] | 165 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 166 | POWERPC_EXCP_INVAL | |
| 167 | POWERPC_EXCP_INVAL_INVAL, GETPC()); |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 168 | } else if (unlikely(ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, |
| 169 | (uint32_t)val) != 0)) { |
Paolo Bonzini | 48880da | 2015-11-13 13:34:23 +0100 | [diff] [blame] | 170 | qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n", |
| 171 | (uint32_t)dcrn, (uint32_t)dcrn); |
Benjamin Herrenschmidt | a13f0a9 | 2016-07-27 16:56:35 +1000 | [diff] [blame] | 172 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 173 | POWERPC_EXCP_INVAL | |
| 174 | POWERPC_EXCP_PRIV_REG, GETPC()); |
Blue Swirl | 6de673d | 2012-05-30 04:23:35 +0000 | [diff] [blame] | 175 | } |
| 176 | } |