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Blue Swirl6de673d2012-05-30 04:23:35 +00001/*
2 * PowerPC emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
Peter Maydell0d755902016-01-26 18:16:58 +000019#include "qemu/osdep.h"
Blue Swirl6de673d2012-05-30 04:23:35 +000020#include "cpu.h"
Richard Henderson2ef61752014-04-07 22:31:41 -070021#include "exec/helper-proto.h"
Benjamin Herrenschmidta13f0a92016-07-27 16:56:35 +100022#include "exec/exec-all.h"
Paolo Bonzini63c91552016-03-15 13:18:37 +010023#include "qemu/log.h"
Blue Swirl6de673d2012-05-30 04:23:35 +000024
25/*****************************************************************************/
26/* SPR accesses */
27
Blue Swirld0f15622012-05-30 04:23:36 +000028target_ulong helper_load_tbl(CPUPPCState *env)
Blue Swirl6de673d2012-05-30 04:23:35 +000029{
30 return (target_ulong)cpu_ppc_load_tbl(env);
31}
32
Blue Swirld0f15622012-05-30 04:23:36 +000033target_ulong helper_load_tbu(CPUPPCState *env)
Blue Swirl6de673d2012-05-30 04:23:35 +000034{
35 return cpu_ppc_load_tbu(env);
36}
37
Blue Swirld0f15622012-05-30 04:23:36 +000038target_ulong helper_load_atbl(CPUPPCState *env)
Blue Swirl6de673d2012-05-30 04:23:35 +000039{
40 return (target_ulong)cpu_ppc_load_atbl(env);
41}
42
Blue Swirld0f15622012-05-30 04:23:36 +000043target_ulong helper_load_atbu(CPUPPCState *env)
Blue Swirl6de673d2012-05-30 04:23:35 +000044{
45 return cpu_ppc_load_atbu(env);
46}
47
48#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
Blue Swirld0f15622012-05-30 04:23:36 +000049target_ulong helper_load_purr(CPUPPCState *env)
Blue Swirl6de673d2012-05-30 04:23:35 +000050{
51 return (target_ulong)cpu_ppc_load_purr(env);
52}
53#endif
54
Blue Swirld0f15622012-05-30 04:23:36 +000055target_ulong helper_load_601_rtcl(CPUPPCState *env)
Blue Swirl6de673d2012-05-30 04:23:35 +000056{
57 return cpu_ppc601_load_rtcl(env);
58}
59
Blue Swirld0f15622012-05-30 04:23:36 +000060target_ulong helper_load_601_rtcu(CPUPPCState *env)
Blue Swirl6de673d2012-05-30 04:23:35 +000061{
62 return cpu_ppc601_load_rtcu(env);
63}
64
65#if !defined(CONFIG_USER_ONLY)
Blue Swirld0f15622012-05-30 04:23:36 +000066void helper_store_tbl(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +000067{
68 cpu_ppc_store_tbl(env, val);
69}
70
Blue Swirld0f15622012-05-30 04:23:36 +000071void helper_store_tbu(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +000072{
73 cpu_ppc_store_tbu(env, val);
74}
75
Blue Swirld0f15622012-05-30 04:23:36 +000076void helper_store_atbl(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +000077{
78 cpu_ppc_store_atbl(env, val);
79}
80
Blue Swirld0f15622012-05-30 04:23:36 +000081void helper_store_atbu(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +000082{
83 cpu_ppc_store_atbu(env, val);
84}
85
Blue Swirld0f15622012-05-30 04:23:36 +000086void helper_store_601_rtcl(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +000087{
88 cpu_ppc601_store_rtcl(env, val);
89}
90
Blue Swirld0f15622012-05-30 04:23:36 +000091void helper_store_601_rtcu(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +000092{
93 cpu_ppc601_store_rtcu(env, val);
94}
95
Blue Swirld0f15622012-05-30 04:23:36 +000096target_ulong helper_load_decr(CPUPPCState *env)
Blue Swirl6de673d2012-05-30 04:23:35 +000097{
98 return cpu_ppc_load_decr(env);
99}
100
Blue Swirld0f15622012-05-30 04:23:36 +0000101void helper_store_decr(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +0000102{
103 cpu_ppc_store_decr(env, val);
104}
105
Benjamin Herrenschmidt4b236b62016-06-27 08:55:19 +0200106target_ulong helper_load_hdecr(CPUPPCState *env)
107{
108 return cpu_ppc_load_hdecr(env);
109}
110
111void helper_store_hdecr(CPUPPCState *env, target_ulong val)
112{
113 cpu_ppc_store_hdecr(env, val);
114}
115
Blue Swirld0f15622012-05-30 04:23:36 +0000116target_ulong helper_load_40x_pit(CPUPPCState *env)
Blue Swirl6de673d2012-05-30 04:23:35 +0000117{
118 return load_40x_pit(env);
119}
120
Blue Swirld0f15622012-05-30 04:23:36 +0000121void helper_store_40x_pit(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +0000122{
123 store_40x_pit(env, val);
124}
125
Blue Swirld0f15622012-05-30 04:23:36 +0000126void helper_store_booke_tcr(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +0000127{
128 store_booke_tcr(env, val);
129}
130
Blue Swirld0f15622012-05-30 04:23:36 +0000131void helper_store_booke_tsr(CPUPPCState *env, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +0000132{
133 store_booke_tsr(env, val);
134}
135#endif
136
137/*****************************************************************************/
138/* Embedded PowerPC specific helpers */
139
140/* XXX: to be improved to check access rights when in user-mode */
Blue Swirld0f15622012-05-30 04:23:36 +0000141target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn)
Blue Swirl6de673d2012-05-30 04:23:35 +0000142{
143 uint32_t val = 0;
144
145 if (unlikely(env->dcr_env == NULL)) {
Paolo Bonzini48880da2015-11-13 13:34:23 +0100146 qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n");
Benjamin Herrenschmidta13f0a92016-07-27 16:56:35 +1000147 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
148 POWERPC_EXCP_INVAL |
149 POWERPC_EXCP_INVAL_INVAL, GETPC());
Blue Swirl6de673d2012-05-30 04:23:35 +0000150 } else if (unlikely(ppc_dcr_read(env->dcr_env,
151 (uint32_t)dcrn, &val) != 0)) {
Paolo Bonzini48880da2015-11-13 13:34:23 +0100152 qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n",
153 (uint32_t)dcrn, (uint32_t)dcrn);
Benjamin Herrenschmidta13f0a92016-07-27 16:56:35 +1000154 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
155 POWERPC_EXCP_INVAL |
156 POWERPC_EXCP_PRIV_REG, GETPC());
Blue Swirl6de673d2012-05-30 04:23:35 +0000157 }
158 return val;
159}
160
Blue Swirld0f15622012-05-30 04:23:36 +0000161void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val)
Blue Swirl6de673d2012-05-30 04:23:35 +0000162{
163 if (unlikely(env->dcr_env == NULL)) {
Paolo Bonzini48880da2015-11-13 13:34:23 +0100164 qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n");
Benjamin Herrenschmidta13f0a92016-07-27 16:56:35 +1000165 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
166 POWERPC_EXCP_INVAL |
167 POWERPC_EXCP_INVAL_INVAL, GETPC());
Blue Swirl6de673d2012-05-30 04:23:35 +0000168 } else if (unlikely(ppc_dcr_write(env->dcr_env, (uint32_t)dcrn,
169 (uint32_t)val) != 0)) {
Paolo Bonzini48880da2015-11-13 13:34:23 +0100170 qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n",
171 (uint32_t)dcrn, (uint32_t)dcrn);
Benjamin Herrenschmidta13f0a92016-07-27 16:56:35 +1000172 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
173 POWERPC_EXCP_INVAL |
174 POWERPC_EXCP_PRIV_REG, GETPC());
Blue Swirl6de673d2012-05-30 04:23:35 +0000175 }
176}