balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Intel XScale PXA255/270 processor support. |
| 3 | * |
| 4 | * Copyright (c) 2006 Openedhand Ltd. |
| 5 | * Written by Andrzej Zaborowski <balrog@zabor.org> |
| 6 | * |
balrog | 3efda49 | 2007-10-29 10:34:01 +0000 | [diff] [blame] | 7 | * This code is licenced under the GNU GPL v2. |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 8 | */ |
| 9 | #ifndef PXA_H |
| 10 | # define PXA_H "pxa.h" |
| 11 | |
| 12 | /* Interrupt numbers */ |
| 13 | # define PXA2XX_PIC_SSP3 0 |
| 14 | # define PXA2XX_PIC_USBH2 2 |
| 15 | # define PXA2XX_PIC_USBH1 3 |
balrog | 31b87f2 | 2007-12-16 12:13:51 +0000 | [diff] [blame] | 16 | # define PXA2XX_PIC_KEYPAD 4 |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 17 | # define PXA2XX_PIC_PWRI2C 6 |
| 18 | # define PXA25X_PIC_HWUART 7 |
| 19 | # define PXA27X_PIC_OST_4_11 7 |
| 20 | # define PXA2XX_PIC_GPIO_0 8 |
| 21 | # define PXA2XX_PIC_GPIO_1 9 |
| 22 | # define PXA2XX_PIC_GPIO_X 10 |
| 23 | # define PXA2XX_PIC_I2S 13 |
| 24 | # define PXA26X_PIC_ASSP 15 |
| 25 | # define PXA25X_PIC_NSSP 16 |
| 26 | # define PXA27X_PIC_SSP2 16 |
| 27 | # define PXA2XX_PIC_LCD 17 |
| 28 | # define PXA2XX_PIC_I2C 18 |
| 29 | # define PXA2XX_PIC_ICP 19 |
| 30 | # define PXA2XX_PIC_STUART 20 |
| 31 | # define PXA2XX_PIC_BTUART 21 |
| 32 | # define PXA2XX_PIC_FFUART 22 |
| 33 | # define PXA2XX_PIC_MMC 23 |
| 34 | # define PXA2XX_PIC_SSP 24 |
| 35 | # define PXA2XX_PIC_DMA 25 |
| 36 | # define PXA2XX_PIC_OST_0 26 |
| 37 | # define PXA2XX_PIC_RTC1HZ 30 |
| 38 | # define PXA2XX_PIC_RTCALARM 31 |
| 39 | |
| 40 | /* DMA requests */ |
| 41 | # define PXA2XX_RX_RQ_I2S 2 |
| 42 | # define PXA2XX_TX_RQ_I2S 3 |
| 43 | # define PXA2XX_RX_RQ_BTUART 4 |
| 44 | # define PXA2XX_TX_RQ_BTUART 5 |
| 45 | # define PXA2XX_RX_RQ_FFUART 6 |
| 46 | # define PXA2XX_TX_RQ_FFUART 7 |
| 47 | # define PXA2XX_RX_RQ_SSP1 13 |
| 48 | # define PXA2XX_TX_RQ_SSP1 14 |
| 49 | # define PXA2XX_RX_RQ_SSP2 15 |
| 50 | # define PXA2XX_TX_RQ_SSP2 16 |
| 51 | # define PXA2XX_RX_RQ_ICP 17 |
| 52 | # define PXA2XX_TX_RQ_ICP 18 |
| 53 | # define PXA2XX_RX_RQ_STUART 19 |
| 54 | # define PXA2XX_TX_RQ_STUART 20 |
| 55 | # define PXA2XX_RX_RQ_MMCI 21 |
| 56 | # define PXA2XX_TX_RQ_MMCI 22 |
| 57 | # define PXA2XX_USB_RQ(x) ((x) + 24) |
| 58 | # define PXA2XX_RX_RQ_SSP3 66 |
| 59 | # define PXA2XX_TX_RQ_SSP3 67 |
| 60 | |
balrog | d95b2f8 | 2007-05-08 19:03:12 +0000 | [diff] [blame] | 61 | # define PXA2XX_SDRAM_BASE 0xa0000000 |
| 62 | # define PXA2XX_INTERNAL_BASE 0x5c000000 |
balrog | a07dec2 | 2007-05-12 09:19:36 +0000 | [diff] [blame] | 63 | # define PXA2XX_INTERNAL_SIZE 0x40000 |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 64 | |
| 65 | /* pxa2xx_pic.c */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 66 | qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 67 | |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 68 | /* pxa2xx_timer.c */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 69 | void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs); |
| 70 | void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 71 | |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 72 | /* pxa2xx_gpio.c */ |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 73 | typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 74 | PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base, |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 75 | CPUState *env, qemu_irq *pic, int lines); |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 76 | qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s); |
| 77 | void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s, |
balrog | 38641a5 | 2007-11-17 14:07:13 +0000 | [diff] [blame] | 78 | int line, qemu_irq handler); |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 79 | void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 80 | |
| 81 | /* pxa2xx_dma.c */ |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 82 | typedef struct PXA2xxDMAState PXA2xxDMAState; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 83 | PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 84 | qemu_irq irq); |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 85 | PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 86 | qemu_irq irq); |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 87 | void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 88 | |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 89 | /* pxa2xx_lcd.c */ |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 90 | typedef struct PXA2xxLCDState PXA2xxLCDState; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 91 | PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, |
aliguori | 3023f33 | 2009-01-16 19:04:14 +0000 | [diff] [blame] | 92 | qemu_irq irq); |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 93 | void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 94 | void pxa2xx_lcdc_oritentation(void *opaque, int angle); |
| 95 | |
| 96 | /* pxa2xx_mmci.c */ |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 97 | typedef struct PXA2xxMMCIState PXA2xxMMCIState; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 98 | PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 99 | BlockDriverState *bd, qemu_irq irq, void *dma); |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 100 | void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, |
balrog | 02ce600 | 2007-11-17 14:34:44 +0000 | [diff] [blame] | 101 | qemu_irq coverswitch); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 102 | |
| 103 | /* pxa2xx_pcmcia.c */ |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 104 | typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 105 | PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base); |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 106 | int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); |
balrog | a171fe3 | 2007-04-30 01:48:07 +0000 | [diff] [blame] | 107 | int pxa2xx_pcmcia_dettach(void *opaque); |
| 108 | void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); |
| 109 | |
balrog | 31b87f2 | 2007-12-16 12:13:51 +0000 | [diff] [blame] | 110 | /* pxa2xx_keypad.c */ |
| 111 | struct keymap { |
| 112 | int column; |
| 113 | int row; |
| 114 | }; |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 115 | typedef struct PXA2xxKeyPadState PXA2xxKeyPadState; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 116 | PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base, |
balrog | 31b87f2 | 2007-12-16 12:13:51 +0000 | [diff] [blame] | 117 | qemu_irq irq); |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 118 | void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map, |
balrog | 31b87f2 | 2007-12-16 12:13:51 +0000 | [diff] [blame] | 119 | int size); |
| 120 | |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 121 | /* pxa2xx.c */ |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 122 | typedef struct PXA2xxI2CState PXA2xxI2CState; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 123 | PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base, |
balrog | 2a16392 | 2007-05-28 11:26:15 +0000 | [diff] [blame] | 124 | qemu_irq irq, uint32_t page_size); |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 125 | i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s); |
balrog | 3f58226 | 2007-05-23 21:47:51 +0000 | [diff] [blame] | 126 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 127 | typedef struct PXA2xxI2SState PXA2xxI2SState; |
| 128 | typedef struct PXA2xxFIrState PXA2xxFIrState; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 129 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 130 | typedef struct { |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 131 | CPUState *env; |
| 132 | qemu_irq *pic; |
balrog | 38641a5 | 2007-11-17 14:07:13 +0000 | [diff] [blame] | 133 | qemu_irq reset; |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 134 | PXA2xxDMAState *dma; |
| 135 | PXA2xxGPIOInfo *gpio; |
| 136 | PXA2xxLCDState *lcd; |
Paul Brook | a984a69 | 2009-05-14 22:35:09 +0100 | [diff] [blame] | 137 | SSIBus **ssp; |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 138 | PXA2xxI2CState *i2c[2]; |
| 139 | PXA2xxMMCIState *mmc; |
| 140 | PXA2xxPCMCIAState *pcmcia[2]; |
| 141 | PXA2xxI2SState *i2s; |
| 142 | PXA2xxFIrState *fir; |
| 143 | PXA2xxKeyPadState *kp; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 144 | |
| 145 | /* Power management */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 146 | target_phys_addr_t pm_base; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 147 | uint32_t pm_regs[0x40]; |
| 148 | |
| 149 | /* Clock management */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 150 | target_phys_addr_t cm_base; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 151 | uint32_t cm_regs[4]; |
| 152 | uint32_t clkcfg; |
| 153 | |
| 154 | /* Memory management */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 155 | target_phys_addr_t mm_base; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 156 | uint32_t mm_regs[0x1a]; |
| 157 | |
| 158 | /* Performance monitoring */ |
| 159 | uint32_t pmnc; |
| 160 | |
| 161 | /* Real-Time clock */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 162 | target_phys_addr_t rtc_base; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 163 | uint32_t rttr; |
| 164 | uint32_t rtsr; |
| 165 | uint32_t rtar; |
| 166 | uint32_t rdar1; |
| 167 | uint32_t rdar2; |
| 168 | uint32_t ryar1; |
| 169 | uint32_t ryar2; |
| 170 | uint32_t swar1; |
| 171 | uint32_t swar2; |
| 172 | uint32_t piar; |
| 173 | uint32_t last_rcnr; |
| 174 | uint32_t last_rdcr; |
| 175 | uint32_t last_rycr; |
| 176 | uint32_t last_swcr; |
| 177 | uint32_t last_rtcpicr; |
| 178 | int64_t last_hz; |
| 179 | int64_t last_sw; |
| 180 | int64_t last_pi; |
| 181 | QEMUTimer *rtc_hz; |
| 182 | QEMUTimer *rtc_rdal1; |
| 183 | QEMUTimer *rtc_rdal2; |
| 184 | QEMUTimer *rtc_swal1; |
| 185 | QEMUTimer *rtc_swal2; |
| 186 | QEMUTimer *rtc_pi; |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 187 | } PXA2xxState; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 188 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 189 | struct PXA2xxI2SState { |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 190 | qemu_irq irq; |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 191 | PXA2xxDMAState *dma; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 192 | void (*data_req)(void *, int, int); |
| 193 | |
| 194 | uint32_t control[2]; |
| 195 | uint32_t status; |
| 196 | uint32_t mask; |
| 197 | uint32_t clk; |
| 198 | |
| 199 | int enable; |
| 200 | int rx_len; |
| 201 | int tx_len; |
| 202 | void (*codec_out)(void *, uint32_t); |
| 203 | uint32_t (*codec_in)(void *); |
| 204 | void *opaque; |
| 205 | |
| 206 | int fifo_len; |
| 207 | uint32_t fifo[16]; |
| 208 | }; |
| 209 | |
| 210 | # define PA_FMT "0x%08lx" |
bellard | 444ce24 | 2007-11-11 19:47:59 +0000 | [diff] [blame] | 211 | # define REG_FMT "0x" TARGET_FMT_plx |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 212 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 213 | PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision); |
| 214 | PXA2xxState *pxa255_init(unsigned int sdram_size); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 215 | |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 216 | #endif /* PXA_H */ |