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balrogc1713132007-04-30 01:26:42 +00001/*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
balrog3efda492007-10-29 10:34:01 +00007 * This code is licenced under the GNU GPL v2.
balrogc1713132007-04-30 01:26:42 +00008 */
9#ifndef PXA_H
10# define PXA_H "pxa.h"
11
12/* Interrupt numbers */
13# define PXA2XX_PIC_SSP3 0
14# define PXA2XX_PIC_USBH2 2
15# define PXA2XX_PIC_USBH1 3
balrog31b87f22007-12-16 12:13:51 +000016# define PXA2XX_PIC_KEYPAD 4
balrogc1713132007-04-30 01:26:42 +000017# define PXA2XX_PIC_PWRI2C 6
18# define PXA25X_PIC_HWUART 7
19# define PXA27X_PIC_OST_4_11 7
20# define PXA2XX_PIC_GPIO_0 8
21# define PXA2XX_PIC_GPIO_1 9
22# define PXA2XX_PIC_GPIO_X 10
23# define PXA2XX_PIC_I2S 13
24# define PXA26X_PIC_ASSP 15
25# define PXA25X_PIC_NSSP 16
26# define PXA27X_PIC_SSP2 16
27# define PXA2XX_PIC_LCD 17
28# define PXA2XX_PIC_I2C 18
29# define PXA2XX_PIC_ICP 19
30# define PXA2XX_PIC_STUART 20
31# define PXA2XX_PIC_BTUART 21
32# define PXA2XX_PIC_FFUART 22
33# define PXA2XX_PIC_MMC 23
34# define PXA2XX_PIC_SSP 24
35# define PXA2XX_PIC_DMA 25
36# define PXA2XX_PIC_OST_0 26
37# define PXA2XX_PIC_RTC1HZ 30
38# define PXA2XX_PIC_RTCALARM 31
39
40/* DMA requests */
41# define PXA2XX_RX_RQ_I2S 2
42# define PXA2XX_TX_RQ_I2S 3
43# define PXA2XX_RX_RQ_BTUART 4
44# define PXA2XX_TX_RQ_BTUART 5
45# define PXA2XX_RX_RQ_FFUART 6
46# define PXA2XX_TX_RQ_FFUART 7
47# define PXA2XX_RX_RQ_SSP1 13
48# define PXA2XX_TX_RQ_SSP1 14
49# define PXA2XX_RX_RQ_SSP2 15
50# define PXA2XX_TX_RQ_SSP2 16
51# define PXA2XX_RX_RQ_ICP 17
52# define PXA2XX_TX_RQ_ICP 18
53# define PXA2XX_RX_RQ_STUART 19
54# define PXA2XX_TX_RQ_STUART 20
55# define PXA2XX_RX_RQ_MMCI 21
56# define PXA2XX_TX_RQ_MMCI 22
57# define PXA2XX_USB_RQ(x) ((x) + 24)
58# define PXA2XX_RX_RQ_SSP3 66
59# define PXA2XX_TX_RQ_SSP3 67
60
balrogd95b2f82007-05-08 19:03:12 +000061# define PXA2XX_SDRAM_BASE 0xa0000000
62# define PXA2XX_INTERNAL_BASE 0x5c000000
balroga07dec22007-05-12 09:19:36 +000063# define PXA2XX_INTERNAL_SIZE 0x40000
balrogc1713132007-04-30 01:26:42 +000064
65/* pxa2xx_pic.c */
Anthony Liguoric227f092009-10-01 16:12:16 -050066qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
balrogc1713132007-04-30 01:26:42 +000067
balroga171fe32007-04-30 01:48:07 +000068/* pxa2xx_timer.c */
Anthony Liguoric227f092009-10-01 16:12:16 -050069void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
70void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
balroga171fe32007-04-30 01:48:07 +000071
balrogc1713132007-04-30 01:26:42 +000072/* pxa2xx_gpio.c */
Paul Brookbc24a222009-05-10 01:44:56 +010073typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
Anthony Liguoric227f092009-10-01 16:12:16 -050074PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
balrogc1713132007-04-30 01:26:42 +000075 CPUState *env, qemu_irq *pic, int lines);
Paul Brookbc24a222009-05-10 01:44:56 +010076qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s);
77void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s,
balrog38641a52007-11-17 14:07:13 +000078 int line, qemu_irq handler);
Paul Brookbc24a222009-05-10 01:44:56 +010079void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler);
balrogc1713132007-04-30 01:26:42 +000080
81/* pxa2xx_dma.c */
Paul Brookbc24a222009-05-10 01:44:56 +010082typedef struct PXA2xxDMAState PXA2xxDMAState;
Anthony Liguoric227f092009-10-01 16:12:16 -050083PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
balrogc1713132007-04-30 01:26:42 +000084 qemu_irq irq);
Anthony Liguoric227f092009-10-01 16:12:16 -050085PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
balrogc1713132007-04-30 01:26:42 +000086 qemu_irq irq);
Paul Brookbc24a222009-05-10 01:44:56 +010087void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);
balrogc1713132007-04-30 01:26:42 +000088
balroga171fe32007-04-30 01:48:07 +000089/* pxa2xx_lcd.c */
Paul Brookbc24a222009-05-10 01:44:56 +010090typedef struct PXA2xxLCDState PXA2xxLCDState;
Anthony Liguoric227f092009-10-01 16:12:16 -050091PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
aliguori3023f332009-01-16 19:04:14 +000092 qemu_irq irq);
Paul Brookbc24a222009-05-10 01:44:56 +010093void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
balroga171fe32007-04-30 01:48:07 +000094void pxa2xx_lcdc_oritentation(void *opaque, int angle);
95
96/* pxa2xx_mmci.c */
Paul Brookbc24a222009-05-10 01:44:56 +010097typedef struct PXA2xxMMCIState PXA2xxMMCIState;
Anthony Liguoric227f092009-10-01 16:12:16 -050098PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
pbrook87ecb682007-11-17 17:14:51 +000099 BlockDriverState *bd, qemu_irq irq, void *dma);
Paul Brookbc24a222009-05-10 01:44:56 +0100100void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
balrog02ce6002007-11-17 14:34:44 +0000101 qemu_irq coverswitch);
balroga171fe32007-04-30 01:48:07 +0000102
103/* pxa2xx_pcmcia.c */
Paul Brookbc24a222009-05-10 01:44:56 +0100104typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
Anthony Liguoric227f092009-10-01 16:12:16 -0500105PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
Paul Brookbc24a222009-05-10 01:44:56 +0100106int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
balroga171fe32007-04-30 01:48:07 +0000107int pxa2xx_pcmcia_dettach(void *opaque);
108void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
109
balrog31b87f22007-12-16 12:13:51 +0000110/* pxa2xx_keypad.c */
111struct keymap {
112 int column;
113 int row;
114};
Paul Brookbc24a222009-05-10 01:44:56 +0100115typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
Anthony Liguoric227f092009-10-01 16:12:16 -0500116PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
balrog31b87f22007-12-16 12:13:51 +0000117 qemu_irq irq);
Paul Brookbc24a222009-05-10 01:44:56 +0100118void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
balrog31b87f22007-12-16 12:13:51 +0000119 int size);
120
balrogc1713132007-04-30 01:26:42 +0000121/* pxa2xx.c */
Paul Brookbc24a222009-05-10 01:44:56 +0100122typedef struct PXA2xxI2CState PXA2xxI2CState;
Anthony Liguoric227f092009-10-01 16:12:16 -0500123PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
balrog2a163922007-05-28 11:26:15 +0000124 qemu_irq irq, uint32_t page_size);
Paul Brookbc24a222009-05-10 01:44:56 +0100125i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
balrog3f582262007-05-23 21:47:51 +0000126
Paul Brookbc24a222009-05-10 01:44:56 +0100127typedef struct PXA2xxI2SState PXA2xxI2SState;
128typedef struct PXA2xxFIrState PXA2xxFIrState;
balrogc1713132007-04-30 01:26:42 +0000129
Paul Brookbc24a222009-05-10 01:44:56 +0100130typedef struct {
balrogc1713132007-04-30 01:26:42 +0000131 CPUState *env;
132 qemu_irq *pic;
balrog38641a52007-11-17 14:07:13 +0000133 qemu_irq reset;
Paul Brookbc24a222009-05-10 01:44:56 +0100134 PXA2xxDMAState *dma;
135 PXA2xxGPIOInfo *gpio;
136 PXA2xxLCDState *lcd;
Paul Brooka984a692009-05-14 22:35:09 +0100137 SSIBus **ssp;
Paul Brookbc24a222009-05-10 01:44:56 +0100138 PXA2xxI2CState *i2c[2];
139 PXA2xxMMCIState *mmc;
140 PXA2xxPCMCIAState *pcmcia[2];
141 PXA2xxI2SState *i2s;
142 PXA2xxFIrState *fir;
143 PXA2xxKeyPadState *kp;
balrogc1713132007-04-30 01:26:42 +0000144
145 /* Power management */
Anthony Liguoric227f092009-10-01 16:12:16 -0500146 target_phys_addr_t pm_base;
balrogc1713132007-04-30 01:26:42 +0000147 uint32_t pm_regs[0x40];
148
149 /* Clock management */
Anthony Liguoric227f092009-10-01 16:12:16 -0500150 target_phys_addr_t cm_base;
balrogc1713132007-04-30 01:26:42 +0000151 uint32_t cm_regs[4];
152 uint32_t clkcfg;
153
154 /* Memory management */
Anthony Liguoric227f092009-10-01 16:12:16 -0500155 target_phys_addr_t mm_base;
balrogc1713132007-04-30 01:26:42 +0000156 uint32_t mm_regs[0x1a];
157
158 /* Performance monitoring */
159 uint32_t pmnc;
160
161 /* Real-Time clock */
Anthony Liguoric227f092009-10-01 16:12:16 -0500162 target_phys_addr_t rtc_base;
balrogc1713132007-04-30 01:26:42 +0000163 uint32_t rttr;
164 uint32_t rtsr;
165 uint32_t rtar;
166 uint32_t rdar1;
167 uint32_t rdar2;
168 uint32_t ryar1;
169 uint32_t ryar2;
170 uint32_t swar1;
171 uint32_t swar2;
172 uint32_t piar;
173 uint32_t last_rcnr;
174 uint32_t last_rdcr;
175 uint32_t last_rycr;
176 uint32_t last_swcr;
177 uint32_t last_rtcpicr;
178 int64_t last_hz;
179 int64_t last_sw;
180 int64_t last_pi;
181 QEMUTimer *rtc_hz;
182 QEMUTimer *rtc_rdal1;
183 QEMUTimer *rtc_rdal2;
184 QEMUTimer *rtc_swal1;
185 QEMUTimer *rtc_swal2;
186 QEMUTimer *rtc_pi;
Paul Brookbc24a222009-05-10 01:44:56 +0100187} PXA2xxState;
balrogc1713132007-04-30 01:26:42 +0000188
Paul Brookbc24a222009-05-10 01:44:56 +0100189struct PXA2xxI2SState {
balrogc1713132007-04-30 01:26:42 +0000190 qemu_irq irq;
Paul Brookbc24a222009-05-10 01:44:56 +0100191 PXA2xxDMAState *dma;
balrogc1713132007-04-30 01:26:42 +0000192 void (*data_req)(void *, int, int);
193
194 uint32_t control[2];
195 uint32_t status;
196 uint32_t mask;
197 uint32_t clk;
198
199 int enable;
200 int rx_len;
201 int tx_len;
202 void (*codec_out)(void *, uint32_t);
203 uint32_t (*codec_in)(void *);
204 void *opaque;
205
206 int fifo_len;
207 uint32_t fifo[16];
208};
209
210# define PA_FMT "0x%08lx"
bellard444ce242007-11-11 19:47:59 +0000211# define REG_FMT "0x" TARGET_FMT_plx
balrogc1713132007-04-30 01:26:42 +0000212
Paul Brookbc24a222009-05-10 01:44:56 +0100213PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
214PXA2xxState *pxa255_init(unsigned int sdram_size);
balrogc1713132007-04-30 01:26:42 +0000215
balrogc1713132007-04-30 01:26:42 +0000216#endif /* PXA_H */