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bellarddbda8082004-06-15 21:38:40 +00001/*
2 * OpenPIC emulation
ths5fafdf22007-09-16 21:08:06 +00003 *
bellarddbda8082004-06-15 21:38:40 +00004 * Copyright (c) 2004 Jocelyn Mayer
Alexander Graf704c7e52011-07-21 01:33:29 +02005 * 2011 Alexander Graf
ths5fafdf22007-09-16 21:08:06 +00006 *
bellarddbda8082004-06-15 21:38:40 +00007 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25/*
26 *
27 * Based on OpenPic implementations:
blueswir167b55782009-02-06 21:30:02 +000028 * - Intel GW80314 I/O companion chip developer's manual
bellarddbda8082004-06-15 21:38:40 +000029 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
32 *
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
ths5fafdf22007-09-16 21:08:06 +000034 *
bellarddbda8082004-06-15 21:38:40 +000035 */
pbrook87ecb682007-11-17 17:14:51 +000036#include "hw.h"
37#include "ppc_mac.h"
38#include "pci.h"
aurel32b7169912009-03-02 16:42:04 +000039#include "openpic.h"
bellarddbda8082004-06-15 21:38:40 +000040
bellard611493d2004-06-21 16:50:43 +000041//#define DEBUG_OPENPIC
bellarddbda8082004-06-15 21:38:40 +000042
43#ifdef DEBUG_OPENPIC
Blue Swirl001faf32009-05-13 17:53:17 +000044#define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
bellarddbda8082004-06-15 21:38:40 +000045#else
Blue Swirl001faf32009-05-13 17:53:17 +000046#define DPRINTF(fmt, ...) do { } while (0)
bellarddbda8082004-06-15 21:38:40 +000047#endif
bellarddbda8082004-06-15 21:38:40 +000048
49#define USE_MPCxxx /* Intel model is broken, for now */
50
51#if defined (USE_INTEL_GW80314)
52/* Intel GW80314 I/O Companion chip */
53
54#define MAX_CPU 4
55#define MAX_IRQ 32
56#define MAX_DBL 4
57#define MAX_MBX 4
58#define MAX_TMR 4
59#define VECTOR_BITS 8
Alexander Grafa6751552011-07-21 01:36:44 +020060#define MAX_IPI 4
bellarddbda8082004-06-15 21:38:40 +000061
62#define VID (0x00000000)
63
bellarddbda8082004-06-15 21:38:40 +000064#elif defined(USE_MPCxxx)
65
Alexander Grafbbc58422011-07-21 01:39:46 +020066#define MAX_CPU 15
aurel32b7169912009-03-02 16:42:04 +000067#define MAX_IRQ 128
bellarddbda8082004-06-15 21:38:40 +000068#define MAX_DBL 0
69#define MAX_MBX 0
70#define MAX_TMR 4
71#define VECTOR_BITS 8
72#define MAX_IPI 4
73#define VID 0x03 /* MPIC version ID */
74#define VENI 0x00000000 /* Vendor ID */
75
76enum {
77 IRQ_IPVP = 0,
78 IRQ_IDE,
79};
80
aurel32b7169912009-03-02 16:42:04 +000081/* OpenPIC */
82#define OPENPIC_MAX_CPU 2
83#define OPENPIC_MAX_IRQ 64
84#define OPENPIC_EXT_IRQ 48
85#define OPENPIC_MAX_TMR MAX_TMR
86#define OPENPIC_MAX_IPI MAX_IPI
87
88/* Interrupt definitions */
89#define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */
90#define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
91#define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
92#if OPENPIC_MAX_IPI > 0
93#define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
94#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
95#else
96#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
97#define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
98#endif
99
100/* MPIC */
101#define MPIC_MAX_CPU 1
102#define MPIC_MAX_EXT 12
103#define MPIC_MAX_INT 64
104#define MPIC_MAX_MSG 4
105#define MPIC_MAX_MSI 8
106#define MPIC_MAX_TMR MAX_TMR
107#define MPIC_MAX_IPI MAX_IPI
108#define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
109
110/* Interrupt definitions */
111#define MPIC_EXT_IRQ 0
112#define MPIC_INT_IRQ (MPIC_EXT_IRQ + MPIC_MAX_EXT)
113#define MPIC_TMR_IRQ (MPIC_INT_IRQ + MPIC_MAX_INT)
114#define MPIC_MSG_IRQ (MPIC_TMR_IRQ + MPIC_MAX_TMR)
115#define MPIC_MSI_IRQ (MPIC_MSG_IRQ + MPIC_MAX_MSG)
116#define MPIC_IPI_IRQ (MPIC_MSI_IRQ + MPIC_MAX_MSI)
117
118#define MPIC_GLB_REG_START 0x0
119#define MPIC_GLB_REG_SIZE 0x10F0
120#define MPIC_TMR_REG_START 0x10F0
121#define MPIC_TMR_REG_SIZE 0x220
122#define MPIC_EXT_REG_START 0x10000
123#define MPIC_EXT_REG_SIZE 0x180
124#define MPIC_INT_REG_START 0x10200
125#define MPIC_INT_REG_SIZE 0x800
126#define MPIC_MSG_REG_START 0x11600
127#define MPIC_MSG_REG_SIZE 0x100
128#define MPIC_MSI_REG_START 0x11C00
129#define MPIC_MSI_REG_SIZE 0x100
130#define MPIC_CPU_REG_START 0x20000
Alexander Grafbc59d9c2011-07-21 01:35:15 +0200131#define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
aurel32b7169912009-03-02 16:42:04 +0000132
133enum mpic_ide_bits {
Alexander Graf0d33def2011-07-23 11:27:53 +0200134 IDR_EP = 31,
135 IDR_CI0 = 30,
136 IDR_CI1 = 29,
137 IDR_P1 = 1,
138 IDR_P0 = 0,
aurel32b7169912009-03-02 16:42:04 +0000139};
bellarddbda8082004-06-15 21:38:40 +0000140
141#else
142#error "Please select which OpenPic implementation is to be emulated"
143#endif
144
Blue Swirl5c4532e2010-03-29 19:23:59 +0000145#define OPENPIC_PAGE_SIZE 4096
146
bellarddbda8082004-06-15 21:38:40 +0000147#define BF_WIDTH(_bits_) \
148(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
149
150static inline void set_bit (uint32_t *field, int bit)
151{
152 field[bit >> 5] |= 1 << (bit & 0x1F);
153}
154
155static inline void reset_bit (uint32_t *field, int bit)
156{
157 field[bit >> 5] &= ~(1 << (bit & 0x1F));
158}
159
160static inline int test_bit (uint32_t *field, int bit)
161{
162 return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0;
163}
164
Alexander Graf704c7e52011-07-21 01:33:29 +0200165static int get_current_cpu(void)
166{
167 return cpu_single_env->cpu_index;
168}
169
170static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
171 int idx);
172static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
173 uint32_t val, int idx);
174
bellarddbda8082004-06-15 21:38:40 +0000175enum {
176 IRQ_EXTERNAL = 0x01,
177 IRQ_INTERNAL = 0x02,
178 IRQ_TIMER = 0x04,
179 IRQ_SPECIAL = 0x08,
blueswir1b1d8e522008-10-26 13:43:07 +0000180};
bellarddbda8082004-06-15 21:38:40 +0000181
Anthony Liguoric227f092009-10-01 16:12:16 -0500182typedef struct IRQ_queue_t {
bellarddbda8082004-06-15 21:38:40 +0000183 uint32_t queue[BF_WIDTH(MAX_IRQ)];
184 int next;
185 int priority;
Anthony Liguoric227f092009-10-01 16:12:16 -0500186} IRQ_queue_t;
bellarddbda8082004-06-15 21:38:40 +0000187
Anthony Liguoric227f092009-10-01 16:12:16 -0500188typedef struct IRQ_src_t {
bellarddbda8082004-06-15 21:38:40 +0000189 uint32_t ipvp; /* IRQ vector/priority register */
190 uint32_t ide; /* IRQ destination register */
191 int type;
192 int last_cpu;
bellard611493d2004-06-21 16:50:43 +0000193 int pending; /* TRUE if IRQ is pending */
Anthony Liguoric227f092009-10-01 16:12:16 -0500194} IRQ_src_t;
bellarddbda8082004-06-15 21:38:40 +0000195
196enum IPVP_bits {
197 IPVP_MASK = 31,
198 IPVP_ACTIVITY = 30,
199 IPVP_MODE = 29,
200 IPVP_POLARITY = 23,
201 IPVP_SENSE = 22,
202};
203#define IPVP_PRIORITY_MASK (0x1F << 16)
bellard611493d2004-06-21 16:50:43 +0000204#define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
bellarddbda8082004-06-15 21:38:40 +0000205#define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
206#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
207
Anthony Liguoric227f092009-10-01 16:12:16 -0500208typedef struct IRQ_dst_t {
aurel32b7169912009-03-02 16:42:04 +0000209 uint32_t tfrr;
bellarddbda8082004-06-15 21:38:40 +0000210 uint32_t pctp; /* CPU current task priority */
211 uint32_t pcsr; /* CPU sensitivity register */
Anthony Liguoric227f092009-10-01 16:12:16 -0500212 IRQ_queue_t raised;
213 IRQ_queue_t servicing;
j_mayere9df0142007-04-09 22:45:36 +0000214 qemu_irq *irqs;
Anthony Liguoric227f092009-10-01 16:12:16 -0500215} IRQ_dst_t;
bellarddbda8082004-06-15 21:38:40 +0000216
Anthony Liguoric227f092009-10-01 16:12:16 -0500217typedef struct openpic_t {
bellarddbda8082004-06-15 21:38:40 +0000218 PCIDevice pci_dev;
Avi Kivity23c5e4c2011-08-08 16:09:17 +0300219 MemoryRegion mem;
Fabien Chouteau71cf9e62011-08-30 17:46:26 +0200220
221 /* Sub-regions */
222 MemoryRegion sub_io_mem[7];
223
bellarddbda8082004-06-15 21:38:40 +0000224 /* Global registers */
225 uint32_t frep; /* Feature reporting register */
226 uint32_t glbc; /* Global configuration register */
227 uint32_t micr; /* MPIC interrupt configuration register */
228 uint32_t veni; /* Vendor identification register */
j_mayere9df0142007-04-09 22:45:36 +0000229 uint32_t pint; /* Processor initialization register */
bellarddbda8082004-06-15 21:38:40 +0000230 uint32_t spve; /* Spurious vector register */
231 uint32_t tifr; /* Timer frequency reporting register */
232 /* Source registers */
Anthony Liguoric227f092009-10-01 16:12:16 -0500233 IRQ_src_t src[MAX_IRQ];
bellarddbda8082004-06-15 21:38:40 +0000234 /* Local registers per output pin */
Anthony Liguoric227f092009-10-01 16:12:16 -0500235 IRQ_dst_t dst[MAX_CPU];
bellarddbda8082004-06-15 21:38:40 +0000236 int nb_cpus;
237 /* Timer registers */
238 struct {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100239 uint32_t ticc; /* Global timer current count register */
240 uint32_t tibc; /* Global timer base count register */
bellarddbda8082004-06-15 21:38:40 +0000241 } timers[MAX_TMR];
242#if MAX_DBL > 0
243 /* Doorbell registers */
244 uint32_t dar; /* Doorbell activate register */
245 struct {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100246 uint32_t dmr; /* Doorbell messaging register */
bellarddbda8082004-06-15 21:38:40 +0000247 } doorbells[MAX_DBL];
248#endif
249#if MAX_MBX > 0
250 /* Mailbox registers */
251 struct {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100252 uint32_t mbr; /* Mailbox register */
bellarddbda8082004-06-15 21:38:40 +0000253 } mailboxes[MAX_MAILBOXES];
254#endif
j_mayere9df0142007-04-09 22:45:36 +0000255 /* IRQ out is used when in bypass mode (not implemented) */
256 qemu_irq irq_out;
aurel32b7169912009-03-02 16:42:04 +0000257 int max_irq;
258 int irq_ipi0;
259 int irq_tim0;
aurel32b7169912009-03-02 16:42:04 +0000260 void (*reset) (void *);
Anthony Liguoric227f092009-10-01 16:12:16 -0500261 void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
262} openpic_t;
bellarddbda8082004-06-15 21:38:40 +0000263
Anthony Liguoric227f092009-10-01 16:12:16 -0500264static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
bellarddbda8082004-06-15 21:38:40 +0000265{
266 set_bit(q->queue, n_IRQ);
267}
268
Anthony Liguoric227f092009-10-01 16:12:16 -0500269static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ)
bellarddbda8082004-06-15 21:38:40 +0000270{
271 reset_bit(q->queue, n_IRQ);
272}
273
Anthony Liguoric227f092009-10-01 16:12:16 -0500274static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
bellarddbda8082004-06-15 21:38:40 +0000275{
276 return test_bit(q->queue, n_IRQ);
277}
278
Anthony Liguoric227f092009-10-01 16:12:16 -0500279static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
bellarddbda8082004-06-15 21:38:40 +0000280{
281 int next, i;
282 int priority;
283
284 next = -1;
285 priority = -1;
aurel32b7169912009-03-02 16:42:04 +0000286 for (i = 0; i < opp->max_irq; i++) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100287 if (IRQ_testbit(q, i)) {
ths5fafdf22007-09-16 21:08:06 +0000288 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
bellard611493d2004-06-21 16:50:43 +0000289 i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100290 if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
291 next = i;
292 priority = IPVP_PRIORITY(opp->src[i].ipvp);
293 }
294 }
bellarddbda8082004-06-15 21:38:40 +0000295 }
296 q->next = next;
297 q->priority = priority;
298}
299
Anthony Liguoric227f092009-10-01 16:12:16 -0500300static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
bellarddbda8082004-06-15 21:38:40 +0000301{
302 if (q->next == -1) {
bellard611493d2004-06-21 16:50:43 +0000303 /* XXX: optimize */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100304 IRQ_check(opp, q);
bellarddbda8082004-06-15 21:38:40 +0000305 }
306
307 return q->next;
308}
309
Anthony Liguoric227f092009-10-01 16:12:16 -0500310static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
bellarddbda8082004-06-15 21:38:40 +0000311{
Anthony Liguoric227f092009-10-01 16:12:16 -0500312 IRQ_dst_t *dst;
313 IRQ_src_t *src;
bellarddbda8082004-06-15 21:38:40 +0000314 int priority;
315
316 dst = &opp->dst[n_CPU];
317 src = &opp->src[n_IRQ];
318 priority = IPVP_PRIORITY(src->ipvp);
319 if (priority <= dst->pctp) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100320 /* Too low priority */
j_mayere9df0142007-04-09 22:45:36 +0000321 DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
322 __func__, n_IRQ, n_CPU);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100323 return;
bellarddbda8082004-06-15 21:38:40 +0000324 }
325 if (IRQ_testbit(&dst->raised, n_IRQ)) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100326 /* Interrupt miss */
j_mayere9df0142007-04-09 22:45:36 +0000327 DPRINTF("%s: IRQ %d was missed on CPU %d\n",
328 __func__, n_IRQ, n_CPU);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100329 return;
bellarddbda8082004-06-15 21:38:40 +0000330 }
331 set_bit(&src->ipvp, IPVP_ACTIVITY);
332 IRQ_setbit(&dst->raised, n_IRQ);
j_mayere9df0142007-04-09 22:45:36 +0000333 if (priority < dst->raised.priority) {
334 /* An higher priority IRQ is already raised */
335 DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
336 __func__, n_IRQ, dst->raised.next, n_CPU);
337 return;
bellarddbda8082004-06-15 21:38:40 +0000338 }
j_mayere9df0142007-04-09 22:45:36 +0000339 IRQ_get_next(opp, &dst->raised);
340 if (IRQ_get_next(opp, &dst->servicing) != -1 &&
aliguori24865162009-01-15 21:19:54 +0000341 priority <= dst->servicing.priority) {
j_mayere9df0142007-04-09 22:45:36 +0000342 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
343 __func__, n_IRQ, dst->servicing.next, n_CPU);
344 /* Already servicing a higher priority IRQ */
345 return;
346 }
347 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
aurel32b7169912009-03-02 16:42:04 +0000348 opp->irq_raise(opp, n_CPU, src);
bellarddbda8082004-06-15 21:38:40 +0000349}
350
bellard611493d2004-06-21 16:50:43 +0000351/* update pic state because registers for n_IRQ have changed value */
Anthony Liguoric227f092009-10-01 16:12:16 -0500352static void openpic_update_irq(openpic_t *opp, int n_IRQ)
bellarddbda8082004-06-15 21:38:40 +0000353{
Anthony Liguoric227f092009-10-01 16:12:16 -0500354 IRQ_src_t *src;
bellarddbda8082004-06-15 21:38:40 +0000355 int i;
356
357 src = &opp->src[n_IRQ];
bellard611493d2004-06-21 16:50:43 +0000358
359 if (!src->pending) {
360 /* no irq pending */
j_mayere9df0142007-04-09 22:45:36 +0000361 DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
bellard611493d2004-06-21 16:50:43 +0000362 return;
363 }
364 if (test_bit(&src->ipvp, IPVP_MASK)) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100365 /* Interrupt source is disabled */
j_mayere9df0142007-04-09 22:45:36 +0000366 DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100367 return;
bellarddbda8082004-06-15 21:38:40 +0000368 }
369 if (IPVP_PRIORITY(src->ipvp) == 0) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100370 /* Priority set to zero */
j_mayere9df0142007-04-09 22:45:36 +0000371 DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100372 return;
bellarddbda8082004-06-15 21:38:40 +0000373 }
bellard611493d2004-06-21 16:50:43 +0000374 if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
375 /* IRQ already active */
j_mayere9df0142007-04-09 22:45:36 +0000376 DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ);
bellard611493d2004-06-21 16:50:43 +0000377 return;
378 }
bellarddbda8082004-06-15 21:38:40 +0000379 if (src->ide == 0x00000000) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100380 /* No target */
j_mayere9df0142007-04-09 22:45:36 +0000381 DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100382 return;
bellarddbda8082004-06-15 21:38:40 +0000383 }
bellard611493d2004-06-21 16:50:43 +0000384
j_mayere9df0142007-04-09 22:45:36 +0000385 if (src->ide == (1 << src->last_cpu)) {
386 /* Only one CPU is allowed to receive this IRQ */
387 IRQ_local_pipe(opp, src->last_cpu, n_IRQ);
388 } else if (!test_bit(&src->ipvp, IPVP_MODE)) {
bellard611493d2004-06-21 16:50:43 +0000389 /* Directed delivery mode */
390 for (i = 0; i < opp->nb_cpus; i++) {
391 if (test_bit(&src->ide, i))
392 IRQ_local_pipe(opp, i, n_IRQ);
393 }
bellarddbda8082004-06-15 21:38:40 +0000394 } else {
bellard611493d2004-06-21 16:50:43 +0000395 /* Distributed delivery mode */
j_mayere9df0142007-04-09 22:45:36 +0000396 for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
397 if (i == opp->nb_cpus)
bellard611493d2004-06-21 16:50:43 +0000398 i = 0;
399 if (test_bit(&src->ide, i)) {
400 IRQ_local_pipe(opp, i, n_IRQ);
401 src->last_cpu = i;
402 break;
403 }
404 }
bellarddbda8082004-06-15 21:38:40 +0000405 }
406}
407
pbrookd537cf62007-04-07 18:14:41 +0000408static void openpic_set_irq(void *opaque, int n_IRQ, int level)
bellard611493d2004-06-21 16:50:43 +0000409{
Anthony Liguoric227f092009-10-01 16:12:16 -0500410 openpic_t *opp = opaque;
411 IRQ_src_t *src;
bellard611493d2004-06-21 16:50:43 +0000412
413 src = &opp->src[n_IRQ];
ths5fafdf22007-09-16 21:08:06 +0000414 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
bellard611493d2004-06-21 16:50:43 +0000415 n_IRQ, level, src->ipvp);
416 if (test_bit(&src->ipvp, IPVP_SENSE)) {
417 /* level-sensitive irq */
418 src->pending = level;
419 if (!level)
420 reset_bit(&src->ipvp, IPVP_ACTIVITY);
421 } else {
422 /* edge-sensitive irq */
423 if (level)
424 src->pending = 1;
425 }
426 openpic_update_irq(opp, n_IRQ);
427}
428
blueswir167b55782009-02-06 21:30:02 +0000429static void openpic_reset (void *opaque)
bellarddbda8082004-06-15 21:38:40 +0000430{
Anthony Liguoric227f092009-10-01 16:12:16 -0500431 openpic_t *opp = (openpic_t *)opaque;
bellarddbda8082004-06-15 21:38:40 +0000432 int i;
433
434 opp->glbc = 0x80000000;
bellardf8407022005-02-09 00:01:34 +0000435 /* Initialise controller registers */
aurel32b7169912009-03-02 16:42:04 +0000436 opp->frep = ((OPENPIC_EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID;
bellarddbda8082004-06-15 21:38:40 +0000437 opp->veni = VENI;
j_mayere9df0142007-04-09 22:45:36 +0000438 opp->pint = 0x00000000;
bellarddbda8082004-06-15 21:38:40 +0000439 opp->spve = 0x000000FF;
440 opp->tifr = 0x003F7A00;
441 /* ? */
442 opp->micr = 0x00000000;
443 /* Initialise IRQ sources */
aurel32b7169912009-03-02 16:42:04 +0000444 for (i = 0; i < opp->max_irq; i++) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100445 opp->src[i].ipvp = 0xA0000000;
446 opp->src[i].ide = 0x00000000;
bellarddbda8082004-06-15 21:38:40 +0000447 }
448 /* Initialise IRQ destinations */
j_mayere9df0142007-04-09 22:45:36 +0000449 for (i = 0; i < MAX_CPU; i++) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100450 opp->dst[i].pctp = 0x0000000F;
451 opp->dst[i].pcsr = 0x00000000;
452 memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
Alexander Grafd14ed252009-12-18 23:37:26 +0100453 opp->dst[i].raised.next = -1;
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100454 memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
Alexander Grafd14ed252009-12-18 23:37:26 +0100455 opp->dst[i].servicing.next = -1;
bellarddbda8082004-06-15 21:38:40 +0000456 }
457 /* Initialise timers */
458 for (i = 0; i < MAX_TMR; i++) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100459 opp->timers[i].ticc = 0x00000000;
460 opp->timers[i].tibc = 0x80000000;
bellarddbda8082004-06-15 21:38:40 +0000461 }
462 /* Initialise doorbells */
463#if MAX_DBL > 0
464 opp->dar = 0x00000000;
465 for (i = 0; i < MAX_DBL; i++) {
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100466 opp->doorbells[i].dmr = 0x00000000;
bellarddbda8082004-06-15 21:38:40 +0000467 }
468#endif
469 /* Initialise mailboxes */
470#if MAX_MBX > 0
471 for (i = 0; i < MAX_MBX; i++) { /* ? */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100472 opp->mailboxes[i].mbr = 0x00000000;
bellarddbda8082004-06-15 21:38:40 +0000473 }
474#endif
475 /* Go out of RESET state */
476 opp->glbc = 0x00000000;
477}
478
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200479static inline uint32_t read_IRQreg_ide(openpic_t *opp, int n_IRQ)
bellarddbda8082004-06-15 21:38:40 +0000480{
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200481 return opp->src[n_IRQ].ide;
bellarddbda8082004-06-15 21:38:40 +0000482}
483
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200484static inline uint32_t read_IRQreg_ipvp(openpic_t *opp, int n_IRQ)
485{
486 return opp->src[n_IRQ].ipvp;
bellarddbda8082004-06-15 21:38:40 +0000487}
488
Alexander Graf11de8b72011-09-07 13:47:22 +0200489static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val)
bellarddbda8082004-06-15 21:38:40 +0000490{
491 uint32_t tmp;
492
Alexander Graf11de8b72011-09-07 13:47:22 +0200493 tmp = val & 0xC0000000;
494 tmp |= val & ((1ULL << MAX_CPU) - 1);
495 opp->src[n_IRQ].ide = tmp;
496 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
497}
498
499static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
500{
501 /* NOTE: not fully accurate for special IRQs, but simple and sufficient */
502 /* ACTIVITY bit is read-only */
503 opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & 0x40000000)
504 | (val & 0x800F00FF);
505 openpic_update_irq(opp, n_IRQ);
506 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
507 opp->src[n_IRQ].ipvp);
bellarddbda8082004-06-15 21:38:40 +0000508}
509
510#if 0 // Code provision for Intel model
511#if MAX_DBL > 0
Anthony Liguoric227f092009-10-01 16:12:16 -0500512static uint32_t read_doorbell_register (openpic_t *opp,
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100513 int n_dbl, uint32_t offset)
bellarddbda8082004-06-15 21:38:40 +0000514{
515 uint32_t retval;
516
517 switch (offset) {
518 case DBL_IPVP_OFFSET:
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200519 retval = read_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100520 break;
bellarddbda8082004-06-15 21:38:40 +0000521 case DBL_IDE_OFFSET:
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200522 retval = read_IRQreg_ide(opp, IRQ_DBL0 + n_dbl);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100523 break;
bellarddbda8082004-06-15 21:38:40 +0000524 case DBL_DMR_OFFSET:
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100525 retval = opp->doorbells[n_dbl].dmr;
526 break;
bellarddbda8082004-06-15 21:38:40 +0000527 }
528
529 return retval;
530}
ths3b46e622007-09-17 08:09:54 +0000531
bellarddbda8082004-06-15 21:38:40 +0000532static void write_doorbell_register (penpic_t *opp, int n_dbl,
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100533 uint32_t offset, uint32_t value)
bellarddbda8082004-06-15 21:38:40 +0000534{
535 switch (offset) {
536 case DBL_IVPR_OFFSET:
Alexander Graf11de8b72011-09-07 13:47:22 +0200537 write_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl, value);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100538 break;
bellarddbda8082004-06-15 21:38:40 +0000539 case DBL_IDE_OFFSET:
Alexander Graf11de8b72011-09-07 13:47:22 +0200540 write_IRQreg_ide(opp, IRQ_DBL0 + n_dbl, value);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100541 break;
bellarddbda8082004-06-15 21:38:40 +0000542 case DBL_DMR_OFFSET:
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100543 opp->doorbells[n_dbl].dmr = value;
544 break;
bellarddbda8082004-06-15 21:38:40 +0000545 }
546}
547#endif
548
549#if MAX_MBX > 0
Anthony Liguoric227f092009-10-01 16:12:16 -0500550static uint32_t read_mailbox_register (openpic_t *opp,
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100551 int n_mbx, uint32_t offset)
bellarddbda8082004-06-15 21:38:40 +0000552{
553 uint32_t retval;
554
555 switch (offset) {
556 case MBX_MBR_OFFSET:
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100557 retval = opp->mailboxes[n_mbx].mbr;
558 break;
bellarddbda8082004-06-15 21:38:40 +0000559 case MBX_IVPR_OFFSET:
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200560 retval = read_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100561 break;
bellarddbda8082004-06-15 21:38:40 +0000562 case MBX_DMR_OFFSET:
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200563 retval = read_IRQreg_ide(opp, IRQ_MBX0 + n_mbx);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100564 break;
bellarddbda8082004-06-15 21:38:40 +0000565 }
566
567 return retval;
568}
569
Anthony Liguoric227f092009-10-01 16:12:16 -0500570static void write_mailbox_register (openpic_t *opp, int n_mbx,
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100571 uint32_t address, uint32_t value)
bellarddbda8082004-06-15 21:38:40 +0000572{
573 switch (offset) {
574 case MBX_MBR_OFFSET:
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100575 opp->mailboxes[n_mbx].mbr = value;
576 break;
bellarddbda8082004-06-15 21:38:40 +0000577 case MBX_IVPR_OFFSET:
Alexander Graf11de8b72011-09-07 13:47:22 +0200578 write_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx, value);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100579 break;
bellarddbda8082004-06-15 21:38:40 +0000580 case MBX_DMR_OFFSET:
Alexander Graf11de8b72011-09-07 13:47:22 +0200581 write_IRQreg_ide(opp, IRQ_MBX0 + n_mbx, value);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100582 break;
bellarddbda8082004-06-15 21:38:40 +0000583 }
584}
585#endif
586#endif /* 0 : Code provision for Intel model */
587
Anthony Liguoric227f092009-10-01 16:12:16 -0500588static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t val)
bellarddbda8082004-06-15 21:38:40 +0000589{
Anthony Liguoric227f092009-10-01 16:12:16 -0500590 openpic_t *opp = opaque;
591 IRQ_dst_t *dst;
j_mayere9df0142007-04-09 22:45:36 +0000592 int idx;
bellarddbda8082004-06-15 21:38:40 +0000593
Blue Swirl0bf9e312009-07-20 17:19:25 +0000594 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
bellarddbda8082004-06-15 21:38:40 +0000595 if (addr & 0xF)
596 return;
bellarddbda8082004-06-15 21:38:40 +0000597 switch (addr) {
Alexander Graf704c7e52011-07-21 01:33:29 +0200598 case 0x40:
599 case 0x50:
600 case 0x60:
601 case 0x70:
602 case 0x80:
603 case 0x90:
604 case 0xA0:
605 case 0xB0:
606 openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
bellarddbda8082004-06-15 21:38:40 +0000607 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200608 case 0x1000: /* FREP */
609 break;
610 case 0x1020: /* GLBC */
aurel32b7169912009-03-02 16:42:04 +0000611 if (val & 0x80000000 && opp->reset)
612 opp->reset(opp);
bellarddbda8082004-06-15 21:38:40 +0000613 opp->glbc = val & ~0x80000000;
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100614 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200615 case 0x1080: /* VENI */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100616 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200617 case 0x1090: /* PINT */
j_mayere9df0142007-04-09 22:45:36 +0000618 for (idx = 0; idx < opp->nb_cpus; idx++) {
619 if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) {
620 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
621 dst = &opp->dst[idx];
622 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]);
623 } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) {
624 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
625 dst = &opp->dst[idx];
626 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]);
627 }
bellarddbda8082004-06-15 21:38:40 +0000628 }
j_mayere9df0142007-04-09 22:45:36 +0000629 opp->pint = val;
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100630 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200631 case 0x10A0: /* IPI_IPVP */
632 case 0x10B0:
633 case 0x10C0:
634 case 0x10D0:
bellarddbda8082004-06-15 21:38:40 +0000635 {
636 int idx;
Alexander Graf704c7e52011-07-21 01:33:29 +0200637 idx = (addr - 0x10A0) >> 4;
Alexander Graf11de8b72011-09-07 13:47:22 +0200638 write_IRQreg_ipvp(opp, opp->irq_ipi0 + idx, val);
bellarddbda8082004-06-15 21:38:40 +0000639 }
640 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200641 case 0x10E0: /* SPVE */
bellarddbda8082004-06-15 21:38:40 +0000642 opp->spve = val & 0x000000FF;
643 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200644 case 0x10F0: /* TIFR */
bellarddbda8082004-06-15 21:38:40 +0000645 opp->tifr = val;
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100646 break;
bellarddbda8082004-06-15 21:38:40 +0000647 default:
648 break;
649 }
650}
651
Anthony Liguoric227f092009-10-01 16:12:16 -0500652static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
bellarddbda8082004-06-15 21:38:40 +0000653{
Anthony Liguoric227f092009-10-01 16:12:16 -0500654 openpic_t *opp = opaque;
bellarddbda8082004-06-15 21:38:40 +0000655 uint32_t retval;
656
Blue Swirl0bf9e312009-07-20 17:19:25 +0000657 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
bellarddbda8082004-06-15 21:38:40 +0000658 retval = 0xFFFFFFFF;
659 if (addr & 0xF)
660 return retval;
bellarddbda8082004-06-15 21:38:40 +0000661 switch (addr) {
Alexander Graf704c7e52011-07-21 01:33:29 +0200662 case 0x1000: /* FREP */
bellarddbda8082004-06-15 21:38:40 +0000663 retval = opp->frep;
664 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200665 case 0x1020: /* GLBC */
bellarddbda8082004-06-15 21:38:40 +0000666 retval = opp->glbc;
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100667 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200668 case 0x1080: /* VENI */
bellarddbda8082004-06-15 21:38:40 +0000669 retval = opp->veni;
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100670 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200671 case 0x1090: /* PINT */
bellarddbda8082004-06-15 21:38:40 +0000672 retval = 0x00000000;
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100673 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200674 case 0x40:
675 case 0x50:
676 case 0x60:
677 case 0x70:
678 case 0x80:
679 case 0x90:
680 case 0xA0:
bellarddbda8082004-06-15 21:38:40 +0000681 case 0xB0:
Alexander Graf704c7e52011-07-21 01:33:29 +0200682 retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
683 break;
684 case 0x10A0: /* IPI_IPVP */
685 case 0x10B0:
686 case 0x10C0:
687 case 0x10D0:
bellarddbda8082004-06-15 21:38:40 +0000688 {
689 int idx;
Alexander Graf704c7e52011-07-21 01:33:29 +0200690 idx = (addr - 0x10A0) >> 4;
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200691 retval = read_IRQreg_ipvp(opp, opp->irq_ipi0 + idx);
bellarddbda8082004-06-15 21:38:40 +0000692 }
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100693 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200694 case 0x10E0: /* SPVE */
bellarddbda8082004-06-15 21:38:40 +0000695 retval = opp->spve;
696 break;
Alexander Graf704c7e52011-07-21 01:33:29 +0200697 case 0x10F0: /* TIFR */
bellarddbda8082004-06-15 21:38:40 +0000698 retval = opp->tifr;
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100699 break;
bellarddbda8082004-06-15 21:38:40 +0000700 default:
701 break;
702 }
703 DPRINTF("%s: => %08x\n", __func__, retval);
bellarddbda8082004-06-15 21:38:40 +0000704
705 return retval;
706}
707
708static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
709{
Anthony Liguoric227f092009-10-01 16:12:16 -0500710 openpic_t *opp = opaque;
bellarddbda8082004-06-15 21:38:40 +0000711 int idx;
712
713 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
714 if (addr & 0xF)
715 return;
bellarddbda8082004-06-15 21:38:40 +0000716 addr -= 0x1100;
717 addr &= 0xFFFF;
718 idx = (addr & 0xFFF0) >> 6;
719 addr = addr & 0x30;
720 switch (addr) {
721 case 0x00: /* TICC */
722 break;
723 case 0x10: /* TIBC */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100724 if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
725 (val & 0x80000000) == 0 &&
bellarddbda8082004-06-15 21:38:40 +0000726 (opp->timers[idx].tibc & 0x80000000) != 0)
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100727 opp->timers[idx].ticc &= ~0x80000000;
728 opp->timers[idx].tibc = val;
729 break;
bellarddbda8082004-06-15 21:38:40 +0000730 case 0x20: /* TIVP */
Alexander Graf11de8b72011-09-07 13:47:22 +0200731 write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100732 break;
bellarddbda8082004-06-15 21:38:40 +0000733 case 0x30: /* TIDE */
Alexander Graf11de8b72011-09-07 13:47:22 +0200734 write_IRQreg_ide(opp, opp->irq_tim0 + idx, val);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100735 break;
bellarddbda8082004-06-15 21:38:40 +0000736 }
737}
738
739static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
740{
Anthony Liguoric227f092009-10-01 16:12:16 -0500741 openpic_t *opp = opaque;
bellarddbda8082004-06-15 21:38:40 +0000742 uint32_t retval;
743 int idx;
744
745 DPRINTF("%s: addr %08x\n", __func__, addr);
746 retval = 0xFFFFFFFF;
747 if (addr & 0xF)
748 return retval;
749 addr -= 0x1100;
750 addr &= 0xFFFF;
751 idx = (addr & 0xFFF0) >> 6;
752 addr = addr & 0x30;
753 switch (addr) {
754 case 0x00: /* TICC */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100755 retval = opp->timers[idx].ticc;
bellarddbda8082004-06-15 21:38:40 +0000756 break;
757 case 0x10: /* TIBC */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100758 retval = opp->timers[idx].tibc;
759 break;
bellarddbda8082004-06-15 21:38:40 +0000760 case 0x20: /* TIPV */
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200761 retval = read_IRQreg_ipvp(opp, opp->irq_tim0 + idx);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100762 break;
bellarddbda8082004-06-15 21:38:40 +0000763 case 0x30: /* TIDE */
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200764 retval = read_IRQreg_ide(opp, opp->irq_tim0 + idx);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100765 break;
bellarddbda8082004-06-15 21:38:40 +0000766 }
767 DPRINTF("%s: => %08x\n", __func__, retval);
bellarddbda8082004-06-15 21:38:40 +0000768
769 return retval;
770}
771
772static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
773{
Anthony Liguoric227f092009-10-01 16:12:16 -0500774 openpic_t *opp = opaque;
bellarddbda8082004-06-15 21:38:40 +0000775 int idx;
776
777 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
778 if (addr & 0xF)
779 return;
bellarddbda8082004-06-15 21:38:40 +0000780 addr = addr & 0xFFF0;
781 idx = addr >> 5;
782 if (addr & 0x10) {
783 /* EXDE / IFEDE / IEEDE */
Alexander Graf11de8b72011-09-07 13:47:22 +0200784 write_IRQreg_ide(opp, idx, val);
bellarddbda8082004-06-15 21:38:40 +0000785 } else {
786 /* EXVP / IFEVP / IEEVP */
Alexander Graf11de8b72011-09-07 13:47:22 +0200787 write_IRQreg_ipvp(opp, idx, val);
bellarddbda8082004-06-15 21:38:40 +0000788 }
789}
790
791static uint32_t openpic_src_read (void *opaque, uint32_t addr)
792{
Anthony Liguoric227f092009-10-01 16:12:16 -0500793 openpic_t *opp = opaque;
bellarddbda8082004-06-15 21:38:40 +0000794 uint32_t retval;
795 int idx;
796
797 DPRINTF("%s: addr %08x\n", __func__, addr);
798 retval = 0xFFFFFFFF;
799 if (addr & 0xF)
800 return retval;
801 addr = addr & 0xFFF0;
802 idx = addr >> 5;
803 if (addr & 0x10) {
804 /* EXDE / IFEDE / IEEDE */
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200805 retval = read_IRQreg_ide(opp, idx);
bellarddbda8082004-06-15 21:38:40 +0000806 } else {
807 /* EXVP / IFEVP / IEEVP */
Alexander Graf8d3a8c12011-09-07 13:41:54 +0200808 retval = read_IRQreg_ipvp(opp, idx);
bellarddbda8082004-06-15 21:38:40 +0000809 }
810 DPRINTF("%s: => %08x\n", __func__, retval);
bellarddbda8082004-06-15 21:38:40 +0000811
812 return retval;
813}
814
Alexander Graf704c7e52011-07-21 01:33:29 +0200815static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
816 uint32_t val, int idx)
bellarddbda8082004-06-15 21:38:40 +0000817{
Anthony Liguoric227f092009-10-01 16:12:16 -0500818 openpic_t *opp = opaque;
819 IRQ_src_t *src;
820 IRQ_dst_t *dst;
Alexander Graf704c7e52011-07-21 01:33:29 +0200821 int s_IRQ, n_IRQ;
bellarddbda8082004-06-15 21:38:40 +0000822
Alexander Graf704c7e52011-07-21 01:33:29 +0200823 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx,
824 addr, val);
bellarddbda8082004-06-15 21:38:40 +0000825 if (addr & 0xF)
826 return;
bellarddbda8082004-06-15 21:38:40 +0000827 dst = &opp->dst[idx];
828 addr &= 0xFF0;
829 switch (addr) {
830#if MAX_IPI > 0
Alexander Graf704c7e52011-07-21 01:33:29 +0200831 case 0x40: /* IPIDR */
bellarddbda8082004-06-15 21:38:40 +0000832 case 0x50:
833 case 0x60:
834 case 0x70:
835 idx = (addr - 0x40) >> 4;
Alexander Grafa6751552011-07-21 01:36:44 +0200836 /* we use IDE as mask which CPUs to deliver the IPI to still. */
Alexander Graf11de8b72011-09-07 13:47:22 +0200837 write_IRQreg_ide(opp, opp->irq_ipi0 + idx,
838 opp->src[opp->irq_ipi0 + idx].ide | val);
aurel32b7169912009-03-02 16:42:04 +0000839 openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
840 openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
bellarddbda8082004-06-15 21:38:40 +0000841 break;
842#endif
843 case 0x80: /* PCTP */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100844 dst->pctp = val & 0x0000000F;
845 break;
bellarddbda8082004-06-15 21:38:40 +0000846 case 0x90: /* WHOAMI */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100847 /* Read-only register */
848 break;
bellarddbda8082004-06-15 21:38:40 +0000849 case 0xA0: /* PIAC */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100850 /* Read-only register */
851 break;
bellarddbda8082004-06-15 21:38:40 +0000852 case 0xB0: /* PEOI */
853 DPRINTF("PEOI\n");
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100854 s_IRQ = IRQ_get_next(opp, &dst->servicing);
855 IRQ_resetbit(&dst->servicing, s_IRQ);
856 dst->servicing.next = -1;
857 /* Set up next servicing IRQ */
858 s_IRQ = IRQ_get_next(opp, &dst->servicing);
j_mayere9df0142007-04-09 22:45:36 +0000859 /* Check queued interrupts. */
860 n_IRQ = IRQ_get_next(opp, &dst->raised);
861 src = &opp->src[n_IRQ];
862 if (n_IRQ != -1 &&
863 (s_IRQ == -1 ||
864 IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) {
865 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
866 idx, n_IRQ);
aurel32b7169912009-03-02 16:42:04 +0000867 opp->irq_raise(opp, idx, src);
j_mayere9df0142007-04-09 22:45:36 +0000868 }
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100869 break;
bellarddbda8082004-06-15 21:38:40 +0000870 default:
871 break;
872 }
873}
874
Alexander Graf704c7e52011-07-21 01:33:29 +0200875static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val)
876{
877 openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
878}
879
880static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
881 int idx)
bellarddbda8082004-06-15 21:38:40 +0000882{
Anthony Liguoric227f092009-10-01 16:12:16 -0500883 openpic_t *opp = opaque;
884 IRQ_src_t *src;
885 IRQ_dst_t *dst;
bellarddbda8082004-06-15 21:38:40 +0000886 uint32_t retval;
Alexander Graf704c7e52011-07-21 01:33:29 +0200887 int n_IRQ;
ths3b46e622007-09-17 08:09:54 +0000888
Alexander Graf704c7e52011-07-21 01:33:29 +0200889 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr);
bellarddbda8082004-06-15 21:38:40 +0000890 retval = 0xFFFFFFFF;
891 if (addr & 0xF)
892 return retval;
bellarddbda8082004-06-15 21:38:40 +0000893 dst = &opp->dst[idx];
894 addr &= 0xFF0;
895 switch (addr) {
896 case 0x80: /* PCTP */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100897 retval = dst->pctp;
898 break;
bellarddbda8082004-06-15 21:38:40 +0000899 case 0x90: /* WHOAMI */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100900 retval = idx;
901 break;
bellarddbda8082004-06-15 21:38:40 +0000902 case 0xA0: /* PIAC */
j_mayere9df0142007-04-09 22:45:36 +0000903 DPRINTF("Lower OpenPIC INT output\n");
904 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100905 n_IRQ = IRQ_get_next(opp, &dst->raised);
bellarddbda8082004-06-15 21:38:40 +0000906 DPRINTF("PIAC: irq=%d\n", n_IRQ);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100907 if (n_IRQ == -1) {
908 /* No more interrupt pending */
j_mayere9df0142007-04-09 22:45:36 +0000909 retval = IPVP_VECTOR(opp->spve);
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100910 } else {
911 src = &opp->src[n_IRQ];
912 if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
913 !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
914 /* - Spurious level-sensitive IRQ
915 * - Priorities has been changed
916 * and the pending IRQ isn't allowed anymore
917 */
918 reset_bit(&src->ipvp, IPVP_ACTIVITY);
919 retval = IPVP_VECTOR(opp->spve);
920 } else {
921 /* IRQ enter servicing state */
922 IRQ_setbit(&dst->servicing, n_IRQ);
923 retval = IPVP_VECTOR(src->ipvp);
924 }
925 IRQ_resetbit(&dst->raised, n_IRQ);
926 dst->raised.next = -1;
927 if (!test_bit(&src->ipvp, IPVP_SENSE)) {
bellard611493d2004-06-21 16:50:43 +0000928 /* edge-sensitive IRQ */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100929 reset_bit(&src->ipvp, IPVP_ACTIVITY);
bellard611493d2004-06-21 16:50:43 +0000930 src->pending = 0;
931 }
Alexander Grafa6751552011-07-21 01:36:44 +0200932
933 if ((n_IRQ >= opp->irq_ipi0) && (n_IRQ < (opp->irq_ipi0 + MAX_IPI))) {
934 src->ide &= ~(1 << idx);
935 if (src->ide && !test_bit(&src->ipvp, IPVP_SENSE)) {
936 /* trigger on CPUs that didn't know about it yet */
937 openpic_set_irq(opp, n_IRQ, 1);
938 openpic_set_irq(opp, n_IRQ, 0);
939 /* if all CPUs knew about it, set active bit again */
940 set_bit(&src->ipvp, IPVP_ACTIVITY);
941 }
942 }
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100943 }
944 break;
bellarddbda8082004-06-15 21:38:40 +0000945 case 0xB0: /* PEOI */
Aurelien Jarno060fbfe2009-12-19 15:59:29 +0100946 retval = 0;
947 break;
bellarddbda8082004-06-15 21:38:40 +0000948 default:
949 break;
950 }
951 DPRINTF("%s: => %08x\n", __func__, retval);
bellarddbda8082004-06-15 21:38:40 +0000952
953 return retval;
954}
955
Alexander Graf704c7e52011-07-21 01:33:29 +0200956static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr)
957{
958 return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
959}
960
bellarddbda8082004-06-15 21:38:40 +0000961static void openpic_buggy_write (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500962 target_phys_addr_t addr, uint32_t val)
bellarddbda8082004-06-15 21:38:40 +0000963{
964 printf("Invalid OPENPIC write access !\n");
965}
966
Anthony Liguoric227f092009-10-01 16:12:16 -0500967static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
bellarddbda8082004-06-15 21:38:40 +0000968{
969 printf("Invalid OPENPIC read access !\n");
970
971 return -1;
972}
973
974static void openpic_writel (void *opaque,
Anthony Liguoric227f092009-10-01 16:12:16 -0500975 target_phys_addr_t addr, uint32_t val)
bellarddbda8082004-06-15 21:38:40 +0000976{
Anthony Liguoric227f092009-10-01 16:12:16 -0500977 openpic_t *opp = opaque;
bellarddbda8082004-06-15 21:38:40 +0000978
979 addr &= 0x3FFFF;
bellard611493d2004-06-21 16:50:43 +0000980 DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
bellarddbda8082004-06-15 21:38:40 +0000981 if (addr < 0x1100) {
982 /* Global registers */
983 openpic_gbl_write(opp, addr, val);
984 } else if (addr < 0x10000) {
985 /* Timers registers */
986 openpic_timer_write(opp, addr, val);
987 } else if (addr < 0x20000) {
988 /* Source registers */
989 openpic_src_write(opp, addr, val);
990 } else {
991 /* CPU registers */
992 openpic_cpu_write(opp, addr, val);
993 }
994}
995
Anthony Liguoric227f092009-10-01 16:12:16 -0500996static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
bellarddbda8082004-06-15 21:38:40 +0000997{
Anthony Liguoric227f092009-10-01 16:12:16 -0500998 openpic_t *opp = opaque;
bellarddbda8082004-06-15 21:38:40 +0000999 uint32_t retval;
1000
1001 addr &= 0x3FFFF;
bellard611493d2004-06-21 16:50:43 +00001002 DPRINTF("%s: offset %08x\n", __func__, (int)addr);
bellarddbda8082004-06-15 21:38:40 +00001003 if (addr < 0x1100) {
1004 /* Global registers */
1005 retval = openpic_gbl_read(opp, addr);
1006 } else if (addr < 0x10000) {
1007 /* Timers registers */
1008 retval = openpic_timer_read(opp, addr);
1009 } else if (addr < 0x20000) {
1010 /* Source registers */
1011 retval = openpic_src_read(opp, addr);
1012 } else {
1013 /* CPU registers */
1014 retval = openpic_cpu_read(opp, addr);
1015 }
1016
1017 return retval;
1018}
1019
Avi Kivity23c5e4c2011-08-08 16:09:17 +03001020static uint64_t openpic_read(void *opaque, target_phys_addr_t addr,
1021 unsigned size)
bellarddbda8082004-06-15 21:38:40 +00001022{
Avi Kivity23c5e4c2011-08-08 16:09:17 +03001023 openpic_t *opp = opaque;
bellarddbda8082004-06-15 21:38:40 +00001024
Avi Kivity23c5e4c2011-08-08 16:09:17 +03001025 switch (size) {
1026 case 4: return openpic_readl(opp, addr);
1027 default: return openpic_buggy_read(opp, addr);
1028 }
bellarddbda8082004-06-15 21:38:40 +00001029}
1030
Avi Kivity23c5e4c2011-08-08 16:09:17 +03001031static void openpic_write(void *opaque, target_phys_addr_t addr,
1032 uint64_t data, unsigned size)
1033{
1034 openpic_t *opp = opaque;
1035
1036 switch (size) {
1037 case 4: return openpic_writel(opp, addr, data);
1038 default: return openpic_buggy_write(opp, addr, data);
1039 }
1040}
1041
1042static const MemoryRegionOps openpic_ops = {
1043 .read = openpic_read,
1044 .write = openpic_write,
1045 .endianness = DEVICE_LITTLE_ENDIAN,
1046};
1047
Anthony Liguoric227f092009-10-01 16:12:16 -05001048static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
blueswir167b55782009-02-06 21:30:02 +00001049{
1050 unsigned int i;
1051
1052 for (i = 0; i < BF_WIDTH(MAX_IRQ); i++)
1053 qemu_put_be32s(f, &q->queue[i]);
1054
1055 qemu_put_sbe32s(f, &q->next);
1056 qemu_put_sbe32s(f, &q->priority);
1057}
1058
1059static void openpic_save(QEMUFile* f, void *opaque)
1060{
Anthony Liguoric227f092009-10-01 16:12:16 -05001061 openpic_t *opp = (openpic_t *)opaque;
blueswir167b55782009-02-06 21:30:02 +00001062 unsigned int i;
1063
1064 qemu_put_be32s(f, &opp->frep);
1065 qemu_put_be32s(f, &opp->glbc);
1066 qemu_put_be32s(f, &opp->micr);
1067 qemu_put_be32s(f, &opp->veni);
1068 qemu_put_be32s(f, &opp->pint);
1069 qemu_put_be32s(f, &opp->spve);
1070 qemu_put_be32s(f, &opp->tifr);
1071
aurel32b7169912009-03-02 16:42:04 +00001072 for (i = 0; i < opp->max_irq; i++) {
blueswir167b55782009-02-06 21:30:02 +00001073 qemu_put_be32s(f, &opp->src[i].ipvp);
1074 qemu_put_be32s(f, &opp->src[i].ide);
1075 qemu_put_sbe32s(f, &opp->src[i].type);
1076 qemu_put_sbe32s(f, &opp->src[i].last_cpu);
1077 qemu_put_sbe32s(f, &opp->src[i].pending);
1078 }
1079
aurel32b7169912009-03-02 16:42:04 +00001080 qemu_put_sbe32s(f, &opp->nb_cpus);
1081
1082 for (i = 0; i < opp->nb_cpus; i++) {
1083 qemu_put_be32s(f, &opp->dst[i].tfrr);
blueswir167b55782009-02-06 21:30:02 +00001084 qemu_put_be32s(f, &opp->dst[i].pctp);
1085 qemu_put_be32s(f, &opp->dst[i].pcsr);
1086 openpic_save_IRQ_queue(f, &opp->dst[i].raised);
1087 openpic_save_IRQ_queue(f, &opp->dst[i].servicing);
1088 }
1089
blueswir167b55782009-02-06 21:30:02 +00001090 for (i = 0; i < MAX_TMR; i++) {
1091 qemu_put_be32s(f, &opp->timers[i].ticc);
1092 qemu_put_be32s(f, &opp->timers[i].tibc);
1093 }
1094
1095#if MAX_DBL > 0
1096 qemu_put_be32s(f, &opp->dar);
1097
1098 for (i = 0; i < MAX_DBL; i++) {
1099 qemu_put_be32s(f, &opp->doorbells[i].dmr);
1100 }
1101#endif
1102
1103#if MAX_MBX > 0
1104 for (i = 0; i < MAX_MAILBOXES; i++) {
1105 qemu_put_be32s(f, &opp->mailboxes[i].mbr);
1106 }
1107#endif
1108
1109 pci_device_save(&opp->pci_dev, f);
1110}
1111
Anthony Liguoric227f092009-10-01 16:12:16 -05001112static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
blueswir167b55782009-02-06 21:30:02 +00001113{
1114 unsigned int i;
1115
1116 for (i = 0; i < BF_WIDTH(MAX_IRQ); i++)
1117 qemu_get_be32s(f, &q->queue[i]);
1118
1119 qemu_get_sbe32s(f, &q->next);
1120 qemu_get_sbe32s(f, &q->priority);
1121}
1122
1123static int openpic_load(QEMUFile* f, void *opaque, int version_id)
1124{
Anthony Liguoric227f092009-10-01 16:12:16 -05001125 openpic_t *opp = (openpic_t *)opaque;
blueswir167b55782009-02-06 21:30:02 +00001126 unsigned int i;
1127
1128 if (version_id != 1)
1129 return -EINVAL;
1130
1131 qemu_get_be32s(f, &opp->frep);
1132 qemu_get_be32s(f, &opp->glbc);
1133 qemu_get_be32s(f, &opp->micr);
1134 qemu_get_be32s(f, &opp->veni);
1135 qemu_get_be32s(f, &opp->pint);
1136 qemu_get_be32s(f, &opp->spve);
1137 qemu_get_be32s(f, &opp->tifr);
1138
aurel32b7169912009-03-02 16:42:04 +00001139 for (i = 0; i < opp->max_irq; i++) {
blueswir167b55782009-02-06 21:30:02 +00001140 qemu_get_be32s(f, &opp->src[i].ipvp);
1141 qemu_get_be32s(f, &opp->src[i].ide);
1142 qemu_get_sbe32s(f, &opp->src[i].type);
1143 qemu_get_sbe32s(f, &opp->src[i].last_cpu);
1144 qemu_get_sbe32s(f, &opp->src[i].pending);
1145 }
1146
aurel32b7169912009-03-02 16:42:04 +00001147 qemu_get_sbe32s(f, &opp->nb_cpus);
1148
1149 for (i = 0; i < opp->nb_cpus; i++) {
1150 qemu_get_be32s(f, &opp->dst[i].tfrr);
blueswir167b55782009-02-06 21:30:02 +00001151 qemu_get_be32s(f, &opp->dst[i].pctp);
1152 qemu_get_be32s(f, &opp->dst[i].pcsr);
1153 openpic_load_IRQ_queue(f, &opp->dst[i].raised);
1154 openpic_load_IRQ_queue(f, &opp->dst[i].servicing);
1155 }
1156
blueswir167b55782009-02-06 21:30:02 +00001157 for (i = 0; i < MAX_TMR; i++) {
1158 qemu_get_be32s(f, &opp->timers[i].ticc);
1159 qemu_get_be32s(f, &opp->timers[i].tibc);
1160 }
1161
1162#if MAX_DBL > 0
1163 qemu_get_be32s(f, &opp->dar);
1164
1165 for (i = 0; i < MAX_DBL; i++) {
1166 qemu_get_be32s(f, &opp->doorbells[i].dmr);
1167 }
1168#endif
1169
1170#if MAX_MBX > 0
1171 for (i = 0; i < MAX_MAILBOXES; i++) {
1172 qemu_get_be32s(f, &opp->mailboxes[i].mbr);
1173 }
1174#endif
1175
1176 return pci_device_load(&opp->pci_dev, f);
1177}
1178
Anthony Liguoric227f092009-10-01 16:12:16 -05001179static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
aurel32b7169912009-03-02 16:42:04 +00001180{
1181 qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
1182}
1183
Anthony Liguori8a5faa12011-12-21 16:18:02 -06001184qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
j_mayere9df0142007-04-09 22:45:36 +00001185 qemu_irq **irqs, qemu_irq irq_out)
bellarddbda8082004-06-15 21:38:40 +00001186{
Anthony Liguoric227f092009-10-01 16:12:16 -05001187 openpic_t *opp;
bellarddbda8082004-06-15 21:38:40 +00001188 int i, m;
ths3b46e622007-09-17 08:09:54 +00001189
bellarddbda8082004-06-15 21:38:40 +00001190 /* XXX: for now, only one CPU is supported */
1191 if (nb_cpus != 1)
1192 return NULL;
Anthony Liguori8a5faa12011-12-21 16:18:02 -06001193 opp = g_malloc0(sizeof(openpic_t));
1194 memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000);
ths3b46e622007-09-17 08:09:54 +00001195
bellard91d848e2004-06-21 22:46:48 +00001196 // isu_base &= 0xFFFC0000;
bellarddbda8082004-06-15 21:38:40 +00001197 opp->nb_cpus = nb_cpus;
aurel32b7169912009-03-02 16:42:04 +00001198 opp->max_irq = OPENPIC_MAX_IRQ;
1199 opp->irq_ipi0 = OPENPIC_IRQ_IPI0;
1200 opp->irq_tim0 = OPENPIC_IRQ_TIM0;
bellarddbda8082004-06-15 21:38:40 +00001201 /* Set IRQ types */
aurel32b7169912009-03-02 16:42:04 +00001202 for (i = 0; i < OPENPIC_EXT_IRQ; i++) {
bellarddbda8082004-06-15 21:38:40 +00001203 opp->src[i].type = IRQ_EXTERNAL;
1204 }
aurel32b7169912009-03-02 16:42:04 +00001205 for (; i < OPENPIC_IRQ_TIM0; i++) {
bellarddbda8082004-06-15 21:38:40 +00001206 opp->src[i].type = IRQ_SPECIAL;
1207 }
1208#if MAX_IPI > 0
aurel32b7169912009-03-02 16:42:04 +00001209 m = OPENPIC_IRQ_IPI0;
bellarddbda8082004-06-15 21:38:40 +00001210#else
aurel32b7169912009-03-02 16:42:04 +00001211 m = OPENPIC_IRQ_DBL0;
bellarddbda8082004-06-15 21:38:40 +00001212#endif
1213 for (; i < m; i++) {
1214 opp->src[i].type = IRQ_TIMER;
1215 }
aurel32b7169912009-03-02 16:42:04 +00001216 for (; i < OPENPIC_MAX_IRQ; i++) {
bellarddbda8082004-06-15 21:38:40 +00001217 opp->src[i].type = IRQ_INTERNAL;
1218 }
bellard7668a272005-11-23 21:13:45 +00001219 for (i = 0; i < nb_cpus; i++)
j_mayere9df0142007-04-09 22:45:36 +00001220 opp->dst[i].irqs = irqs[i];
1221 opp->irq_out = irq_out;
blueswir167b55782009-02-06 21:30:02 +00001222
Alex Williamson0be71e32010-06-25 11:09:07 -06001223 register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,
1224 openpic_save, openpic_load, opp);
Jan Kiszkaa08d4362009-06-27 09:25:07 +02001225 qemu_register_reset(openpic_reset, opp);
aurel32b7169912009-03-02 16:42:04 +00001226
1227 opp->irq_raise = openpic_irq_raise;
1228 opp->reset = openpic_reset;
1229
Avi Kivity23c5e4c2011-08-08 16:09:17 +03001230 if (pmem)
1231 *pmem = &opp->mem;
j_mayere9df0142007-04-09 22:45:36 +00001232
aurel32b7169912009-03-02 16:42:04 +00001233 return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
1234}
1235
Anthony Liguoric227f092009-10-01 16:12:16 -05001236static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
aurel32b7169912009-03-02 16:42:04 +00001237{
1238 int n_ci = IDR_CI0 - n_CPU;
Blue Swirl0bf9e312009-07-20 17:19:25 +00001239
aurel32b7169912009-03-02 16:42:04 +00001240 if(test_bit(&src->ide, n_ci)) {
1241 qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
1242 }
1243 else {
1244 qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
1245 }
1246}
1247
1248static void mpic_reset (void *opaque)
1249{
Anthony Liguoric227f092009-10-01 16:12:16 -05001250 openpic_t *mpp = (openpic_t *)opaque;
aurel32b7169912009-03-02 16:42:04 +00001251 int i;
1252
1253 mpp->glbc = 0x80000000;
1254 /* Initialise controller registers */
Alexander Grafbbc58422011-07-21 01:39:46 +02001255 mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8);
aurel32b7169912009-03-02 16:42:04 +00001256 mpp->veni = VENI;
1257 mpp->pint = 0x00000000;
1258 mpp->spve = 0x0000FFFF;
1259 /* Initialise IRQ sources */
1260 for (i = 0; i < mpp->max_irq; i++) {
1261 mpp->src[i].ipvp = 0x80800000;
1262 mpp->src[i].ide = 0x00000001;
1263 }
Alexander Graf9250fd22011-07-23 11:05:35 +02001264 /* Set IDE for IPIs to 0 so we don't get spurious interrupts */
1265 for (i = mpp->irq_ipi0; i < (mpp->irq_ipi0 + MAX_IPI); i++) {
1266 mpp->src[i].ide = 0;
1267 }
aurel32b7169912009-03-02 16:42:04 +00001268 /* Initialise IRQ destinations */
1269 for (i = 0; i < MAX_CPU; i++) {
1270 mpp->dst[i].pctp = 0x0000000F;
1271 mpp->dst[i].tfrr = 0x00000000;
Anthony Liguoric227f092009-10-01 16:12:16 -05001272 memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t));
aurel32b7169912009-03-02 16:42:04 +00001273 mpp->dst[i].raised.next = -1;
Anthony Liguoric227f092009-10-01 16:12:16 -05001274 memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
aurel32b7169912009-03-02 16:42:04 +00001275 mpp->dst[i].servicing.next = -1;
1276 }
1277 /* Initialise timers */
1278 for (i = 0; i < MAX_TMR; i++) {
1279 mpp->timers[i].ticc = 0x00000000;
1280 mpp->timers[i].tibc = 0x80000000;
1281 }
1282 /* Go out of RESET state */
1283 mpp->glbc = 0x00000000;
1284}
1285
Anthony Liguoric227f092009-10-01 16:12:16 -05001286static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t val)
aurel32b7169912009-03-02 16:42:04 +00001287{
Anthony Liguoric227f092009-10-01 16:12:16 -05001288 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001289 int idx, cpu;
1290
Blue Swirl0bf9e312009-07-20 17:19:25 +00001291 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
aurel32b7169912009-03-02 16:42:04 +00001292 if (addr & 0xF)
1293 return;
1294 addr &= 0xFFFF;
1295 cpu = addr >> 12;
1296 idx = (addr >> 6) & 0x3;
1297 switch (addr & 0x30) {
1298 case 0x00: /* gtccr */
1299 break;
1300 case 0x10: /* gtbcr */
1301 if ((mpp->timers[idx].ticc & 0x80000000) != 0 &&
1302 (val & 0x80000000) == 0 &&
1303 (mpp->timers[idx].tibc & 0x80000000) != 0)
1304 mpp->timers[idx].ticc &= ~0x80000000;
1305 mpp->timers[idx].tibc = val;
1306 break;
1307 case 0x20: /* GTIVPR */
Alexander Graf11de8b72011-09-07 13:47:22 +02001308 write_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx, val);
aurel32b7169912009-03-02 16:42:04 +00001309 break;
1310 case 0x30: /* GTIDR & TFRR */
1311 if ((addr & 0xF0) == 0xF0)
1312 mpp->dst[cpu].tfrr = val;
1313 else
Alexander Graf11de8b72011-09-07 13:47:22 +02001314 write_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx, val);
aurel32b7169912009-03-02 16:42:04 +00001315 break;
1316 }
1317}
1318
Anthony Liguoric227f092009-10-01 16:12:16 -05001319static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
aurel32b7169912009-03-02 16:42:04 +00001320{
Anthony Liguoric227f092009-10-01 16:12:16 -05001321 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001322 uint32_t retval;
1323 int idx, cpu;
1324
Blue Swirl0bf9e312009-07-20 17:19:25 +00001325 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
aurel32b7169912009-03-02 16:42:04 +00001326 retval = 0xFFFFFFFF;
1327 if (addr & 0xF)
1328 return retval;
1329 addr &= 0xFFFF;
1330 cpu = addr >> 12;
1331 idx = (addr >> 6) & 0x3;
1332 switch (addr & 0x30) {
1333 case 0x00: /* gtccr */
1334 retval = mpp->timers[idx].ticc;
1335 break;
1336 case 0x10: /* gtbcr */
1337 retval = mpp->timers[idx].tibc;
1338 break;
1339 case 0x20: /* TIPV */
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001340 retval = read_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx);
aurel32b7169912009-03-02 16:42:04 +00001341 break;
1342 case 0x30: /* TIDR */
1343 if ((addr &0xF0) == 0XF0)
1344 retval = mpp->dst[cpu].tfrr;
1345 else
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001346 retval = read_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx);
aurel32b7169912009-03-02 16:42:04 +00001347 break;
1348 }
1349 DPRINTF("%s: => %08x\n", __func__, retval);
1350
1351 return retval;
1352}
1353
Anthony Liguoric227f092009-10-01 16:12:16 -05001354static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
aurel32b7169912009-03-02 16:42:04 +00001355 uint32_t val)
1356{
Anthony Liguoric227f092009-10-01 16:12:16 -05001357 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001358 int idx = MPIC_EXT_IRQ;
1359
Blue Swirl0bf9e312009-07-20 17:19:25 +00001360 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
aurel32b7169912009-03-02 16:42:04 +00001361 if (addr & 0xF)
1362 return;
1363
Blue Swirl5c4532e2010-03-29 19:23:59 +00001364 addr -= MPIC_EXT_REG_START & (OPENPIC_PAGE_SIZE - 1);
aurel32b7169912009-03-02 16:42:04 +00001365 if (addr < MPIC_EXT_REG_SIZE) {
1366 idx += (addr & 0xFFF0) >> 5;
1367 if (addr & 0x10) {
1368 /* EXDE / IFEDE / IEEDE */
Alexander Graf11de8b72011-09-07 13:47:22 +02001369 write_IRQreg_ide(mpp, idx, val);
aurel32b7169912009-03-02 16:42:04 +00001370 } else {
1371 /* EXVP / IFEVP / IEEVP */
Alexander Graf11de8b72011-09-07 13:47:22 +02001372 write_IRQreg_ipvp(mpp, idx, val);
aurel32b7169912009-03-02 16:42:04 +00001373 }
1374 }
1375}
1376
Anthony Liguoric227f092009-10-01 16:12:16 -05001377static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
aurel32b7169912009-03-02 16:42:04 +00001378{
Anthony Liguoric227f092009-10-01 16:12:16 -05001379 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001380 uint32_t retval;
1381 int idx = MPIC_EXT_IRQ;
1382
Blue Swirl0bf9e312009-07-20 17:19:25 +00001383 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
aurel32b7169912009-03-02 16:42:04 +00001384 retval = 0xFFFFFFFF;
1385 if (addr & 0xF)
1386 return retval;
1387
Blue Swirl5c4532e2010-03-29 19:23:59 +00001388 addr -= MPIC_EXT_REG_START & (OPENPIC_PAGE_SIZE - 1);
aurel32b7169912009-03-02 16:42:04 +00001389 if (addr < MPIC_EXT_REG_SIZE) {
1390 idx += (addr & 0xFFF0) >> 5;
1391 if (addr & 0x10) {
1392 /* EXDE / IFEDE / IEEDE */
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001393 retval = read_IRQreg_ide(mpp, idx);
aurel32b7169912009-03-02 16:42:04 +00001394 } else {
1395 /* EXVP / IFEVP / IEEVP */
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001396 retval = read_IRQreg_ipvp(mpp, idx);
aurel32b7169912009-03-02 16:42:04 +00001397 }
1398 DPRINTF("%s: => %08x\n", __func__, retval);
1399 }
1400
1401 return retval;
1402}
1403
Anthony Liguoric227f092009-10-01 16:12:16 -05001404static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
aurel32b7169912009-03-02 16:42:04 +00001405 uint32_t val)
1406{
Anthony Liguoric227f092009-10-01 16:12:16 -05001407 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001408 int idx = MPIC_INT_IRQ;
1409
Blue Swirl0bf9e312009-07-20 17:19:25 +00001410 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
aurel32b7169912009-03-02 16:42:04 +00001411 if (addr & 0xF)
1412 return;
1413
Blue Swirl5c4532e2010-03-29 19:23:59 +00001414 addr -= MPIC_INT_REG_START & (OPENPIC_PAGE_SIZE - 1);
aurel32b7169912009-03-02 16:42:04 +00001415 if (addr < MPIC_INT_REG_SIZE) {
1416 idx += (addr & 0xFFF0) >> 5;
1417 if (addr & 0x10) {
1418 /* EXDE / IFEDE / IEEDE */
Alexander Graf11de8b72011-09-07 13:47:22 +02001419 write_IRQreg_ide(mpp, idx, val);
aurel32b7169912009-03-02 16:42:04 +00001420 } else {
1421 /* EXVP / IFEVP / IEEVP */
Alexander Graf11de8b72011-09-07 13:47:22 +02001422 write_IRQreg_ipvp(mpp, idx, val);
aurel32b7169912009-03-02 16:42:04 +00001423 }
1424 }
1425}
1426
Anthony Liguoric227f092009-10-01 16:12:16 -05001427static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
aurel32b7169912009-03-02 16:42:04 +00001428{
Anthony Liguoric227f092009-10-01 16:12:16 -05001429 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001430 uint32_t retval;
1431 int idx = MPIC_INT_IRQ;
1432
Blue Swirl0bf9e312009-07-20 17:19:25 +00001433 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
aurel32b7169912009-03-02 16:42:04 +00001434 retval = 0xFFFFFFFF;
1435 if (addr & 0xF)
1436 return retval;
1437
Blue Swirl5c4532e2010-03-29 19:23:59 +00001438 addr -= MPIC_INT_REG_START & (OPENPIC_PAGE_SIZE - 1);
aurel32b7169912009-03-02 16:42:04 +00001439 if (addr < MPIC_INT_REG_SIZE) {
1440 idx += (addr & 0xFFF0) >> 5;
1441 if (addr & 0x10) {
1442 /* EXDE / IFEDE / IEEDE */
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001443 retval = read_IRQreg_ide(mpp, idx);
aurel32b7169912009-03-02 16:42:04 +00001444 } else {
1445 /* EXVP / IFEVP / IEEVP */
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001446 retval = read_IRQreg_ipvp(mpp, idx);
aurel32b7169912009-03-02 16:42:04 +00001447 }
1448 DPRINTF("%s: => %08x\n", __func__, retval);
1449 }
1450
1451 return retval;
1452}
1453
Anthony Liguoric227f092009-10-01 16:12:16 -05001454static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
aurel32b7169912009-03-02 16:42:04 +00001455 uint32_t val)
1456{
Anthony Liguoric227f092009-10-01 16:12:16 -05001457 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001458 int idx = MPIC_MSG_IRQ;
1459
Blue Swirl0bf9e312009-07-20 17:19:25 +00001460 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
aurel32b7169912009-03-02 16:42:04 +00001461 if (addr & 0xF)
1462 return;
1463
Blue Swirl5c4532e2010-03-29 19:23:59 +00001464 addr -= MPIC_MSG_REG_START & (OPENPIC_PAGE_SIZE - 1);
aurel32b7169912009-03-02 16:42:04 +00001465 if (addr < MPIC_MSG_REG_SIZE) {
1466 idx += (addr & 0xFFF0) >> 5;
1467 if (addr & 0x10) {
1468 /* EXDE / IFEDE / IEEDE */
Alexander Graf11de8b72011-09-07 13:47:22 +02001469 write_IRQreg_ide(mpp, idx, val);
aurel32b7169912009-03-02 16:42:04 +00001470 } else {
1471 /* EXVP / IFEVP / IEEVP */
Alexander Graf11de8b72011-09-07 13:47:22 +02001472 write_IRQreg_ipvp(mpp, idx, val);
aurel32b7169912009-03-02 16:42:04 +00001473 }
1474 }
1475}
1476
Anthony Liguoric227f092009-10-01 16:12:16 -05001477static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
aurel32b7169912009-03-02 16:42:04 +00001478{
Anthony Liguoric227f092009-10-01 16:12:16 -05001479 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001480 uint32_t retval;
1481 int idx = MPIC_MSG_IRQ;
1482
Blue Swirl0bf9e312009-07-20 17:19:25 +00001483 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
aurel32b7169912009-03-02 16:42:04 +00001484 retval = 0xFFFFFFFF;
1485 if (addr & 0xF)
1486 return retval;
1487
Blue Swirl5c4532e2010-03-29 19:23:59 +00001488 addr -= MPIC_MSG_REG_START & (OPENPIC_PAGE_SIZE - 1);
aurel32b7169912009-03-02 16:42:04 +00001489 if (addr < MPIC_MSG_REG_SIZE) {
1490 idx += (addr & 0xFFF0) >> 5;
1491 if (addr & 0x10) {
1492 /* EXDE / IFEDE / IEEDE */
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001493 retval = read_IRQreg_ide(mpp, idx);
aurel32b7169912009-03-02 16:42:04 +00001494 } else {
1495 /* EXVP / IFEVP / IEEVP */
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001496 retval = read_IRQreg_ipvp(mpp, idx);
aurel32b7169912009-03-02 16:42:04 +00001497 }
1498 DPRINTF("%s: => %08x\n", __func__, retval);
1499 }
1500
1501 return retval;
1502}
1503
Anthony Liguoric227f092009-10-01 16:12:16 -05001504static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
aurel32b7169912009-03-02 16:42:04 +00001505 uint32_t val)
1506{
Anthony Liguoric227f092009-10-01 16:12:16 -05001507 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001508 int idx = MPIC_MSI_IRQ;
1509
Blue Swirl0bf9e312009-07-20 17:19:25 +00001510 DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
aurel32b7169912009-03-02 16:42:04 +00001511 if (addr & 0xF)
1512 return;
1513
Blue Swirl5c4532e2010-03-29 19:23:59 +00001514 addr -= MPIC_MSI_REG_START & (OPENPIC_PAGE_SIZE - 1);
aurel32b7169912009-03-02 16:42:04 +00001515 if (addr < MPIC_MSI_REG_SIZE) {
1516 idx += (addr & 0xFFF0) >> 5;
1517 if (addr & 0x10) {
1518 /* EXDE / IFEDE / IEEDE */
Alexander Graf11de8b72011-09-07 13:47:22 +02001519 write_IRQreg_ide(mpp, idx, val);
aurel32b7169912009-03-02 16:42:04 +00001520 } else {
1521 /* EXVP / IFEVP / IEEVP */
Alexander Graf11de8b72011-09-07 13:47:22 +02001522 write_IRQreg_ipvp(mpp, idx, val);
aurel32b7169912009-03-02 16:42:04 +00001523 }
1524 }
1525}
Anthony Liguoric227f092009-10-01 16:12:16 -05001526static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
aurel32b7169912009-03-02 16:42:04 +00001527{
Anthony Liguoric227f092009-10-01 16:12:16 -05001528 openpic_t *mpp = opaque;
aurel32b7169912009-03-02 16:42:04 +00001529 uint32_t retval;
1530 int idx = MPIC_MSI_IRQ;
1531
Blue Swirl0bf9e312009-07-20 17:19:25 +00001532 DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
aurel32b7169912009-03-02 16:42:04 +00001533 retval = 0xFFFFFFFF;
1534 if (addr & 0xF)
1535 return retval;
1536
Blue Swirl5c4532e2010-03-29 19:23:59 +00001537 addr -= MPIC_MSI_REG_START & (OPENPIC_PAGE_SIZE - 1);
aurel32b7169912009-03-02 16:42:04 +00001538 if (addr < MPIC_MSI_REG_SIZE) {
1539 idx += (addr & 0xFFF0) >> 5;
1540 if (addr & 0x10) {
1541 /* EXDE / IFEDE / IEEDE */
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001542 retval = read_IRQreg_ide(mpp, idx);
aurel32b7169912009-03-02 16:42:04 +00001543 } else {
1544 /* EXVP / IFEVP / IEEVP */
Alexander Graf8d3a8c12011-09-07 13:41:54 +02001545 retval = read_IRQreg_ipvp(mpp, idx);
aurel32b7169912009-03-02 16:42:04 +00001546 }
1547 DPRINTF("%s: => %08x\n", __func__, retval);
1548 }
1549
1550 return retval;
1551}
1552
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001553static const MemoryRegionOps mpic_glb_ops = {
1554 .old_mmio = {
1555 .write = { openpic_buggy_write,
1556 openpic_buggy_write,
1557 openpic_gbl_write,
1558 },
1559 .read = { openpic_buggy_read,
1560 openpic_buggy_read,
1561 openpic_gbl_read,
1562 },
1563 },
1564 .endianness = DEVICE_BIG_ENDIAN,
aurel32b7169912009-03-02 16:42:04 +00001565};
1566
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001567static const MemoryRegionOps mpic_tmr_ops = {
1568 .old_mmio = {
1569 .write = { openpic_buggy_write,
1570 openpic_buggy_write,
1571 mpic_timer_write,
1572 },
1573 .read = { openpic_buggy_read,
1574 openpic_buggy_read,
1575 mpic_timer_read,
1576 },
1577 },
1578 .endianness = DEVICE_BIG_ENDIAN,
aurel32b7169912009-03-02 16:42:04 +00001579};
1580
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001581static const MemoryRegionOps mpic_cpu_ops = {
1582 .old_mmio = {
1583 .write = { openpic_buggy_write,
1584 openpic_buggy_write,
1585 openpic_cpu_write,
1586 },
1587 .read = { openpic_buggy_read,
1588 openpic_buggy_read,
1589 openpic_cpu_read,
1590 },
1591 },
1592 .endianness = DEVICE_BIG_ENDIAN,
aurel32b7169912009-03-02 16:42:04 +00001593};
1594
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001595static const MemoryRegionOps mpic_ext_ops = {
1596 .old_mmio = {
1597 .write = { openpic_buggy_write,
1598 openpic_buggy_write,
1599 mpic_src_ext_write,
1600 },
1601 .read = { openpic_buggy_read,
1602 openpic_buggy_read,
1603 mpic_src_ext_read,
1604 },
1605 },
1606 .endianness = DEVICE_BIG_ENDIAN,
aurel32b7169912009-03-02 16:42:04 +00001607};
1608
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001609static const MemoryRegionOps mpic_int_ops = {
1610 .old_mmio = {
1611 .write = { openpic_buggy_write,
1612 openpic_buggy_write,
1613 mpic_src_int_write,
1614 },
1615 .read = { openpic_buggy_read,
1616 openpic_buggy_read,
1617 mpic_src_int_read,
1618 },
1619 },
1620 .endianness = DEVICE_BIG_ENDIAN,
aurel32b7169912009-03-02 16:42:04 +00001621};
1622
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001623static const MemoryRegionOps mpic_msg_ops = {
1624 .old_mmio = {
1625 .write = { openpic_buggy_write,
1626 openpic_buggy_write,
1627 mpic_src_msg_write,
1628 },
1629 .read = { openpic_buggy_read,
1630 openpic_buggy_read,
1631 mpic_src_msg_read,
1632 },
1633 },
1634 .endianness = DEVICE_BIG_ENDIAN,
aurel32b7169912009-03-02 16:42:04 +00001635};
1636
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001637static const MemoryRegionOps mpic_msi_ops = {
1638 .old_mmio = {
1639 .write = { openpic_buggy_write,
1640 openpic_buggy_write,
1641 mpic_src_msi_write,
1642 },
1643 .read = { openpic_buggy_read,
1644 openpic_buggy_read,
1645 mpic_src_msi_read,
1646 },
1647 },
1648 .endianness = DEVICE_BIG_ENDIAN,
aurel32b7169912009-03-02 16:42:04 +00001649};
1650
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001651qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
1652 int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
aurel32b7169912009-03-02 16:42:04 +00001653{
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001654 openpic_t *mpp;
1655 int i;
aurel32b7169912009-03-02 16:42:04 +00001656 struct {
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001657 const char *name;
1658 MemoryRegionOps const *ops;
1659 target_phys_addr_t start_addr;
1660 ram_addr_t size;
aurel32dfebf622009-03-02 16:42:14 +00001661 } const list[] = {
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001662 {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
1663 {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
1664 {"ext", &mpic_ext_ops, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
1665 {"int", &mpic_int_ops, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
1666 {"msg", &mpic_msg_ops, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
1667 {"msi", &mpic_msi_ops, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
1668 {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
aurel32b7169912009-03-02 16:42:04 +00001669 };
1670
Anthony Liguori7267c092011-08-20 22:09:37 -05001671 mpp = g_malloc0(sizeof(openpic_t));
aurel32b7169912009-03-02 16:42:04 +00001672
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001673 memory_region_init(&mpp->mem, "mpic", 0x40000);
1674 memory_region_add_subregion(address_space, base, &mpp->mem);
aurel32b7169912009-03-02 16:42:04 +00001675
Fabien Chouteau71cf9e62011-08-30 17:46:26 +02001676 for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
1677
1678 memory_region_init_io(&mpp->sub_io_mem[i], list[i].ops, mpp,
1679 list[i].name, list[i].size);
1680
1681 memory_region_add_subregion(&mpp->mem, list[i].start_addr,
1682 &mpp->sub_io_mem[i]);
aurel32b7169912009-03-02 16:42:04 +00001683 }
1684
1685 mpp->nb_cpus = nb_cpus;
1686 mpp->max_irq = MPIC_MAX_IRQ;
1687 mpp->irq_ipi0 = MPIC_IPI_IRQ;
1688 mpp->irq_tim0 = MPIC_TMR_IRQ;
1689
1690 for (i = 0; i < nb_cpus; i++)
1691 mpp->dst[i].irqs = irqs[i];
1692 mpp->irq_out = irq_out;
aurel32b7169912009-03-02 16:42:04 +00001693
1694 mpp->irq_raise = mpic_irq_raise;
1695 mpp->reset = mpic_reset;
1696
Alex Williamson0be71e32010-06-25 11:09:07 -06001697 register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
Jan Kiszkaa08d4362009-06-27 09:25:07 +02001698 qemu_register_reset(mpic_reset, mpp);
aurel32b7169912009-03-02 16:42:04 +00001699
1700 return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
bellarddbda8082004-06-15 21:38:40 +00001701}