blob: 19982f2477a48eb95339377b9f2452bf3ec016b3 [file] [log] [blame]
Mathieu Sonetd028d022011-10-28 10:55:37 +01001/*
2 * Arm PrimeCell PL041 Advanced Audio Codec Interface
3 *
4 * Copyright (c) 2011
5 * Written by Mathieu Sonet - www.elasticsheep.com
6 *
Stefan Weil4d8db4e2011-12-10 00:19:43 +01007 * This code is licensed under the GPL.
Mathieu Sonetd028d022011-10-28 10:55:37 +01008 *
9 * *****************************************************************
10 *
11 * This driver emulates the ARM AACI interface
12 * connected to a LM4549 codec.
13 *
14 * Limitations:
15 * - Supports only a playback on one channel (Versatile/Vexpress)
16 * - Supports only one TX FIFO in compact-mode or non-compact mode.
17 * - Supports playback of 12, 16, 18 and 20 bits samples.
18 * - Record is not supported.
19 * - The PL041 is hardwired to a LM4549 codec.
20 *
21 */
22
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010023#include "hw/sysbus.h"
Mathieu Sonetd028d022011-10-28 10:55:37 +010024
Paolo Bonzini47b43a12013-03-18 17:36:02 +010025#include "pl041.h"
26#include "lm4549.h"
Mathieu Sonetd028d022011-10-28 10:55:37 +010027
28#if 0
29#define PL041_DEBUG_LEVEL 1
30#endif
31
32#if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 1)
33#define DBG_L1(fmt, ...) \
34do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0)
35#else
36#define DBG_L1(fmt, ...) \
37do { } while (0)
38#endif
39
40#if defined(PL041_DEBUG_LEVEL) && (PL041_DEBUG_LEVEL >= 2)
41#define DBG_L2(fmt, ...) \
42do { printf("pl041: " fmt , ## __VA_ARGS__); } while (0)
43#else
44#define DBG_L2(fmt, ...) \
45do { } while (0)
46#endif
47
48
49#define MAX_FIFO_DEPTH (1024)
50#define DEFAULT_FIFO_DEPTH (8)
51
52#define SLOT1_RW (1 << 19)
53
54/* This FIFO only stores 20-bit samples on 32-bit words.
55 So its level is independent of the selected mode */
56typedef struct {
57 uint32_t level;
58 uint32_t data[MAX_FIFO_DEPTH];
59} pl041_fifo;
60
61typedef struct {
62 pl041_fifo tx_fifo;
63 uint8_t tx_enabled;
64 uint8_t tx_compact_mode;
65 uint8_t tx_sample_size;
66
67 pl041_fifo rx_fifo;
68 uint8_t rx_enabled;
69 uint8_t rx_compact_mode;
70 uint8_t rx_sample_size;
71} pl041_channel;
72
Andreas Färberb354f032013-07-24 10:19:32 +020073#define TYPE_PL041 "pl041"
74#define PL041(obj) OBJECT_CHECK(PL041State, (obj), TYPE_PL041)
75
Andreas Färberbaae6722013-07-27 19:45:52 +020076typedef struct PL041State {
Andreas Färberb354f032013-07-24 10:19:32 +020077 SysBusDevice parent_obj;
78
Mathieu Sonetd028d022011-10-28 10:55:37 +010079 MemoryRegion iomem;
80 qemu_irq irq;
81
82 uint32_t fifo_depth; /* FIFO depth in non-compact mode */
83
84 pl041_regfile regs;
85 pl041_channel fifo1;
86 lm4549_state codec;
Andreas Färberbaae6722013-07-27 19:45:52 +020087} PL041State;
Mathieu Sonetd028d022011-10-28 10:55:37 +010088
89
90static const unsigned char pl041_default_id[8] = {
91 0x41, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
92};
93
94#if defined(PL041_DEBUG_LEVEL)
95#define REGISTER(name, offset) #name,
96static const char *pl041_regs_name[] = {
97 #include "pl041.hx"
98};
99#undef REGISTER
100#endif
101
102
103#if defined(PL041_DEBUG_LEVEL)
Avi Kivitya8170e52012-10-23 12:30:10 +0200104static const char *get_reg_name(hwaddr offset)
Mathieu Sonetd028d022011-10-28 10:55:37 +0100105{
106 if (offset <= PL041_dr1_7) {
107 return pl041_regs_name[offset >> 2];
108 }
109
110 return "unknown";
111}
112#endif
113
Andreas Färberbaae6722013-07-27 19:45:52 +0200114static uint8_t pl041_compute_periphid3(PL041State *s)
Mathieu Sonetd028d022011-10-28 10:55:37 +0100115{
116 uint8_t id3 = 1; /* One channel */
117
118 /* Add the fifo depth information */
119 switch (s->fifo_depth) {
120 case 8:
121 id3 |= 0 << 3;
122 break;
123 case 32:
124 id3 |= 1 << 3;
125 break;
126 case 64:
127 id3 |= 2 << 3;
128 break;
129 case 128:
130 id3 |= 3 << 3;
131 break;
132 case 256:
133 id3 |= 4 << 3;
134 break;
135 case 512:
136 id3 |= 5 << 3;
137 break;
138 case 1024:
139 id3 |= 6 << 3;
140 break;
141 case 2048:
142 id3 |= 7 << 3;
143 break;
144 }
145
146 return id3;
147}
148
Andreas Färberbaae6722013-07-27 19:45:52 +0200149static void pl041_reset(PL041State *s)
Mathieu Sonetd028d022011-10-28 10:55:37 +0100150{
151 DBG_L1("pl041_reset\n");
152
153 memset(&s->regs, 0x00, sizeof(pl041_regfile));
154
155 s->regs.slfr = SL1TXEMPTY | SL2TXEMPTY | SL12TXEMPTY;
156 s->regs.sr1 = TXFE | RXFE | TXHE;
157 s->regs.isr1 = 0;
158
159 memset(&s->fifo1, 0x00, sizeof(s->fifo1));
160}
161
162
Andreas Färberbaae6722013-07-27 19:45:52 +0200163static void pl041_fifo1_write(PL041State *s, uint32_t value)
Mathieu Sonetd028d022011-10-28 10:55:37 +0100164{
165 pl041_channel *channel = &s->fifo1;
166 pl041_fifo *fifo = &s->fifo1.tx_fifo;
167
168 /* Push the value in the FIFO */
169 if (channel->tx_compact_mode == 0) {
170 /* Non-compact mode */
171
172 if (fifo->level < s->fifo_depth) {
173 /* Pad the value with 0 to obtain a 20-bit sample */
174 switch (channel->tx_sample_size) {
175 case 12:
176 value = (value << 8) & 0xFFFFF;
177 break;
178 case 16:
179 value = (value << 4) & 0xFFFFF;
180 break;
181 case 18:
182 value = (value << 2) & 0xFFFFF;
183 break;
184 case 20:
185 default:
186 break;
187 }
188
189 /* Store the sample in the FIFO */
190 fifo->data[fifo->level++] = value;
191 }
192#if defined(PL041_DEBUG_LEVEL)
193 else {
194 DBG_L1("fifo1 write: overrun\n");
195 }
196#endif
197 } else {
198 /* Compact mode */
199
200 if ((fifo->level + 2) < s->fifo_depth) {
201 uint32_t i = 0;
202 uint32_t sample = 0;
203
204 for (i = 0; i < 2; i++) {
205 sample = value & 0xFFFF;
206 value = value >> 16;
207
208 /* Pad each sample with 0 to obtain a 20-bit sample */
209 switch (channel->tx_sample_size) {
210 case 12:
211 sample = sample << 8;
212 break;
213 case 16:
214 default:
215 sample = sample << 4;
216 break;
217 }
218
219 /* Store the sample in the FIFO */
220 fifo->data[fifo->level++] = sample;
221 }
222 }
223#if defined(PL041_DEBUG_LEVEL)
224 else {
225 DBG_L1("fifo1 write: overrun\n");
226 }
227#endif
228 }
229
230 /* Update the status register */
231 if (fifo->level > 0) {
232 s->regs.sr1 &= ~(TXUNDERRUN | TXFE);
233 }
234
235 if (fifo->level >= (s->fifo_depth / 2)) {
236 s->regs.sr1 &= ~TXHE;
237 }
238
239 if (fifo->level >= s->fifo_depth) {
240 s->regs.sr1 |= TXFF;
241 }
242
243 DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1);
244}
245
Andreas Färberbaae6722013-07-27 19:45:52 +0200246static void pl041_fifo1_transmit(PL041State *s)
Mathieu Sonetd028d022011-10-28 10:55:37 +0100247{
248 pl041_channel *channel = &s->fifo1;
249 pl041_fifo *fifo = &s->fifo1.tx_fifo;
250 uint32_t slots = s->regs.txcr1 & TXSLOT_MASK;
251 uint32_t written_samples;
252
253 /* Check if FIFO1 transmit is enabled */
254 if ((channel->tx_enabled) && (slots & (TXSLOT3 | TXSLOT4))) {
255 if (fifo->level >= (s->fifo_depth / 2)) {
256 int i;
257
258 DBG_L1("Transfer FIFO level = %i\n", fifo->level);
259
260 /* Try to transfer the whole FIFO */
261 for (i = 0; i < (fifo->level / 2); i++) {
262 uint32_t left = fifo->data[i * 2];
263 uint32_t right = fifo->data[i * 2 + 1];
264
265 /* Transmit two 20-bit samples to the codec */
266 if (lm4549_write_samples(&s->codec, left, right) == 0) {
267 DBG_L1("Codec buffer full\n");
268 break;
269 }
270 }
271
272 written_samples = i * 2;
273 if (written_samples > 0) {
274 /* Update the FIFO level */
275 fifo->level -= written_samples;
276
277 /* Move back the pending samples to the start of the FIFO */
278 for (i = 0; i < fifo->level; i++) {
279 fifo->data[i] = fifo->data[written_samples + i];
280 }
281
282 /* Update the status register */
283 s->regs.sr1 &= ~TXFF;
284
285 if (fifo->level <= (s->fifo_depth / 2)) {
286 s->regs.sr1 |= TXHE;
287 }
288
289 if (fifo->level == 0) {
290 s->regs.sr1 |= TXFE | TXUNDERRUN;
291 DBG_L1("Empty FIFO\n");
292 }
293 }
294 }
295 }
296}
297
Andreas Färberbaae6722013-07-27 19:45:52 +0200298static void pl041_isr1_update(PL041State *s)
Mathieu Sonetd028d022011-10-28 10:55:37 +0100299{
300 /* Update ISR1 */
301 if (s->regs.sr1 & TXUNDERRUN) {
302 s->regs.isr1 |= URINTR;
303 } else {
304 s->regs.isr1 &= ~URINTR;
305 }
306
307 if (s->regs.sr1 & TXHE) {
308 s->regs.isr1 |= TXINTR;
309 } else {
310 s->regs.isr1 &= ~TXINTR;
311 }
312
313 if (!(s->regs.sr1 & TXBUSY) && (s->regs.sr1 & TXFE)) {
314 s->regs.isr1 |= TXCINTR;
315 } else {
316 s->regs.isr1 &= ~TXCINTR;
317 }
318
319 /* Update the irq state */
320 qemu_set_irq(s->irq, ((s->regs.isr1 & s->regs.ie1) > 0) ? 1 : 0);
321 DBG_L2("Set interrupt sr1 = 0x%08x isr1 = 0x%08x masked = 0x%08x\n",
322 s->regs.sr1, s->regs.isr1, s->regs.isr1 & s->regs.ie1);
323}
324
325static void pl041_request_data(void *opaque)
326{
Andreas Färberbaae6722013-07-27 19:45:52 +0200327 PL041State *s = (PL041State *)opaque;
Mathieu Sonetd028d022011-10-28 10:55:37 +0100328
329 /* Trigger pending transfers */
330 pl041_fifo1_transmit(s);
331 pl041_isr1_update(s);
332}
333
Avi Kivitya8170e52012-10-23 12:30:10 +0200334static uint64_t pl041_read(void *opaque, hwaddr offset,
Mathieu Sonetd028d022011-10-28 10:55:37 +0100335 unsigned size)
336{
Andreas Färberbaae6722013-07-27 19:45:52 +0200337 PL041State *s = (PL041State *)opaque;
Mathieu Sonetd028d022011-10-28 10:55:37 +0100338 int value;
339
340 if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) {
341 if (offset == PL041_periphid3) {
342 value = pl041_compute_periphid3(s);
343 } else {
344 value = pl041_default_id[(offset - PL041_periphid0) >> 2];
345 }
346
347 DBG_L1("pl041_read [0x%08x] => 0x%08x\n", offset, value);
348 return value;
349 } else if (offset <= PL041_dr4_7) {
350 value = *((uint32_t *)&s->regs + (offset >> 2));
351 } else {
352 DBG_L1("pl041_read: Reserved offset %x\n", (int)offset);
353 return 0;
354 }
355
356 switch (offset) {
357 case PL041_allints:
358 value = s->regs.isr1 & 0x7F;
359 break;
360 }
361
362 DBG_L1("pl041_read [0x%08x] %s => 0x%08x\n", offset,
363 get_reg_name(offset), value);
364
365 return value;
366}
367
Avi Kivitya8170e52012-10-23 12:30:10 +0200368static void pl041_write(void *opaque, hwaddr offset,
Mathieu Sonetd028d022011-10-28 10:55:37 +0100369 uint64_t value, unsigned size)
370{
Andreas Färberbaae6722013-07-27 19:45:52 +0200371 PL041State *s = (PL041State *)opaque;
Mathieu Sonetd028d022011-10-28 10:55:37 +0100372 uint16_t control, data;
373 uint32_t result;
374
375 DBG_L1("pl041_write [0x%08x] %s <= 0x%08x\n", offset,
376 get_reg_name(offset), (unsigned int)value);
377
378 /* Write the register */
379 if (offset <= PL041_dr4_7) {
380 *((uint32_t *)&s->regs + (offset >> 2)) = value;
381 } else {
382 DBG_L1("pl041_write: Reserved offset %x\n", (int)offset);
383 return;
384 }
385
386 /* Execute the actions */
387 switch (offset) {
388 case PL041_txcr1:
389 {
390 pl041_channel *channel = &s->fifo1;
391
392 uint32_t txen = s->regs.txcr1 & TXEN;
393 uint32_t tsize = (s->regs.txcr1 & TSIZE_MASK) >> TSIZE_MASK_BIT;
394 uint32_t compact_mode = (s->regs.txcr1 & TXCOMPACT) ? 1 : 0;
395#if defined(PL041_DEBUG_LEVEL)
396 uint32_t slots = (s->regs.txcr1 & TXSLOT_MASK) >> TXSLOT_MASK_BIT;
397 uint32_t txfen = (s->regs.txcr1 & TXFEN) > 0 ? 1 : 0;
398#endif
399
400 DBG_L1("=> txen = %i slots = 0x%01x tsize = %i compact = %i "
401 "txfen = %i\n", txen, slots, tsize, compact_mode, txfen);
402
403 channel->tx_enabled = txen;
404 channel->tx_compact_mode = compact_mode;
405
406 switch (tsize) {
407 case 0:
408 channel->tx_sample_size = 16;
409 break;
410 case 1:
411 channel->tx_sample_size = 18;
412 break;
413 case 2:
414 channel->tx_sample_size = 20;
415 break;
416 case 3:
417 channel->tx_sample_size = 12;
418 break;
419 }
420
421 DBG_L1("TX enabled = %i\n", channel->tx_enabled);
422 DBG_L1("TX compact mode = %i\n", channel->tx_compact_mode);
423 DBG_L1("TX sample width = %i\n", channel->tx_sample_size);
424
425 /* Check if compact mode is allowed with selected tsize */
426 if (channel->tx_compact_mode == 1) {
427 if ((channel->tx_sample_size == 18) ||
428 (channel->tx_sample_size == 20)) {
429 channel->tx_compact_mode = 0;
430 DBG_L1("Compact mode not allowed with 18/20-bit sample size\n");
431 }
432 }
433
434 break;
435 }
436 case PL041_sl1tx:
437 s->regs.slfr &= ~SL1TXEMPTY;
438
439 control = (s->regs.sl1tx >> 12) & 0x7F;
440 data = (s->regs.sl2tx >> 4) & 0xFFFF;
441
442 if ((s->regs.sl1tx & SLOT1_RW) == 0) {
443 /* Write operation */
444 lm4549_write(&s->codec, control, data);
445 } else {
446 /* Read operation */
447 result = lm4549_read(&s->codec, control);
448
449 /* Store the returned value */
450 s->regs.sl1rx = s->regs.sl1tx & ~SLOT1_RW;
451 s->regs.sl2rx = result << 4;
452
453 s->regs.slfr &= ~(SL1RXBUSY | SL2RXBUSY);
454 s->regs.slfr |= SL1RXVALID | SL2RXVALID;
455 }
456 break;
457
458 case PL041_sl2tx:
459 s->regs.sl2tx = value;
460 s->regs.slfr &= ~SL2TXEMPTY;
461 break;
462
463 case PL041_intclr:
464 DBG_L1("=> Clear interrupt intclr = 0x%08x isr1 = 0x%08x\n",
465 s->regs.intclr, s->regs.isr1);
466
467 if (s->regs.intclr & TXUEC1) {
468 s->regs.sr1 &= ~TXUNDERRUN;
469 }
470 break;
471
472 case PL041_maincr:
473 {
474#if defined(PL041_DEBUG_LEVEL)
475 char debug[] = " AACIFE SL1RXEN SL1TXEN";
476 if (!(value & AACIFE)) {
477 debug[0] = '!';
478 }
479 if (!(value & SL1RXEN)) {
480 debug[8] = '!';
481 }
482 if (!(value & SL1TXEN)) {
483 debug[17] = '!';
484 }
485 DBG_L1("%s\n", debug);
486#endif
487
488 if ((s->regs.maincr & AACIFE) == 0) {
489 pl041_reset(s);
490 }
491 break;
492 }
493
494 case PL041_dr1_0:
495 case PL041_dr1_1:
496 case PL041_dr1_2:
497 case PL041_dr1_3:
498 pl041_fifo1_write(s, value);
499 break;
500 }
501
502 /* Transmit the FIFO content */
503 pl041_fifo1_transmit(s);
504
505 /* Update the ISR1 register */
506 pl041_isr1_update(s);
507}
508
509static void pl041_device_reset(DeviceState *d)
510{
Andreas Färberb354f032013-07-24 10:19:32 +0200511 PL041State *s = PL041(d);
Mathieu Sonetd028d022011-10-28 10:55:37 +0100512
513 pl041_reset(s);
514}
515
516static const MemoryRegionOps pl041_ops = {
517 .read = pl041_read,
518 .write = pl041_write,
519 .endianness = DEVICE_NATIVE_ENDIAN,
520};
521
522static int pl041_init(SysBusDevice *dev)
523{
Andreas Färberb354f032013-07-24 10:19:32 +0200524 PL041State *s = PL041(dev);
Mathieu Sonetd028d022011-10-28 10:55:37 +0100525
526 DBG_L1("pl041_init 0x%08x\n", (uint32_t)s);
527
528 /* Check the device properties */
529 switch (s->fifo_depth) {
530 case 8:
531 case 32:
532 case 64:
533 case 128:
534 case 256:
535 case 512:
536 case 1024:
537 case 2048:
538 break;
539 case 16:
540 default:
541 /* NC FIFO depth of 16 is not allowed because its id bits in
542 AACIPERIPHID3 overlap with the id for the default NC FIFO depth */
Peter Maydellb1d9df92012-10-18 14:11:38 +0100543 qemu_log_mask(LOG_UNIMP,
544 "pl041: unsupported non-compact fifo depth [%i]\n",
545 s->fifo_depth);
Mathieu Sonetd028d022011-10-28 10:55:37 +0100546 return -1;
547 }
548
549 /* Connect the device to the sysbus */
Paolo Bonzini64bde0f2013-06-06 21:25:08 -0400550 memory_region_init_io(&s->iomem, OBJECT(s), &pl041_ops, s, "pl041", 0x1000);
Avi Kivity750ecd42011-11-27 11:38:10 +0200551 sysbus_init_mmio(dev, &s->iomem);
Mathieu Sonetd028d022011-10-28 10:55:37 +0100552 sysbus_init_irq(dev, &s->irq);
553
554 /* Init the codec */
555 lm4549_init(&s->codec, &pl041_request_data, (void *)s);
556
557 return 0;
558}
559
560static const VMStateDescription vmstate_pl041_regfile = {
561 .name = "pl041_regfile",
562 .version_id = 1,
563 .minimum_version_id = 1,
Juan Quintela8f1e8842014-05-13 16:09:35 +0100564 .fields = (VMStateField[]) {
Mathieu Sonetd028d022011-10-28 10:55:37 +0100565#define REGISTER(name, offset) VMSTATE_UINT32(name, pl041_regfile),
566 #include "pl041.hx"
567#undef REGISTER
568 VMSTATE_END_OF_LIST()
569 }
570};
571
572static const VMStateDescription vmstate_pl041_fifo = {
573 .name = "pl041_fifo",
574 .version_id = 1,
575 .minimum_version_id = 1,
Juan Quintela8f1e8842014-05-13 16:09:35 +0100576 .fields = (VMStateField[]) {
Mathieu Sonetd028d022011-10-28 10:55:37 +0100577 VMSTATE_UINT32(level, pl041_fifo),
578 VMSTATE_UINT32_ARRAY(data, pl041_fifo, MAX_FIFO_DEPTH),
579 VMSTATE_END_OF_LIST()
580 }
581};
582
583static const VMStateDescription vmstate_pl041_channel = {
584 .name = "pl041_channel",
585 .version_id = 1,
586 .minimum_version_id = 1,
Juan Quintela8f1e8842014-05-13 16:09:35 +0100587 .fields = (VMStateField[]) {
Mathieu Sonetd028d022011-10-28 10:55:37 +0100588 VMSTATE_STRUCT(tx_fifo, pl041_channel, 0,
589 vmstate_pl041_fifo, pl041_fifo),
590 VMSTATE_UINT8(tx_enabled, pl041_channel),
591 VMSTATE_UINT8(tx_compact_mode, pl041_channel),
592 VMSTATE_UINT8(tx_sample_size, pl041_channel),
593 VMSTATE_STRUCT(rx_fifo, pl041_channel, 0,
594 vmstate_pl041_fifo, pl041_fifo),
595 VMSTATE_UINT8(rx_enabled, pl041_channel),
596 VMSTATE_UINT8(rx_compact_mode, pl041_channel),
597 VMSTATE_UINT8(rx_sample_size, pl041_channel),
598 VMSTATE_END_OF_LIST()
599 }
600};
601
602static const VMStateDescription vmstate_pl041 = {
603 .name = "pl041",
604 .version_id = 1,
605 .minimum_version_id = 1,
606 .fields = (VMStateField[]) {
Andreas Färberbaae6722013-07-27 19:45:52 +0200607 VMSTATE_UINT32(fifo_depth, PL041State),
608 VMSTATE_STRUCT(regs, PL041State, 0,
Mathieu Sonetd028d022011-10-28 10:55:37 +0100609 vmstate_pl041_regfile, pl041_regfile),
Andreas Färberbaae6722013-07-27 19:45:52 +0200610 VMSTATE_STRUCT(fifo1, PL041State, 0,
Mathieu Sonetd028d022011-10-28 10:55:37 +0100611 vmstate_pl041_channel, pl041_channel),
Andreas Färberbaae6722013-07-27 19:45:52 +0200612 VMSTATE_STRUCT(codec, PL041State, 0,
Mathieu Sonetd028d022011-10-28 10:55:37 +0100613 vmstate_lm4549_state, lm4549_state),
614 VMSTATE_END_OF_LIST()
615 }
616};
617
Anthony Liguori999e12b2012-01-24 13:12:29 -0600618static Property pl041_device_properties[] = {
619 /* Non-compact FIFO depth property */
Andreas Färberbaae6722013-07-27 19:45:52 +0200620 DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth,
621 DEFAULT_FIFO_DEPTH),
Anthony Liguori999e12b2012-01-24 13:12:29 -0600622 DEFINE_PROP_END_OF_LIST(),
623};
624
625static void pl041_device_class_init(ObjectClass *klass, void *data)
626{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600627 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600628 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
629
630 k->init = pl041_init;
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +0300631 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
Anthony Liguori39bffca2011-12-07 21:34:16 -0600632 dc->reset = pl041_device_reset;
633 dc->vmsd = &vmstate_pl041;
634 dc->props = pl041_device_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600635}
636
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100637static const TypeInfo pl041_device_info = {
Andreas Färberb354f032013-07-24 10:19:32 +0200638 .name = TYPE_PL041,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600639 .parent = TYPE_SYS_BUS_DEVICE,
Andreas Färberbaae6722013-07-27 19:45:52 +0200640 .instance_size = sizeof(PL041State),
Anthony Liguori39bffca2011-12-07 21:34:16 -0600641 .class_init = pl041_device_class_init,
Mathieu Sonetd028d022011-10-28 10:55:37 +0100642};
643
Andreas Färber83f7d432012-02-09 15:20:55 +0100644static void pl041_register_types(void)
Mathieu Sonetd028d022011-10-28 10:55:37 +0100645{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600646 type_register_static(&pl041_device_info);
Mathieu Sonetd028d022011-10-28 10:55:37 +0100647}
648
Andreas Färber83f7d432012-02-09 15:20:55 +0100649type_init(pl041_register_types)