Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 1 | /* |
| 2 | * x86 SVM helpers |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
Peter Maydell | b6a0aa0 | 2016-01-26 18:17:03 +0000 | [diff] [blame] | 20 | #include "qemu/osdep.h" |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 21 | #include "cpu.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 22 | #include "exec/cpu-all.h" |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 23 | #include "exec/helper-proto.h" |
Paolo Bonzini | f08b617 | 2014-03-28 19:42:10 +0100 | [diff] [blame] | 24 | #include "exec/cpu_ldst.h" |
Blue Swirl | 92fc4b5 | 2012-04-29 20:35:48 +0000 | [diff] [blame] | 25 | |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 26 | /* Secure Virtual Machine helpers */ |
| 27 | |
| 28 | #if defined(CONFIG_USER_ONLY) |
| 29 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 30 | void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 31 | { |
| 32 | } |
| 33 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 34 | void helper_vmmcall(CPUX86State *env) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 35 | { |
| 36 | } |
| 37 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 38 | void helper_vmload(CPUX86State *env, int aflag) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 39 | { |
| 40 | } |
| 41 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 42 | void helper_vmsave(CPUX86State *env, int aflag) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 43 | { |
| 44 | } |
| 45 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 46 | void helper_stgi(CPUX86State *env) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 47 | { |
| 48 | } |
| 49 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 50 | void helper_clgi(CPUX86State *env) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 51 | { |
| 52 | } |
| 53 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 54 | void helper_skinit(CPUX86State *env) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 55 | { |
| 56 | } |
| 57 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 58 | void helper_invlpga(CPUX86State *env, int aflag) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 59 | { |
| 60 | } |
| 61 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 62 | void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 63 | { |
| 64 | } |
| 65 | |
| 66 | void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1) |
| 67 | { |
| 68 | } |
| 69 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 70 | void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, |
| 71 | uint64_t param) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 72 | { |
| 73 | } |
| 74 | |
| 75 | void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, |
| 76 | uint64_t param) |
| 77 | { |
| 78 | } |
| 79 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 80 | void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 81 | uint32_t next_eip_addend) |
| 82 | { |
| 83 | } |
| 84 | #else |
| 85 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 86 | static inline void svm_save_seg(CPUX86State *env, hwaddr addr, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 87 | const SegmentCache *sc) |
| 88 | { |
Andreas Färber | 19d6ca1 | 2014-03-09 19:15:27 +0100 | [diff] [blame] | 89 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
| 90 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 91 | x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, selector), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 92 | sc->selector); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 93 | x86_stq_phys(cs, addr + offsetof(struct vmcb_seg, base), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 94 | sc->base); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 95 | x86_stl_phys(cs, addr + offsetof(struct vmcb_seg, limit), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 96 | sc->limit); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 97 | x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, attrib), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 98 | ((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00)); |
| 99 | } |
| 100 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 101 | static inline void svm_load_seg(CPUX86State *env, hwaddr addr, |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 102 | SegmentCache *sc) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 103 | { |
Andreas Färber | 19d6ca1 | 2014-03-09 19:15:27 +0100 | [diff] [blame] | 104 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 105 | unsigned int flags; |
| 106 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 107 | sc->selector = x86_lduw_phys(cs, |
Edgar E. Iglesias | 41701aa | 2013-12-17 14:33:56 +1000 | [diff] [blame] | 108 | addr + offsetof(struct vmcb_seg, selector)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 109 | sc->base = x86_ldq_phys(cs, addr + offsetof(struct vmcb_seg, base)); |
| 110 | sc->limit = x86_ldl_phys(cs, addr + offsetof(struct vmcb_seg, limit)); |
| 111 | flags = x86_lduw_phys(cs, addr + offsetof(struct vmcb_seg, attrib)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 112 | sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12); |
| 113 | } |
| 114 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 115 | static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr, |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 116 | int seg_reg) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 117 | { |
| 118 | SegmentCache sc1, *sc = &sc1; |
| 119 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 120 | svm_load_seg(env, addr, sc); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 121 | cpu_x86_load_seg_cache(env, seg_reg, sc->selector, |
| 122 | sc->base, sc->limit, sc->flags); |
| 123 | } |
| 124 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 125 | void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 126 | { |
Andreas Färber | 19d6ca1 | 2014-03-09 19:15:27 +0100 | [diff] [blame] | 127 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 128 | target_ulong addr; |
| 129 | uint32_t event_inj; |
| 130 | uint32_t int_ctl; |
| 131 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 132 | cpu_svm_check_intercept_param(env, SVM_EXIT_VMRUN, 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 133 | |
| 134 | if (aflag == 2) { |
liguang | 4b34e3a | 2013-05-28 16:20:59 +0800 | [diff] [blame] | 135 | addr = env->regs[R_EAX]; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 136 | } else { |
liguang | 4b34e3a | 2013-05-28 16:20:59 +0800 | [diff] [blame] | 137 | addr = (uint32_t)env->regs[R_EAX]; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmrun! " TARGET_FMT_lx "\n", addr); |
| 141 | |
| 142 | env->vm_vmcb = addr; |
| 143 | |
| 144 | /* save the current CPU state in the hsave page */ |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 145 | x86_stq_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.gdtr.base), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 146 | env->gdt.base); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 147 | x86_stl_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.gdtr.limit), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 148 | env->gdt.limit); |
| 149 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 150 | x86_stq_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.idtr.base), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 151 | env->idt.base); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 152 | x86_stl_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.idtr.limit), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 153 | env->idt.limit); |
| 154 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 155 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 156 | env->vm_hsave + offsetof(struct vmcb, save.cr0), env->cr[0]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 157 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 158 | env->vm_hsave + offsetof(struct vmcb, save.cr2), env->cr[2]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 159 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 160 | env->vm_hsave + offsetof(struct vmcb, save.cr3), env->cr[3]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 161 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 162 | env->vm_hsave + offsetof(struct vmcb, save.cr4), env->cr[4]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 163 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 164 | env->vm_hsave + offsetof(struct vmcb, save.dr6), env->dr[6]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 165 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 166 | env->vm_hsave + offsetof(struct vmcb, save.dr7), env->dr[7]); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 167 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 168 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 169 | env->vm_hsave + offsetof(struct vmcb, save.efer), env->efer); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 170 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 171 | env->vm_hsave + offsetof(struct vmcb, save.rflags), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 172 | cpu_compute_eflags(env)); |
| 173 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 174 | svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.es), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 175 | &env->segs[R_ES]); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 176 | svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.cs), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 177 | &env->segs[R_CS]); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 178 | svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ss), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 179 | &env->segs[R_SS]); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 180 | svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ds), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 181 | &env->segs[R_DS]); |
| 182 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 183 | x86_stq_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.rip), |
liguang | a78d0ea | 2013-05-28 16:21:07 +0800 | [diff] [blame] | 184 | env->eip + next_eip_addend); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 185 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 186 | env->vm_hsave + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 187 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 188 | env->vm_hsave + offsetof(struct vmcb, save.rax), env->regs[R_EAX]); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 189 | |
| 190 | /* load the interception bitmaps so we do not need to access the |
| 191 | vmcb in svm mode */ |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 192 | env->intercept = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 193 | control.intercept)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 194 | env->intercept_cr_read = x86_lduw_phys(cs, env->vm_vmcb + |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 195 | offsetof(struct vmcb, |
| 196 | control.intercept_cr_read)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 197 | env->intercept_cr_write = x86_lduw_phys(cs, env->vm_vmcb + |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 198 | offsetof(struct vmcb, |
| 199 | control.intercept_cr_write)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 200 | env->intercept_dr_read = x86_lduw_phys(cs, env->vm_vmcb + |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 201 | offsetof(struct vmcb, |
| 202 | control.intercept_dr_read)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 203 | env->intercept_dr_write = x86_lduw_phys(cs, env->vm_vmcb + |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 204 | offsetof(struct vmcb, |
| 205 | control.intercept_dr_write)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 206 | env->intercept_exceptions = x86_ldl_phys(cs, env->vm_vmcb + |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 207 | offsetof(struct vmcb, |
| 208 | control.intercept_exceptions |
| 209 | )); |
| 210 | |
| 211 | /* enable intercepts */ |
| 212 | env->hflags |= HF_SVMI_MASK; |
| 213 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 214 | env->tsc_offset = x86_ldq_phys(cs, env->vm_vmcb + |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 215 | offsetof(struct vmcb, control.tsc_offset)); |
| 216 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 217 | env->gdt.base = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 218 | save.gdtr.base)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 219 | env->gdt.limit = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 220 | save.gdtr.limit)); |
| 221 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 222 | env->idt.base = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 223 | save.idtr.base)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 224 | env->idt.limit = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 225 | save.idtr.limit)); |
| 226 | |
| 227 | /* clear exit_info_2 so we behave like the real hardware */ |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 228 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 229 | env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 230 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 231 | cpu_x86_update_cr0(env, x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 232 | env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 233 | save.cr0))); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 234 | cpu_x86_update_cr4(env, x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 235 | env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 236 | save.cr4))); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 237 | cpu_x86_update_cr3(env, x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 238 | env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 239 | save.cr3))); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 240 | env->cr[2] = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 241 | env->vm_vmcb + offsetof(struct vmcb, save.cr2)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 242 | int_ctl = x86_ldl_phys(cs, |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 243 | env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 244 | env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK); |
| 245 | if (int_ctl & V_INTR_MASKING_MASK) { |
| 246 | env->v_tpr = int_ctl & V_TPR_MASK; |
| 247 | env->hflags2 |= HF2_VINTR_MASK; |
| 248 | if (env->eflags & IF_MASK) { |
| 249 | env->hflags2 |= HF2_HIF_MASK; |
| 250 | } |
| 251 | } |
| 252 | |
| 253 | cpu_load_efer(env, |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 254 | x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 255 | env->vm_vmcb + offsetof(struct vmcb, save.efer))); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 256 | env->eflags = 0; |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 257 | cpu_load_eflags(env, x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 258 | env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 259 | save.rflags)), |
| 260 | ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 261 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 262 | svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.es), |
| 263 | R_ES); |
| 264 | svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.cs), |
| 265 | R_CS); |
| 266 | svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ss), |
| 267 | R_SS); |
| 268 | svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds), |
| 269 | R_DS); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 270 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 271 | env->eip = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 272 | env->vm_vmcb + offsetof(struct vmcb, save.rip)); |
liguang | 0bc60a8 | 2013-05-28 16:21:09 +0800 | [diff] [blame] | 273 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 274 | env->regs[R_ESP] = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 275 | env->vm_vmcb + offsetof(struct vmcb, save.rsp)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 276 | env->regs[R_EAX] = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 277 | env->vm_vmcb + offsetof(struct vmcb, save.rax)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 278 | env->dr[7] = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 279 | env->vm_vmcb + offsetof(struct vmcb, save.dr7)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 280 | env->dr[6] = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 281 | env->vm_vmcb + offsetof(struct vmcb, save.dr6)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 282 | |
| 283 | /* FIXME: guest state consistency checks */ |
| 284 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 285 | switch (x86_ldub_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 286 | env->vm_vmcb + offsetof(struct vmcb, control.tlb_ctl))) { |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 287 | case TLB_CONTROL_DO_NOTHING: |
| 288 | break; |
| 289 | case TLB_CONTROL_FLUSH_ALL_ASID: |
| 290 | /* FIXME: this is not 100% correct but should work for now */ |
Andreas Färber | 00c8cb0 | 2013-09-04 02:19:44 +0200 | [diff] [blame] | 291 | tlb_flush(cs, 1); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 292 | break; |
| 293 | } |
| 294 | |
| 295 | env->hflags2 |= HF2_GIF_MASK; |
| 296 | |
| 297 | if (int_ctl & V_IRQ_MASK) { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 298 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
| 299 | |
| 300 | cs->interrupt_request |= CPU_INTERRUPT_VIRQ; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 301 | } |
| 302 | |
| 303 | /* maybe we need to inject an event */ |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 304 | event_inj = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 305 | control.event_inj)); |
| 306 | if (event_inj & SVM_EVTINJ_VALID) { |
| 307 | uint8_t vector = event_inj & SVM_EVTINJ_VEC_MASK; |
| 308 | uint16_t valid_err = event_inj & SVM_EVTINJ_VALID_ERR; |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 309 | uint32_t event_inj_err = x86_ldl_phys(cs, env->vm_vmcb + |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 310 | offsetof(struct vmcb, |
| 311 | control.event_inj_err)); |
| 312 | |
| 313 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "Injecting(%#hx): ", valid_err); |
| 314 | /* FIXME: need to implement valid_err */ |
| 315 | switch (event_inj & SVM_EVTINJ_TYPE_MASK) { |
| 316 | case SVM_EVTINJ_TYPE_INTR: |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 317 | cs->exception_index = vector; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 318 | env->error_code = event_inj_err; |
| 319 | env->exception_is_int = 0; |
| 320 | env->exception_next_eip = -1; |
| 321 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "INTR"); |
| 322 | /* XXX: is it always correct? */ |
| 323 | do_interrupt_x86_hardirq(env, vector, 1); |
| 324 | break; |
| 325 | case SVM_EVTINJ_TYPE_NMI: |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 326 | cs->exception_index = EXCP02_NMI; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 327 | env->error_code = event_inj_err; |
| 328 | env->exception_is_int = 0; |
liguang | a78d0ea | 2013-05-28 16:21:07 +0800 | [diff] [blame] | 329 | env->exception_next_eip = env->eip; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 330 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI"); |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 331 | cpu_loop_exit(cs); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 332 | break; |
| 333 | case SVM_EVTINJ_TYPE_EXEPT: |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 334 | cs->exception_index = vector; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 335 | env->error_code = event_inj_err; |
| 336 | env->exception_is_int = 0; |
| 337 | env->exception_next_eip = -1; |
| 338 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT"); |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 339 | cpu_loop_exit(cs); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 340 | break; |
| 341 | case SVM_EVTINJ_TYPE_SOFT: |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 342 | cs->exception_index = vector; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 343 | env->error_code = event_inj_err; |
| 344 | env->exception_is_int = 1; |
liguang | a78d0ea | 2013-05-28 16:21:07 +0800 | [diff] [blame] | 345 | env->exception_next_eip = env->eip; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 346 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT"); |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 347 | cpu_loop_exit(cs); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 348 | break; |
| 349 | } |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 350 | qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 351 | env->error_code); |
| 352 | } |
| 353 | } |
| 354 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 355 | void helper_vmmcall(CPUX86State *env) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 356 | { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 357 | cpu_svm_check_intercept_param(env, SVM_EXIT_VMMCALL, 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 358 | raise_exception(env, EXCP06_ILLOP); |
| 359 | } |
| 360 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 361 | void helper_vmload(CPUX86State *env, int aflag) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 362 | { |
Andreas Färber | 19d6ca1 | 2014-03-09 19:15:27 +0100 | [diff] [blame] | 363 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 364 | target_ulong addr; |
| 365 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 366 | cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 367 | |
| 368 | if (aflag == 2) { |
liguang | 4b34e3a | 2013-05-28 16:20:59 +0800 | [diff] [blame] | 369 | addr = env->regs[R_EAX]; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 370 | } else { |
liguang | 4b34e3a | 2013-05-28 16:20:59 +0800 | [diff] [blame] | 371 | addr = (uint32_t)env->regs[R_EAX]; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 372 | } |
| 373 | |
| 374 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx |
| 375 | "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n", |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 376 | addr, x86_ldq_phys(cs, addr + offsetof(struct vmcb, |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 377 | save.fs.base)), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 378 | env->segs[R_FS].base); |
| 379 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 380 | svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.fs), R_FS); |
| 381 | svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.gs), R_GS); |
| 382 | svm_load_seg(env, addr + offsetof(struct vmcb, save.tr), &env->tr); |
| 383 | svm_load_seg(env, addr + offsetof(struct vmcb, save.ldtr), &env->ldt); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 384 | |
| 385 | #ifdef TARGET_X86_64 |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 386 | env->kernelgsbase = x86_ldq_phys(cs, addr + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 387 | save.kernel_gs_base)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 388 | env->lstar = x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.lstar)); |
| 389 | env->cstar = x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.cstar)); |
| 390 | env->fmask = x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.sfmask)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 391 | #endif |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 392 | env->star = x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.star)); |
| 393 | env->sysenter_cs = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 394 | addr + offsetof(struct vmcb, save.sysenter_cs)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 395 | env->sysenter_esp = x86_ldq_phys(cs, addr + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 396 | save.sysenter_esp)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 397 | env->sysenter_eip = x86_ldq_phys(cs, addr + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 398 | save.sysenter_eip)); |
| 399 | } |
| 400 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 401 | void helper_vmsave(CPUX86State *env, int aflag) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 402 | { |
Andreas Färber | 19d6ca1 | 2014-03-09 19:15:27 +0100 | [diff] [blame] | 403 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 404 | target_ulong addr; |
| 405 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 406 | cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 407 | |
| 408 | if (aflag == 2) { |
liguang | 4b34e3a | 2013-05-28 16:20:59 +0800 | [diff] [blame] | 409 | addr = env->regs[R_EAX]; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 410 | } else { |
liguang | 4b34e3a | 2013-05-28 16:20:59 +0800 | [diff] [blame] | 411 | addr = (uint32_t)env->regs[R_EAX]; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx |
| 415 | "\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n", |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 416 | addr, x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 417 | addr + offsetof(struct vmcb, save.fs.base)), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 418 | env->segs[R_FS].base); |
| 419 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 420 | svm_save_seg(env, addr + offsetof(struct vmcb, save.fs), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 421 | &env->segs[R_FS]); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 422 | svm_save_seg(env, addr + offsetof(struct vmcb, save.gs), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 423 | &env->segs[R_GS]); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 424 | svm_save_seg(env, addr + offsetof(struct vmcb, save.tr), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 425 | &env->tr); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 426 | svm_save_seg(env, addr + offsetof(struct vmcb, save.ldtr), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 427 | &env->ldt); |
| 428 | |
| 429 | #ifdef TARGET_X86_64 |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 430 | x86_stq_phys(cs, addr + offsetof(struct vmcb, save.kernel_gs_base), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 431 | env->kernelgsbase); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 432 | x86_stq_phys(cs, addr + offsetof(struct vmcb, save.lstar), env->lstar); |
| 433 | x86_stq_phys(cs, addr + offsetof(struct vmcb, save.cstar), env->cstar); |
| 434 | x86_stq_phys(cs, addr + offsetof(struct vmcb, save.sfmask), env->fmask); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 435 | #endif |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 436 | x86_stq_phys(cs, addr + offsetof(struct vmcb, save.star), env->star); |
| 437 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 438 | addr + offsetof(struct vmcb, save.sysenter_cs), env->sysenter_cs); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 439 | x86_stq_phys(cs, addr + offsetof(struct vmcb, save.sysenter_esp), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 440 | env->sysenter_esp); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 441 | x86_stq_phys(cs, addr + offsetof(struct vmcb, save.sysenter_eip), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 442 | env->sysenter_eip); |
| 443 | } |
| 444 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 445 | void helper_stgi(CPUX86State *env) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 446 | { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 447 | cpu_svm_check_intercept_param(env, SVM_EXIT_STGI, 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 448 | env->hflags2 |= HF2_GIF_MASK; |
| 449 | } |
| 450 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 451 | void helper_clgi(CPUX86State *env) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 452 | { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 453 | cpu_svm_check_intercept_param(env, SVM_EXIT_CLGI, 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 454 | env->hflags2 &= ~HF2_GIF_MASK; |
| 455 | } |
| 456 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 457 | void helper_skinit(CPUX86State *env) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 458 | { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 459 | cpu_svm_check_intercept_param(env, SVM_EXIT_SKINIT, 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 460 | /* XXX: not implemented */ |
| 461 | raise_exception(env, EXCP06_ILLOP); |
| 462 | } |
| 463 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 464 | void helper_invlpga(CPUX86State *env, int aflag) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 465 | { |
Andreas Färber | 31b030d | 2013-09-04 01:29:02 +0200 | [diff] [blame] | 466 | X86CPU *cpu = x86_env_get_cpu(env); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 467 | target_ulong addr; |
| 468 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 469 | cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 470 | |
| 471 | if (aflag == 2) { |
liguang | 4b34e3a | 2013-05-28 16:20:59 +0800 | [diff] [blame] | 472 | addr = env->regs[R_EAX]; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 473 | } else { |
liguang | 4b34e3a | 2013-05-28 16:20:59 +0800 | [diff] [blame] | 474 | addr = (uint32_t)env->regs[R_EAX]; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 475 | } |
| 476 | |
| 477 | /* XXX: could use the ASID to see if it is needed to do the |
| 478 | flush */ |
Andreas Färber | 31b030d | 2013-09-04 01:29:02 +0200 | [diff] [blame] | 479 | tlb_flush_page(CPU(cpu), addr); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 480 | } |
| 481 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 482 | void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, |
| 483 | uint64_t param) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 484 | { |
Andreas Färber | 19d6ca1 | 2014-03-09 19:15:27 +0100 | [diff] [blame] | 485 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 486 | |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 487 | if (likely(!(env->hflags & HF_SVMI_MASK))) { |
| 488 | return; |
| 489 | } |
| 490 | switch (type) { |
| 491 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR0 + 8: |
| 492 | if (env->intercept_cr_read & (1 << (type - SVM_EXIT_READ_CR0))) { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 493 | helper_vmexit(env, type, param); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 494 | } |
| 495 | break; |
| 496 | case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR0 + 8: |
| 497 | if (env->intercept_cr_write & (1 << (type - SVM_EXIT_WRITE_CR0))) { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 498 | helper_vmexit(env, type, param); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 499 | } |
| 500 | break; |
| 501 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR0 + 7: |
| 502 | if (env->intercept_dr_read & (1 << (type - SVM_EXIT_READ_DR0))) { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 503 | helper_vmexit(env, type, param); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 504 | } |
| 505 | break; |
| 506 | case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR0 + 7: |
| 507 | if (env->intercept_dr_write & (1 << (type - SVM_EXIT_WRITE_DR0))) { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 508 | helper_vmexit(env, type, param); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 509 | } |
| 510 | break; |
| 511 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 31: |
| 512 | if (env->intercept_exceptions & (1 << (type - SVM_EXIT_EXCP_BASE))) { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 513 | helper_vmexit(env, type, param); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 514 | } |
| 515 | break; |
| 516 | case SVM_EXIT_MSR: |
| 517 | if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) { |
| 518 | /* FIXME: this should be read in at vmrun (faster this way?) */ |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 519 | uint64_t addr = x86_ldq_phys(cs, env->vm_vmcb + |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 520 | offsetof(struct vmcb, |
| 521 | control.msrpm_base_pa)); |
| 522 | uint32_t t0, t1; |
| 523 | |
liguang | a416561 | 2013-05-28 16:21:01 +0800 | [diff] [blame] | 524 | switch ((uint32_t)env->regs[R_ECX]) { |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 525 | case 0 ... 0x1fff: |
liguang | a416561 | 2013-05-28 16:21:01 +0800 | [diff] [blame] | 526 | t0 = (env->regs[R_ECX] * 2) % 8; |
| 527 | t1 = (env->regs[R_ECX] * 2) / 8; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 528 | break; |
| 529 | case 0xc0000000 ... 0xc0001fff: |
liguang | a416561 | 2013-05-28 16:21:01 +0800 | [diff] [blame] | 530 | t0 = (8192 + env->regs[R_ECX] - 0xc0000000) * 2; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 531 | t1 = (t0 / 8); |
| 532 | t0 %= 8; |
| 533 | break; |
| 534 | case 0xc0010000 ... 0xc0011fff: |
liguang | a416561 | 2013-05-28 16:21:01 +0800 | [diff] [blame] | 535 | t0 = (16384 + env->regs[R_ECX] - 0xc0010000) * 2; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 536 | t1 = (t0 / 8); |
| 537 | t0 %= 8; |
| 538 | break; |
| 539 | default: |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 540 | helper_vmexit(env, type, param); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 541 | t0 = 0; |
| 542 | t1 = 0; |
| 543 | break; |
| 544 | } |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 545 | if (x86_ldub_phys(cs, addr + t1) & ((1 << param) << t0)) { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 546 | helper_vmexit(env, type, param); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 547 | } |
| 548 | } |
| 549 | break; |
| 550 | default: |
| 551 | if (env->intercept & (1ULL << (type - SVM_EXIT_INTR))) { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 552 | helper_vmexit(env, type, param); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 553 | } |
| 554 | break; |
| 555 | } |
| 556 | } |
| 557 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 558 | void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 559 | uint64_t param) |
| 560 | { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 561 | helper_svm_check_intercept_param(env, type, param); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 562 | } |
| 563 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 564 | void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 565 | uint32_t next_eip_addend) |
| 566 | { |
Andreas Färber | 19d6ca1 | 2014-03-09 19:15:27 +0100 | [diff] [blame] | 567 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
| 568 | |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 569 | if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) { |
| 570 | /* FIXME: this should be read in at vmrun (faster this way?) */ |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 571 | uint64_t addr = x86_ldq_phys(cs, env->vm_vmcb + |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 572 | offsetof(struct vmcb, control.iopm_base_pa)); |
| 573 | uint16_t mask = (1 << ((param >> 4) & 7)) - 1; |
| 574 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 575 | if (x86_lduw_phys(cs, addr + port / 8) & (mask << (port & 7))) { |
liguang | a78d0ea | 2013-05-28 16:21:07 +0800 | [diff] [blame] | 576 | /* next env->eip */ |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 577 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 578 | env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 579 | env->eip + next_eip_addend); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 580 | helper_vmexit(env, SVM_EXIT_IOIO, param | (port << 16)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 581 | } |
| 582 | } |
| 583 | } |
| 584 | |
| 585 | /* Note: currently only 32 bits of exit_code are used */ |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 586 | void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 587 | { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 588 | CPUState *cs = CPU(x86_env_get_cpu(env)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 589 | uint32_t int_ctl; |
| 590 | |
| 591 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016" |
| 592 | PRIx64 ", " TARGET_FMT_lx ")!\n", |
| 593 | exit_code, exit_info_1, |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 594 | x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 595 | control.exit_info_2)), |
liguang | a78d0ea | 2013-05-28 16:21:07 +0800 | [diff] [blame] | 596 | env->eip); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 597 | |
| 598 | if (env->hflags & HF_INHIBIT_IRQ_MASK) { |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 599 | x86_stl_phys(cs, |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 600 | env->vm_vmcb + offsetof(struct vmcb, control.int_state), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 601 | SVM_INTERRUPT_SHADOW_MASK); |
| 602 | env->hflags &= ~HF_INHIBIT_IRQ_MASK; |
| 603 | } else { |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 604 | x86_stl_phys(cs, |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 605 | env->vm_vmcb + offsetof(struct vmcb, control.int_state), 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 606 | } |
| 607 | |
| 608 | /* Save the VM state in the vmcb */ |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 609 | svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.es), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 610 | &env->segs[R_ES]); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 611 | svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.cs), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 612 | &env->segs[R_CS]); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 613 | svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ss), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 614 | &env->segs[R_SS]); |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 615 | svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ds), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 616 | &env->segs[R_DS]); |
| 617 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 618 | x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 619 | env->gdt.base); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 620 | x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.limit), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 621 | env->gdt.limit); |
| 622 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 623 | x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.idtr.base), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 624 | env->idt.base); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 625 | x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.idtr.limit), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 626 | env->idt.limit); |
| 627 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 628 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 629 | env->vm_vmcb + offsetof(struct vmcb, save.efer), env->efer); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 630 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 631 | env->vm_vmcb + offsetof(struct vmcb, save.cr0), env->cr[0]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 632 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 633 | env->vm_vmcb + offsetof(struct vmcb, save.cr2), env->cr[2]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 634 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 635 | env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 636 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 637 | env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 638 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 639 | int_ctl = x86_ldl_phys(cs, |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 640 | env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 641 | int_ctl &= ~(V_TPR_MASK | V_IRQ_MASK); |
| 642 | int_ctl |= env->v_tpr & V_TPR_MASK; |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 643 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 644 | int_ctl |= V_IRQ_MASK; |
| 645 | } |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 646 | x86_stl_phys(cs, |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 647 | env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 648 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 649 | x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.rflags), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 650 | cpu_compute_eflags(env)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 651 | x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.rip), |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 652 | env->eip); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 653 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 654 | env->vm_vmcb + offsetof(struct vmcb, save.rsp), env->regs[R_ESP]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 655 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 656 | env->vm_vmcb + offsetof(struct vmcb, save.rax), env->regs[R_EAX]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 657 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 658 | env->vm_vmcb + offsetof(struct vmcb, save.dr7), env->dr[7]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 659 | x86_stq_phys(cs, |
Edgar E. Iglesias | f606604 | 2013-11-28 00:11:44 +0100 | [diff] [blame] | 660 | env->vm_vmcb + offsetof(struct vmcb, save.dr6), env->dr[6]); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 661 | x86_stb_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.cpl), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 662 | env->hflags & HF_CPL_MASK); |
| 663 | |
| 664 | /* Reload the host state from vm_hsave */ |
| 665 | env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK); |
| 666 | env->hflags &= ~HF_SVMI_MASK; |
| 667 | env->intercept = 0; |
| 668 | env->intercept_exceptions = 0; |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 669 | cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 670 | env->tsc_offset = 0; |
| 671 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 672 | env->gdt.base = x86_ldq_phys(cs, env->vm_hsave + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 673 | save.gdtr.base)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 674 | env->gdt.limit = x86_ldl_phys(cs, env->vm_hsave + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 675 | save.gdtr.limit)); |
| 676 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 677 | env->idt.base = x86_ldq_phys(cs, env->vm_hsave + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 678 | save.idtr.base)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 679 | env->idt.limit = x86_ldl_phys(cs, env->vm_hsave + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 680 | save.idtr.limit)); |
| 681 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 682 | cpu_x86_update_cr0(env, x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 683 | env->vm_hsave + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 684 | save.cr0)) | |
| 685 | CR0_PE_MASK); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 686 | cpu_x86_update_cr4(env, x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 687 | env->vm_hsave + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 688 | save.cr4))); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 689 | cpu_x86_update_cr3(env, x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 690 | env->vm_hsave + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 691 | save.cr3))); |
| 692 | /* we need to set the efer after the crs so the hidden flags get |
| 693 | set properly */ |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 694 | cpu_load_efer(env, x86_ldq_phys(cs, env->vm_hsave + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 695 | save.efer))); |
| 696 | env->eflags = 0; |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 697 | cpu_load_eflags(env, x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 698 | env->vm_hsave + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 699 | save.rflags)), |
Kevin O'Connor | 3045202 | 2014-04-29 16:37:50 -0400 | [diff] [blame] | 700 | ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK | |
| 701 | VM_MASK)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 702 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 703 | svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.es), |
| 704 | R_ES); |
| 705 | svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.cs), |
| 706 | R_CS); |
| 707 | svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ss), |
| 708 | R_SS); |
| 709 | svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds), |
| 710 | R_DS); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 711 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 712 | env->eip = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 713 | env->vm_hsave + offsetof(struct vmcb, save.rip)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 714 | env->regs[R_ESP] = x86_ldq_phys(cs, env->vm_hsave + |
liguang | 90a2541 | 2013-05-28 16:21:10 +0800 | [diff] [blame] | 715 | offsetof(struct vmcb, save.rsp)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 716 | env->regs[R_EAX] = x86_ldq_phys(cs, env->vm_hsave + |
liguang | 90a2541 | 2013-05-28 16:21:10 +0800 | [diff] [blame] | 717 | offsetof(struct vmcb, save.rax)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 718 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 719 | env->dr[6] = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 720 | env->vm_hsave + offsetof(struct vmcb, save.dr6)); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 721 | env->dr[7] = x86_ldq_phys(cs, |
Edgar E. Iglesias | 2c17449 | 2013-12-17 14:05:40 +1000 | [diff] [blame] | 722 | env->vm_hsave + offsetof(struct vmcb, save.dr7)); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 723 | |
| 724 | /* other setups */ |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 725 | x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_code), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 726 | exit_code); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 727 | x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.exit_info_1), |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 728 | exit_info_1); |
| 729 | |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 730 | x86_stl_phys(cs, |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 731 | env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info), |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 732 | x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 733 | control.event_inj))); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 734 | x86_stl_phys(cs, |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 735 | env->vm_vmcb + offsetof(struct vmcb, control.exit_int_info_err), |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 736 | x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 737 | control.event_inj_err))); |
Paolo Bonzini | b216aa6 | 2015-04-08 13:39:37 +0200 | [diff] [blame] | 738 | x86_stl_phys(cs, |
Edgar E. Iglesias | ab1da85 | 2013-12-17 15:07:29 +1000 | [diff] [blame] | 739 | env->vm_vmcb + offsetof(struct vmcb, control.event_inj), 0); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 740 | |
| 741 | env->hflags2 &= ~HF2_GIF_MASK; |
| 742 | /* FIXME: Resets the current ASID register to zero (host ASID). */ |
| 743 | |
| 744 | /* Clears the V_IRQ and V_INTR_MASKING bits inside the processor. */ |
| 745 | |
| 746 | /* Clears the TSC_OFFSET inside the processor. */ |
| 747 | |
| 748 | /* If the host is in PAE mode, the processor reloads the host's PDPEs |
| 749 | from the page table indicated the host's CR3. If the PDPEs contain |
| 750 | illegal state, the processor causes a shutdown. */ |
| 751 | |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 752 | /* Disables all breakpoints in the host DR7 register. */ |
| 753 | |
| 754 | /* Checks the reloaded host state for consistency. */ |
| 755 | |
| 756 | /* If the host's rIP reloaded by #VMEXIT is outside the limit of the |
| 757 | host's code segment or non-canonical (in the case of long mode), a |
| 758 | #GP fault is delivered inside the host. */ |
| 759 | |
| 760 | /* remove any pending exception */ |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 761 | cs->exception_index = -1; |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 762 | env->error_code = 0; |
| 763 | env->old_exception = -1; |
| 764 | |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 765 | cpu_loop_exit(cs); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 766 | } |
| 767 | |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 768 | void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 769 | { |
Blue Swirl | 052e80d | 2012-04-29 15:51:49 +0000 | [diff] [blame] | 770 | helper_vmexit(env, exit_code, exit_info_1); |
Blue Swirl | 6bada5e | 2012-04-29 14:42:35 +0000 | [diff] [blame] | 771 | } |
| 772 | |
| 773 | #endif |