bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 1 | /* |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2 | * i386 execution defines |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 18 | */ |
bellard | 7d3505c | 2004-05-12 19:32:15 +0000 | [diff] [blame] | 19 | #include "config.h" |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 20 | #include "dyngen-exec.h" |
| 21 | |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 22 | /* XXX: factorize this mess */ |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 23 | #ifdef TARGET_X86_64 |
| 24 | #define TARGET_LONG_BITS 64 |
| 25 | #else |
| 26 | #define TARGET_LONG_BITS 32 |
| 27 | #endif |
| 28 | |
bellard | d785e6b | 2005-03-01 22:33:42 +0000 | [diff] [blame] | 29 | #include "cpu-defs.h" |
| 30 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 31 | register struct CPUX86State *env asm(AREG0); |
bellard | 14ce26e | 2005-01-03 23:50:08 +0000 | [diff] [blame] | 32 | |
blueswir1 | 7d99a00 | 2009-01-14 19:00:36 +0000 | [diff] [blame] | 33 | #include "qemu-common.h" |
blueswir1 | 79383c9 | 2008-08-30 09:51:20 +0000 | [diff] [blame] | 34 | #include "qemu-log.h" |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 35 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 36 | #include "cpu.h" |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 37 | |
blueswir1 | d9957a8 | 2008-12-13 11:49:17 +0000 | [diff] [blame] | 38 | /* op_helper.c */ |
malc | a5e50b2 | 2009-02-01 22:19:27 +0000 | [diff] [blame] | 39 | void QEMU_NORETURN raise_exception_err(int exception_index, int error_code); |
| 40 | void QEMU_NORETURN raise_exception(int exception_index); |
Jason Wessel | 63a5473 | 2010-01-26 16:29:50 -0600 | [diff] [blame] | 41 | void QEMU_NORETURN raise_exception_env(int exception_index, CPUState *nenv); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 42 | |
bellard | b6abf97 | 2008-05-17 12:44:31 +0000 | [diff] [blame] | 43 | /* n must be a constant to be efficient */ |
| 44 | static inline target_long lshift(target_long x, int n) |
| 45 | { |
| 46 | if (n >= 0) |
| 47 | return x << n; |
| 48 | else |
| 49 | return x >> (-n); |
| 50 | } |
| 51 | |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 52 | #include "helper.h" |
| 53 | |
bellard | 9951bf3 | 2003-10-28 23:06:17 +0000 | [diff] [blame] | 54 | #if !defined(CONFIG_USER_ONLY) |
| 55 | |
bellard | a9049a0 | 2005-10-30 18:16:26 +0000 | [diff] [blame] | 56 | #include "softmmu_exec.h" |
bellard | 9951bf3 | 2003-10-28 23:06:17 +0000 | [diff] [blame] | 57 | |
bellard | 9951bf3 | 2003-10-28 23:06:17 +0000 | [diff] [blame] | 58 | #endif /* !defined(CONFIG_USER_ONLY) */ |
| 59 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 60 | #define RC_MASK 0xc00 |
| 61 | #define RC_NEAR 0x000 |
| 62 | #define RC_DOWN 0x400 |
| 63 | #define RC_UP 0x800 |
| 64 | #define RC_CHOP 0xc00 |
| 65 | |
| 66 | #define MAXTAN 9223372036854775808.0 |
| 67 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 68 | /* the following deal with x86 long double-precision numbers */ |
| 69 | #define MAXEXPD 0x7fff |
| 70 | #define EXPBIAS 16383 |
| 71 | #define EXPD(fp) (fp.l.upper & 0x7fff) |
| 72 | #define SIGND(fp) ((fp.l.upper) & 0x8000) |
| 73 | #define MANTD(fp) (fp.l.lower) |
| 74 | #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS |
| 75 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 76 | static inline void fpush(void) |
| 77 | { |
| 78 | env->fpstt = (env->fpstt - 1) & 7; |
| 79 | env->fptags[env->fpstt] = 0; /* validate stack entry */ |
| 80 | } |
| 81 | |
| 82 | static inline void fpop(void) |
| 83 | { |
| 84 | env->fptags[env->fpstt] = 1; /* invvalidate stack entry */ |
| 85 | env->fpstt = (env->fpstt + 1) & 7; |
| 86 | } |
| 87 | |
Aurelien Jarno | c31da13 | 2011-05-15 14:09:18 +0200 | [diff] [blame] | 88 | static inline floatx80 helper_fldt(target_ulong ptr) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 89 | { |
Aurelien Jarno | c31da13 | 2011-05-15 14:09:18 +0200 | [diff] [blame] | 90 | CPU_LDoubleU temp; |
bellard | 9951bf3 | 2003-10-28 23:06:17 +0000 | [diff] [blame] | 91 | |
| 92 | temp.l.lower = ldq(ptr); |
| 93 | temp.l.upper = lduw(ptr + 8); |
| 94 | return temp.d; |
| 95 | } |
| 96 | |
Aurelien Jarno | c31da13 | 2011-05-15 14:09:18 +0200 | [diff] [blame] | 97 | static inline void helper_fstt(floatx80 f, target_ulong ptr) |
bellard | 9951bf3 | 2003-10-28 23:06:17 +0000 | [diff] [blame] | 98 | { |
Aurelien Jarno | c31da13 | 2011-05-15 14:09:18 +0200 | [diff] [blame] | 99 | CPU_LDoubleU temp; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 100 | |
bellard | 9951bf3 | 2003-10-28 23:06:17 +0000 | [diff] [blame] | 101 | temp.d = f; |
| 102 | stq(ptr, temp.l.lower); |
| 103 | stw(ptr + 8, temp.l.upper); |
| 104 | } |
| 105 | |
bellard | 2ee73ac | 2004-05-08 21:08:41 +0000 | [diff] [blame] | 106 | #define FPUS_IE (1 << 0) |
| 107 | #define FPUS_DE (1 << 1) |
| 108 | #define FPUS_ZE (1 << 2) |
| 109 | #define FPUS_OE (1 << 3) |
| 110 | #define FPUS_UE (1 << 4) |
| 111 | #define FPUS_PE (1 << 5) |
| 112 | #define FPUS_SF (1 << 6) |
| 113 | #define FPUS_SE (1 << 7) |
| 114 | #define FPUS_B (1 << 15) |
| 115 | |
| 116 | #define FPUC_EM 0x3f |
| 117 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 118 | static inline uint32_t compute_eflags(void) |
| 119 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 120 | return env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 121 | } |
| 122 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 123 | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ |
| 124 | static inline void load_eflags(int eflags, int update_mask) |
| 125 | { |
| 126 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| 127 | DF = 1 - (2 * ((eflags >> 10) & 1)); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 128 | env->eflags = (env->eflags & ~update_mask) | |
bellard | 093f8f0 | 2008-05-28 16:25:20 +0000 | [diff] [blame] | 129 | (eflags & update_mask) | 0x2; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 130 | } |
| 131 | |
bellard | 5efc27b | 2008-06-04 13:35:58 +0000 | [diff] [blame] | 132 | /* load efer and update the corresponding hflags. XXX: do consistency |
| 133 | checks with cpuid bits ? */ |
| 134 | static inline void cpu_load_efer(CPUState *env, uint64_t val) |
| 135 | { |
| 136 | env->efer = val; |
| 137 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); |
| 138 | if (env->efer & MSR_EFER_LMA) |
| 139 | env->hflags |= HF_LMA_MASK; |
| 140 | if (env->efer & MSR_EFER_SVME) |
| 141 | env->hflags |= HF_SVME_MASK; |
| 142 | } |