Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1 | /* |
| 2 | * QEMU LSI SAS1068 Host Bus Adapter emulation |
| 3 | * Based on the QEMU Megaraid emulator |
| 4 | * |
| 5 | * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs |
| 6 | * Copyright (c) 2012 Verizon, Inc. |
| 7 | * Copyright (c) 2016 Red Hat, Inc. |
| 8 | * |
| 9 | * Authors: Don Slutz, Paolo Bonzini |
| 10 | * |
| 11 | * This library is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU Lesser General Public |
| 13 | * License as published by the Free Software Foundation; either |
| 14 | * version 2 of the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This library is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 19 | * Lesser General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU Lesser General Public |
| 22 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "hw/hw.h" |
| 27 | #include "hw/pci/pci.h" |
| 28 | #include "sysemu/dma.h" |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 29 | #include "hw/pci/msi.h" |
| 30 | #include "qemu/iov.h" |
| 31 | #include "hw/scsi/scsi.h" |
Paolo Bonzini | 08e2c9f | 2017-08-22 09:23:55 +0200 | [diff] [blame] | 32 | #include "scsi/constants.h" |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 33 | #include "trace.h" |
Cao jin | 1108b2f | 2016-06-20 14:13:39 +0800 | [diff] [blame] | 34 | #include "qapi/error.h" |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 35 | #include "mptsas.h" |
| 36 | #include "mpi.h" |
| 37 | |
| 38 | #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL |
| 39 | #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400 |
| 40 | |
| 41 | #define TYPE_MPTSAS1068 "mptsas1068" |
| 42 | |
| 43 | #define MPT_SAS(obj) \ |
| 44 | OBJECT_CHECK(MPTSASState, (obj), TYPE_MPTSAS1068) |
| 45 | |
| 46 | #define MPTSAS1068_PRODUCT_ID \ |
| 47 | (MPI_FW_HEADER_PID_FAMILY_1068_SAS | \ |
| 48 | MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI | \ |
| 49 | MPI_FW_HEADER_PID_TYPE_SAS) |
| 50 | |
| 51 | struct MPTSASRequest { |
| 52 | MPIMsgSCSIIORequest scsi_io; |
| 53 | SCSIRequest *sreq; |
| 54 | QEMUSGList qsg; |
| 55 | MPTSASState *dev; |
| 56 | |
| 57 | QTAILQ_ENTRY(MPTSASRequest) next; |
| 58 | }; |
| 59 | |
| 60 | static void mptsas_update_interrupt(MPTSASState *s) |
| 61 | { |
| 62 | PCIDevice *pci = (PCIDevice *) s; |
| 63 | uint32_t state = s->intr_status & ~(s->intr_mask | MPI_HIS_IOP_DOORBELL_STATUS); |
| 64 | |
Cao jin | 2e2aa31 | 2016-06-20 14:13:41 +0800 | [diff] [blame] | 65 | if (msi_enabled(pci)) { |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 66 | if (state) { |
| 67 | trace_mptsas_irq_msi(s); |
| 68 | msi_notify(pci, 0); |
| 69 | } |
| 70 | } |
| 71 | |
| 72 | trace_mptsas_irq_intx(s, !!state); |
| 73 | pci_set_irq(pci, !!state); |
| 74 | } |
| 75 | |
| 76 | static void mptsas_set_fault(MPTSASState *s, uint32_t code) |
| 77 | { |
| 78 | if ((s->state & MPI_IOC_STATE_FAULT) == 0) { |
| 79 | s->state = MPI_IOC_STATE_FAULT | code; |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | #define MPTSAS_FIFO_INVALID(s, name) \ |
| 84 | ((s)->name##_head > ARRAY_SIZE((s)->name) || \ |
| 85 | (s)->name##_tail > ARRAY_SIZE((s)->name)) |
| 86 | |
| 87 | #define MPTSAS_FIFO_EMPTY(s, name) \ |
| 88 | ((s)->name##_head == (s)->name##_tail) |
| 89 | |
| 90 | #define MPTSAS_FIFO_FULL(s, name) \ |
| 91 | ((s)->name##_head == ((s)->name##_tail + 1) % ARRAY_SIZE((s)->name)) |
| 92 | |
| 93 | #define MPTSAS_FIFO_GET(s, name) ({ \ |
| 94 | uint32_t _val = (s)->name[(s)->name##_head++]; \ |
| 95 | (s)->name##_head %= ARRAY_SIZE((s)->name); \ |
| 96 | _val; \ |
| 97 | }) |
| 98 | |
| 99 | #define MPTSAS_FIFO_PUT(s, name, val) do { \ |
| 100 | (s)->name[(s)->name##_tail++] = (val); \ |
| 101 | (s)->name##_tail %= ARRAY_SIZE((s)->name); \ |
| 102 | } while(0) |
| 103 | |
| 104 | static void mptsas_post_reply(MPTSASState *s, MPIDefaultReply *reply) |
| 105 | { |
| 106 | PCIDevice *pci = (PCIDevice *) s; |
| 107 | uint32_t addr_lo; |
| 108 | |
| 109 | if (MPTSAS_FIFO_EMPTY(s, reply_free) || MPTSAS_FIFO_FULL(s, reply_post)) { |
| 110 | mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); |
| 111 | return; |
| 112 | } |
| 113 | |
| 114 | addr_lo = MPTSAS_FIFO_GET(s, reply_free); |
| 115 | |
| 116 | pci_dma_write(pci, addr_lo | s->host_mfa_high_addr, reply, |
| 117 | MIN(s->reply_frame_size, 4 * reply->MsgLength)); |
| 118 | |
| 119 | MPTSAS_FIFO_PUT(s, reply_post, MPI_ADDRESS_REPLY_A_BIT | (addr_lo >> 1)); |
| 120 | |
| 121 | s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; |
| 122 | if (s->doorbell_state == DOORBELL_WRITE) { |
| 123 | s->doorbell_state = DOORBELL_NONE; |
| 124 | s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; |
| 125 | } |
| 126 | mptsas_update_interrupt(s); |
| 127 | } |
| 128 | |
| 129 | void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply) |
| 130 | { |
| 131 | if (s->doorbell_state == DOORBELL_WRITE) { |
| 132 | /* The reply is sent out in 16 bit chunks, while the size |
| 133 | * in the reply is in 32 bit units. |
| 134 | */ |
| 135 | s->doorbell_state = DOORBELL_READ; |
| 136 | s->doorbell_reply_idx = 0; |
| 137 | s->doorbell_reply_size = reply->MsgLength * 2; |
| 138 | memcpy(s->doorbell_reply, reply, s->doorbell_reply_size * 2); |
| 139 | s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; |
| 140 | mptsas_update_interrupt(s); |
| 141 | } else { |
| 142 | mptsas_post_reply(s, reply); |
| 143 | } |
| 144 | } |
| 145 | |
| 146 | static void mptsas_turbo_reply(MPTSASState *s, uint32_t msgctx) |
| 147 | { |
| 148 | if (MPTSAS_FIFO_FULL(s, reply_post)) { |
| 149 | mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); |
| 150 | return; |
| 151 | } |
| 152 | |
| 153 | /* The reply is just the message context ID (bit 31 = clear). */ |
| 154 | MPTSAS_FIFO_PUT(s, reply_post, msgctx); |
| 155 | |
| 156 | s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT; |
| 157 | mptsas_update_interrupt(s); |
| 158 | } |
| 159 | |
| 160 | #define MPTSAS_MAX_REQUEST_SIZE 52 |
| 161 | |
| 162 | static const int mpi_request_sizes[] = { |
| 163 | [MPI_FUNCTION_SCSI_IO_REQUEST] = sizeof(MPIMsgSCSIIORequest), |
| 164 | [MPI_FUNCTION_SCSI_TASK_MGMT] = sizeof(MPIMsgSCSITaskMgmt), |
| 165 | [MPI_FUNCTION_IOC_INIT] = sizeof(MPIMsgIOCInit), |
| 166 | [MPI_FUNCTION_IOC_FACTS] = sizeof(MPIMsgIOCFacts), |
| 167 | [MPI_FUNCTION_CONFIG] = sizeof(MPIMsgConfig), |
| 168 | [MPI_FUNCTION_PORT_FACTS] = sizeof(MPIMsgPortFacts), |
| 169 | [MPI_FUNCTION_PORT_ENABLE] = sizeof(MPIMsgPortEnable), |
| 170 | [MPI_FUNCTION_EVENT_NOTIFICATION] = sizeof(MPIMsgEventNotify), |
| 171 | }; |
| 172 | |
| 173 | static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_length, |
| 174 | dma_addr_t *sgaddr) |
| 175 | { |
| 176 | PCIDevice *pci = (PCIDevice *) s; |
| 177 | dma_addr_t addr; |
| 178 | |
| 179 | if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) { |
| 180 | addr = ldq_le_pci_dma(pci, *sgaddr + 4); |
| 181 | *sgaddr += 12; |
| 182 | } else { |
| 183 | addr = ldl_le_pci_dma(pci, *sgaddr + 4); |
| 184 | *sgaddr += 8; |
| 185 | } |
| 186 | return addr; |
| 187 | } |
| 188 | |
| 189 | static int mptsas_build_sgl(MPTSASState *s, MPTSASRequest *req, hwaddr addr) |
| 190 | { |
| 191 | PCIDevice *pci = (PCIDevice *) s; |
| 192 | hwaddr next_chain_addr; |
| 193 | uint32_t left; |
| 194 | hwaddr sgaddr; |
| 195 | uint32_t chain_offset; |
| 196 | |
| 197 | chain_offset = req->scsi_io.ChainOffset; |
| 198 | next_chain_addr = addr + chain_offset * sizeof(uint32_t); |
| 199 | sgaddr = addr + sizeof(MPIMsgSCSIIORequest); |
| 200 | pci_dma_sglist_init(&req->qsg, pci, 4); |
| 201 | left = req->scsi_io.DataLength; |
| 202 | |
| 203 | for(;;) { |
| 204 | dma_addr_t addr, len; |
| 205 | uint32_t flags_and_length; |
| 206 | |
| 207 | flags_and_length = ldl_le_pci_dma(pci, sgaddr); |
| 208 | len = flags_and_length & MPI_SGE_LENGTH_MASK; |
| 209 | if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) |
| 210 | != MPI_SGE_FLAGS_SIMPLE_ELEMENT || |
| 211 | (!len && |
| 212 | !(flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) && |
| 213 | !(flags_and_length & MPI_SGE_FLAGS_END_OF_BUFFER))) { |
| 214 | return MPI_IOCSTATUS_INVALID_SGL; |
| 215 | } |
| 216 | |
| 217 | len = MIN(len, left); |
| 218 | if (!len) { |
| 219 | /* We reached the desired transfer length, ignore extra |
| 220 | * elements of the s/g list. |
| 221 | */ |
| 222 | break; |
| 223 | } |
| 224 | |
| 225 | addr = mptsas_ld_sg_base(s, flags_and_length, &sgaddr); |
| 226 | qemu_sglist_add(&req->qsg, addr, len); |
| 227 | left -= len; |
| 228 | |
| 229 | if (flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) { |
| 230 | break; |
| 231 | } |
| 232 | |
| 233 | if (flags_and_length & MPI_SGE_FLAGS_LAST_ELEMENT) { |
| 234 | if (!chain_offset) { |
| 235 | break; |
| 236 | } |
| 237 | |
| 238 | flags_and_length = ldl_le_pci_dma(pci, next_chain_addr); |
| 239 | if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK) |
| 240 | != MPI_SGE_FLAGS_CHAIN_ELEMENT) { |
| 241 | return MPI_IOCSTATUS_INVALID_SGL; |
| 242 | } |
| 243 | |
| 244 | sgaddr = mptsas_ld_sg_base(s, flags_and_length, &next_chain_addr); |
| 245 | chain_offset = |
| 246 | (flags_and_length & MPI_SGE_CHAIN_OFFSET_MASK) >> MPI_SGE_CHAIN_OFFSET_SHIFT; |
| 247 | next_chain_addr = sgaddr + chain_offset * sizeof(uint32_t); |
| 248 | } |
| 249 | } |
| 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | static void mptsas_free_request(MPTSASRequest *req) |
| 254 | { |
| 255 | MPTSASState *s = req->dev; |
| 256 | |
| 257 | if (req->sreq != NULL) { |
| 258 | req->sreq->hba_private = NULL; |
| 259 | scsi_req_unref(req->sreq); |
| 260 | req->sreq = NULL; |
| 261 | QTAILQ_REMOVE(&s->pending, req, next); |
| 262 | } |
| 263 | qemu_sglist_destroy(&req->qsg); |
| 264 | g_free(req); |
| 265 | } |
| 266 | |
| 267 | static int mptsas_scsi_device_find(MPTSASState *s, int bus, int target, |
| 268 | uint8_t *lun, SCSIDevice **sdev) |
| 269 | { |
| 270 | if (bus != 0) { |
| 271 | return MPI_IOCSTATUS_SCSI_INVALID_BUS; |
| 272 | } |
| 273 | |
| 274 | if (target >= s->max_devices) { |
| 275 | return MPI_IOCSTATUS_SCSI_INVALID_TARGETID; |
| 276 | } |
| 277 | |
| 278 | *sdev = scsi_device_find(&s->bus, bus, target, lun[1]); |
| 279 | if (!*sdev) { |
| 280 | return MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE; |
| 281 | } |
| 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static int mptsas_process_scsi_io_request(MPTSASState *s, |
| 287 | MPIMsgSCSIIORequest *scsi_io, |
| 288 | hwaddr addr) |
| 289 | { |
| 290 | MPTSASRequest *req; |
| 291 | MPIMsgSCSIIOReply reply; |
| 292 | SCSIDevice *sdev; |
| 293 | int status; |
| 294 | |
| 295 | mptsas_fix_scsi_io_endianness(scsi_io); |
| 296 | |
| 297 | trace_mptsas_process_scsi_io_request(s, scsi_io->Bus, scsi_io->TargetID, |
| 298 | scsi_io->LUN[1], scsi_io->DataLength); |
| 299 | |
| 300 | status = mptsas_scsi_device_find(s, scsi_io->Bus, scsi_io->TargetID, |
| 301 | scsi_io->LUN, &sdev); |
| 302 | if (status) { |
| 303 | goto bad; |
| 304 | } |
| 305 | |
Li Qiang | 670e56d | 2016-09-12 18:14:11 +0530 | [diff] [blame] | 306 | req = g_new0(MPTSASRequest, 1); |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 307 | QTAILQ_INSERT_TAIL(&s->pending, req, next); |
| 308 | req->scsi_io = *scsi_io; |
| 309 | req->dev = s; |
| 310 | |
| 311 | status = mptsas_build_sgl(s, req, addr); |
| 312 | if (status) { |
| 313 | goto free_bad; |
| 314 | } |
| 315 | |
| 316 | if (req->qsg.size < scsi_io->DataLength) { |
| 317 | trace_mptsas_sgl_overflow(s, scsi_io->MsgContext, scsi_io->DataLength, |
| 318 | req->qsg.size); |
| 319 | status = MPI_IOCSTATUS_INVALID_SGL; |
| 320 | goto free_bad; |
| 321 | } |
| 322 | |
| 323 | req->sreq = scsi_req_new(sdev, scsi_io->MsgContext, |
| 324 | scsi_io->LUN[1], scsi_io->CDB, req); |
| 325 | |
| 326 | if (req->sreq->cmd.xfer > scsi_io->DataLength) { |
| 327 | goto overrun; |
| 328 | } |
| 329 | switch (scsi_io->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) { |
| 330 | case MPI_SCSIIO_CONTROL_NODATATRANSFER: |
| 331 | if (req->sreq->cmd.mode != SCSI_XFER_NONE) { |
| 332 | goto overrun; |
| 333 | } |
| 334 | break; |
| 335 | |
| 336 | case MPI_SCSIIO_CONTROL_WRITE: |
| 337 | if (req->sreq->cmd.mode != SCSI_XFER_TO_DEV) { |
| 338 | goto overrun; |
| 339 | } |
| 340 | break; |
| 341 | |
| 342 | case MPI_SCSIIO_CONTROL_READ: |
| 343 | if (req->sreq->cmd.mode != SCSI_XFER_FROM_DEV) { |
| 344 | goto overrun; |
| 345 | } |
| 346 | break; |
| 347 | } |
| 348 | |
| 349 | if (scsi_req_enqueue(req->sreq)) { |
| 350 | scsi_req_continue(req->sreq); |
| 351 | } |
| 352 | return 0; |
| 353 | |
| 354 | overrun: |
| 355 | trace_mptsas_scsi_overflow(s, scsi_io->MsgContext, req->sreq->cmd.xfer, |
| 356 | scsi_io->DataLength); |
| 357 | status = MPI_IOCSTATUS_SCSI_DATA_OVERRUN; |
| 358 | free_bad: |
| 359 | mptsas_free_request(req); |
| 360 | bad: |
| 361 | memset(&reply, 0, sizeof(reply)); |
| 362 | reply.TargetID = scsi_io->TargetID; |
| 363 | reply.Bus = scsi_io->Bus; |
| 364 | reply.MsgLength = sizeof(reply) / 4; |
| 365 | reply.Function = scsi_io->Function; |
| 366 | reply.CDBLength = scsi_io->CDBLength; |
| 367 | reply.SenseBufferLength = scsi_io->SenseBufferLength; |
| 368 | reply.MsgContext = scsi_io->MsgContext; |
| 369 | reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; |
| 370 | reply.IOCStatus = status; |
| 371 | |
| 372 | mptsas_fix_scsi_io_reply_endianness(&reply); |
| 373 | mptsas_reply(s, (MPIDefaultReply *)&reply); |
| 374 | |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | typedef struct { |
| 379 | Notifier notifier; |
| 380 | MPTSASState *s; |
| 381 | MPIMsgSCSITaskMgmtReply *reply; |
| 382 | } MPTSASCancelNotifier; |
| 383 | |
| 384 | static void mptsas_cancel_notify(Notifier *notifier, void *data) |
| 385 | { |
| 386 | MPTSASCancelNotifier *n = container_of(notifier, |
| 387 | MPTSASCancelNotifier, |
| 388 | notifier); |
| 389 | |
| 390 | /* Abusing IOCLogInfo to store the expected number of requests... */ |
| 391 | if (++n->reply->TerminationCount == n->reply->IOCLogInfo) { |
| 392 | n->reply->IOCLogInfo = 0; |
| 393 | mptsas_fix_scsi_task_mgmt_reply_endianness(n->reply); |
| 394 | mptsas_post_reply(n->s, (MPIDefaultReply *)n->reply); |
| 395 | g_free(n->reply); |
| 396 | } |
| 397 | g_free(n); |
| 398 | } |
| 399 | |
| 400 | static void mptsas_process_scsi_task_mgmt(MPTSASState *s, MPIMsgSCSITaskMgmt *req) |
| 401 | { |
| 402 | MPIMsgSCSITaskMgmtReply reply; |
| 403 | MPIMsgSCSITaskMgmtReply *reply_async; |
| 404 | int status, count; |
| 405 | SCSIDevice *sdev; |
| 406 | SCSIRequest *r, *next; |
| 407 | BusChild *kid; |
| 408 | |
| 409 | mptsas_fix_scsi_task_mgmt_endianness(req); |
| 410 | |
| 411 | QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); |
| 412 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); |
| 413 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); |
| 414 | |
| 415 | memset(&reply, 0, sizeof(reply)); |
| 416 | reply.TargetID = req->TargetID; |
| 417 | reply.Bus = req->Bus; |
| 418 | reply.MsgLength = sizeof(reply) / 4; |
| 419 | reply.Function = req->Function; |
| 420 | reply.TaskType = req->TaskType; |
| 421 | reply.MsgContext = req->MsgContext; |
| 422 | |
| 423 | switch (req->TaskType) { |
| 424 | case MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK: |
| 425 | case MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK: |
| 426 | status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, |
| 427 | req->LUN, &sdev); |
| 428 | if (status) { |
| 429 | reply.IOCStatus = status; |
| 430 | goto out; |
| 431 | } |
| 432 | if (sdev->lun != req->LUN[1]) { |
| 433 | reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; |
| 434 | goto out; |
| 435 | } |
| 436 | |
| 437 | QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { |
| 438 | MPTSASRequest *cmd_req = r->hba_private; |
| 439 | if (cmd_req && cmd_req->scsi_io.MsgContext == req->TaskMsgContext) { |
| 440 | break; |
| 441 | } |
| 442 | } |
| 443 | if (r) { |
| 444 | /* |
| 445 | * Assert that the request has not been completed yet, we |
| 446 | * check for it in the loop above. |
| 447 | */ |
| 448 | assert(r->hba_private); |
| 449 | if (req->TaskType == MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK) { |
| 450 | /* "If the specified command is present in the task set, then |
| 451 | * return a service response set to FUNCTION SUCCEEDED". |
| 452 | */ |
| 453 | reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED; |
| 454 | } else { |
| 455 | MPTSASCancelNotifier *notifier; |
| 456 | |
| 457 | reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); |
| 458 | reply_async->IOCLogInfo = INT_MAX; |
| 459 | |
| 460 | count = 1; |
| 461 | notifier = g_new(MPTSASCancelNotifier, 1); |
| 462 | notifier->s = s; |
| 463 | notifier->reply = reply_async; |
| 464 | notifier->notifier.notify = mptsas_cancel_notify; |
| 465 | scsi_req_cancel_async(r, ¬ifier->notifier); |
| 466 | goto reply_maybe_async; |
| 467 | } |
| 468 | } |
| 469 | break; |
| 470 | |
| 471 | case MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: |
| 472 | case MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: |
| 473 | status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, |
| 474 | req->LUN, &sdev); |
| 475 | if (status) { |
| 476 | reply.IOCStatus = status; |
| 477 | goto out; |
| 478 | } |
| 479 | if (sdev->lun != req->LUN[1]) { |
| 480 | reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; |
| 481 | goto out; |
| 482 | } |
| 483 | |
| 484 | reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply)); |
| 485 | reply_async->IOCLogInfo = INT_MAX; |
| 486 | |
| 487 | count = 0; |
| 488 | QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) { |
| 489 | if (r->hba_private) { |
| 490 | MPTSASCancelNotifier *notifier; |
| 491 | |
| 492 | count++; |
| 493 | notifier = g_new(MPTSASCancelNotifier, 1); |
| 494 | notifier->s = s; |
| 495 | notifier->reply = reply_async; |
| 496 | notifier->notifier.notify = mptsas_cancel_notify; |
| 497 | scsi_req_cancel_async(r, ¬ifier->notifier); |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | reply_maybe_async: |
| 502 | if (reply_async->TerminationCount < count) { |
| 503 | reply_async->IOCLogInfo = count; |
| 504 | return; |
| 505 | } |
Paolo Bonzini | 18557e6 | 2016-02-16 08:41:52 +0100 | [diff] [blame] | 506 | g_free(reply_async); |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 507 | reply.TerminationCount = count; |
| 508 | break; |
| 509 | |
| 510 | case MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: |
| 511 | status = mptsas_scsi_device_find(s, req->Bus, req->TargetID, |
| 512 | req->LUN, &sdev); |
| 513 | if (status) { |
| 514 | reply.IOCStatus = status; |
| 515 | goto out; |
| 516 | } |
| 517 | if (sdev->lun != req->LUN[1]) { |
| 518 | reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN; |
| 519 | goto out; |
| 520 | } |
| 521 | qdev_reset_all(&sdev->qdev); |
| 522 | break; |
| 523 | |
| 524 | case MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET: |
| 525 | if (req->Bus != 0) { |
| 526 | reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_BUS; |
| 527 | goto out; |
| 528 | } |
| 529 | if (req->TargetID > s->max_devices) { |
| 530 | reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_TARGETID; |
| 531 | goto out; |
| 532 | } |
| 533 | |
| 534 | QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { |
| 535 | sdev = SCSI_DEVICE(kid->child); |
| 536 | if (sdev->channel == 0 && sdev->id == req->TargetID) { |
| 537 | qdev_reset_all(kid->child); |
| 538 | } |
| 539 | } |
| 540 | break; |
| 541 | |
| 542 | case MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS: |
| 543 | qbus_reset_all(&s->bus.qbus); |
| 544 | break; |
| 545 | |
| 546 | default: |
| 547 | reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED; |
| 548 | break; |
| 549 | } |
| 550 | |
| 551 | out: |
| 552 | mptsas_fix_scsi_task_mgmt_reply_endianness(&reply); |
| 553 | mptsas_post_reply(s, (MPIDefaultReply *)&reply); |
| 554 | } |
| 555 | |
| 556 | static void mptsas_process_ioc_init(MPTSASState *s, MPIMsgIOCInit *req) |
| 557 | { |
| 558 | MPIMsgIOCInitReply reply; |
| 559 | |
| 560 | mptsas_fix_ioc_init_endianness(req); |
| 561 | |
| 562 | QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); |
| 563 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); |
| 564 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); |
| 565 | |
| 566 | s->who_init = req->WhoInit; |
| 567 | s->reply_frame_size = req->ReplyFrameSize; |
| 568 | s->max_buses = req->MaxBuses; |
| 569 | s->max_devices = req->MaxDevices ? req->MaxDevices : 256; |
| 570 | s->host_mfa_high_addr = (hwaddr)req->HostMfaHighAddr << 32; |
| 571 | s->sense_buffer_high_addr = (hwaddr)req->SenseBufferHighAddr << 32; |
| 572 | |
| 573 | if (s->state == MPI_IOC_STATE_READY) { |
| 574 | s->state = MPI_IOC_STATE_OPERATIONAL; |
| 575 | } |
| 576 | |
| 577 | memset(&reply, 0, sizeof(reply)); |
| 578 | reply.WhoInit = s->who_init; |
| 579 | reply.MsgLength = sizeof(reply) / 4; |
| 580 | reply.Function = req->Function; |
| 581 | reply.MaxDevices = s->max_devices; |
| 582 | reply.MaxBuses = s->max_buses; |
| 583 | reply.MsgContext = req->MsgContext; |
| 584 | |
| 585 | mptsas_fix_ioc_init_reply_endianness(&reply); |
| 586 | mptsas_reply(s, (MPIDefaultReply *)&reply); |
| 587 | } |
| 588 | |
| 589 | static void mptsas_process_ioc_facts(MPTSASState *s, |
| 590 | MPIMsgIOCFacts *req) |
| 591 | { |
| 592 | MPIMsgIOCFactsReply reply; |
| 593 | |
| 594 | mptsas_fix_ioc_facts_endianness(req); |
| 595 | |
| 596 | QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); |
| 597 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); |
| 598 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); |
| 599 | |
| 600 | memset(&reply, 0, sizeof(reply)); |
| 601 | reply.MsgVersion = 0x0105; |
| 602 | reply.MsgLength = sizeof(reply) / 4; |
| 603 | reply.Function = req->Function; |
| 604 | reply.MsgContext = req->MsgContext; |
| 605 | reply.MaxChainDepth = MPTSAS_MAXIMUM_CHAIN_DEPTH; |
| 606 | reply.WhoInit = s->who_init; |
| 607 | reply.BlockSize = MPTSAS_MAX_REQUEST_SIZE / sizeof(uint32_t); |
| 608 | reply.ReplyQueueDepth = ARRAY_SIZE(s->reply_post) - 1; |
| 609 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->reply_post) != ARRAY_SIZE(s->reply_free)); |
| 610 | |
| 611 | reply.RequestFrameSize = 128; |
| 612 | reply.ProductID = MPTSAS1068_PRODUCT_ID; |
| 613 | reply.CurrentHostMfaHighAddr = s->host_mfa_high_addr >> 32; |
| 614 | reply.GlobalCredits = ARRAY_SIZE(s->request_post) - 1; |
| 615 | reply.NumberOfPorts = MPTSAS_NUM_PORTS; |
| 616 | reply.CurrentSenseBufferHighAddr = s->sense_buffer_high_addr >> 32; |
| 617 | reply.CurReplyFrameSize = s->reply_frame_size; |
| 618 | reply.MaxDevices = s->max_devices; |
| 619 | reply.MaxBuses = s->max_buses; |
| 620 | reply.FWVersionDev = 0; |
| 621 | reply.FWVersionUnit = 0x92; |
| 622 | reply.FWVersionMinor = 0x32; |
| 623 | reply.FWVersionMajor = 0x1; |
| 624 | |
| 625 | mptsas_fix_ioc_facts_reply_endianness(&reply); |
| 626 | mptsas_reply(s, (MPIDefaultReply *)&reply); |
| 627 | } |
| 628 | |
| 629 | static void mptsas_process_port_facts(MPTSASState *s, |
| 630 | MPIMsgPortFacts *req) |
| 631 | { |
| 632 | MPIMsgPortFactsReply reply; |
| 633 | |
| 634 | mptsas_fix_port_facts_endianness(req); |
| 635 | |
| 636 | QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); |
| 637 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); |
| 638 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); |
| 639 | |
| 640 | memset(&reply, 0, sizeof(reply)); |
| 641 | reply.MsgLength = sizeof(reply) / 4; |
| 642 | reply.Function = req->Function; |
| 643 | reply.PortNumber = req->PortNumber; |
| 644 | reply.MsgContext = req->MsgContext; |
| 645 | |
| 646 | if (req->PortNumber < MPTSAS_NUM_PORTS) { |
| 647 | reply.PortType = MPI_PORTFACTS_PORTTYPE_SAS; |
| 648 | reply.MaxDevices = MPTSAS_NUM_PORTS; |
| 649 | reply.PortSCSIID = MPTSAS_NUM_PORTS; |
| 650 | reply.ProtocolFlags = MPI_PORTFACTS_PROTOCOL_LOGBUSADDR | MPI_PORTFACTS_PROTOCOL_INITIATOR; |
| 651 | } |
| 652 | |
| 653 | mptsas_fix_port_facts_reply_endianness(&reply); |
| 654 | mptsas_reply(s, (MPIDefaultReply *)&reply); |
| 655 | } |
| 656 | |
| 657 | static void mptsas_process_port_enable(MPTSASState *s, |
| 658 | MPIMsgPortEnable *req) |
| 659 | { |
| 660 | MPIMsgPortEnableReply reply; |
| 661 | |
| 662 | mptsas_fix_port_enable_endianness(req); |
| 663 | |
| 664 | QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); |
| 665 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); |
| 666 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); |
| 667 | |
| 668 | memset(&reply, 0, sizeof(reply)); |
| 669 | reply.MsgLength = sizeof(reply) / 4; |
| 670 | reply.PortNumber = req->PortNumber; |
| 671 | reply.Function = req->Function; |
| 672 | reply.MsgContext = req->MsgContext; |
| 673 | |
| 674 | mptsas_fix_port_enable_reply_endianness(&reply); |
| 675 | mptsas_reply(s, (MPIDefaultReply *)&reply); |
| 676 | } |
| 677 | |
| 678 | static void mptsas_process_event_notification(MPTSASState *s, |
| 679 | MPIMsgEventNotify *req) |
| 680 | { |
| 681 | MPIMsgEventNotifyReply reply; |
| 682 | |
| 683 | mptsas_fix_event_notification_endianness(req); |
| 684 | |
| 685 | QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req)); |
| 686 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req)); |
| 687 | QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply)); |
| 688 | |
| 689 | /* Don't even bother storing whether event notification is enabled, |
| 690 | * since it is not accessible. |
| 691 | */ |
| 692 | |
| 693 | memset(&reply, 0, sizeof(reply)); |
| 694 | reply.EventDataLength = sizeof(reply.Data) / 4; |
| 695 | reply.MsgLength = sizeof(reply) / 4; |
| 696 | reply.Function = req->Function; |
| 697 | |
| 698 | /* This is set because events are sent through the reply FIFOs. */ |
| 699 | reply.MsgFlags = MPI_MSGFLAGS_CONTINUATION_REPLY; |
| 700 | |
| 701 | reply.MsgContext = req->MsgContext; |
| 702 | reply.Event = MPI_EVENT_EVENT_CHANGE; |
| 703 | reply.Data[0] = !!req->Switch; |
| 704 | |
| 705 | mptsas_fix_event_notification_reply_endianness(&reply); |
| 706 | mptsas_reply(s, (MPIDefaultReply *)&reply); |
| 707 | } |
| 708 | |
| 709 | static void mptsas_process_message(MPTSASState *s, MPIRequestHeader *req) |
| 710 | { |
| 711 | trace_mptsas_process_message(s, req->Function, req->MsgContext); |
| 712 | switch (req->Function) { |
| 713 | case MPI_FUNCTION_SCSI_TASK_MGMT: |
| 714 | mptsas_process_scsi_task_mgmt(s, (MPIMsgSCSITaskMgmt *)req); |
| 715 | break; |
| 716 | |
| 717 | case MPI_FUNCTION_IOC_INIT: |
| 718 | mptsas_process_ioc_init(s, (MPIMsgIOCInit *)req); |
| 719 | break; |
| 720 | |
| 721 | case MPI_FUNCTION_IOC_FACTS: |
| 722 | mptsas_process_ioc_facts(s, (MPIMsgIOCFacts *)req); |
| 723 | break; |
| 724 | |
| 725 | case MPI_FUNCTION_PORT_FACTS: |
| 726 | mptsas_process_port_facts(s, (MPIMsgPortFacts *)req); |
| 727 | break; |
| 728 | |
| 729 | case MPI_FUNCTION_PORT_ENABLE: |
| 730 | mptsas_process_port_enable(s, (MPIMsgPortEnable *)req); |
| 731 | break; |
| 732 | |
| 733 | case MPI_FUNCTION_EVENT_NOTIFICATION: |
| 734 | mptsas_process_event_notification(s, (MPIMsgEventNotify *)req); |
| 735 | break; |
| 736 | |
| 737 | case MPI_FUNCTION_CONFIG: |
| 738 | mptsas_process_config(s, (MPIMsgConfig *)req); |
| 739 | break; |
| 740 | |
| 741 | default: |
| 742 | trace_mptsas_unhandled_cmd(s, req->Function, 0); |
| 743 | mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_FUNCTION); |
| 744 | break; |
| 745 | } |
| 746 | } |
| 747 | |
| 748 | static void mptsas_fetch_request(MPTSASState *s) |
| 749 | { |
| 750 | PCIDevice *pci = (PCIDevice *) s; |
| 751 | char req[MPTSAS_MAX_REQUEST_SIZE]; |
| 752 | MPIRequestHeader *hdr = (MPIRequestHeader *)req; |
| 753 | hwaddr addr; |
| 754 | int size; |
| 755 | |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 756 | /* Read the message header from the guest first. */ |
| 757 | addr = s->host_mfa_high_addr | MPTSAS_FIFO_GET(s, request_post); |
Li Qiang | b01a2d0 | 2017-03-14 03:56:20 -0700 | [diff] [blame] | 758 | pci_dma_read(pci, addr, req, sizeof(*hdr)); |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 759 | |
| 760 | if (hdr->Function < ARRAY_SIZE(mpi_request_sizes) && |
| 761 | mpi_request_sizes[hdr->Function]) { |
| 762 | /* Read the rest of the request based on the type. Do not |
| 763 | * reread everything, as that could cause a TOC/TOU mismatch |
| 764 | * and leak data from the QEMU stack. |
| 765 | */ |
| 766 | size = mpi_request_sizes[hdr->Function]; |
| 767 | assert(size <= MPTSAS_MAX_REQUEST_SIZE); |
Li Qiang | b01a2d0 | 2017-03-14 03:56:20 -0700 | [diff] [blame] | 768 | pci_dma_read(pci, addr + sizeof(*hdr), &req[sizeof(*hdr)], |
| 769 | size - sizeof(*hdr)); |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 770 | } |
| 771 | |
| 772 | if (hdr->Function == MPI_FUNCTION_SCSI_IO_REQUEST) { |
| 773 | /* SCSI I/O requests are separate from mptsas_process_message |
| 774 | * because they cannot be sent through the doorbell yet. |
| 775 | */ |
| 776 | mptsas_process_scsi_io_request(s, (MPIMsgSCSIIORequest *)req, addr); |
| 777 | } else { |
| 778 | mptsas_process_message(s, (MPIRequestHeader *)req); |
| 779 | } |
| 780 | } |
| 781 | |
| 782 | static void mptsas_fetch_requests(void *opaque) |
| 783 | { |
| 784 | MPTSASState *s = opaque; |
| 785 | |
Prasad J Pandit | 0663055 | 2016-05-24 13:37:44 +0530 | [diff] [blame] | 786 | if (s->state != MPI_IOC_STATE_OPERATIONAL) { |
| 787 | mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_STATE); |
| 788 | return; |
| 789 | } |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 790 | while (!MPTSAS_FIFO_EMPTY(s, request_post)) { |
| 791 | mptsas_fetch_request(s); |
| 792 | } |
| 793 | } |
| 794 | |
| 795 | static void mptsas_soft_reset(MPTSASState *s) |
| 796 | { |
| 797 | uint32_t save_mask; |
| 798 | |
| 799 | trace_mptsas_reset(s); |
| 800 | |
| 801 | /* Temporarily disable interrupts */ |
| 802 | save_mask = s->intr_mask; |
| 803 | s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; |
| 804 | mptsas_update_interrupt(s); |
| 805 | |
| 806 | qbus_reset_all(&s->bus.qbus); |
| 807 | s->intr_status = 0; |
| 808 | s->intr_mask = save_mask; |
| 809 | |
| 810 | s->reply_free_tail = 0; |
| 811 | s->reply_free_head = 0; |
| 812 | s->reply_post_tail = 0; |
| 813 | s->reply_post_head = 0; |
| 814 | s->request_post_tail = 0; |
| 815 | s->request_post_head = 0; |
| 816 | qemu_bh_cancel(s->request_bh); |
| 817 | |
| 818 | s->state = MPI_IOC_STATE_READY; |
| 819 | } |
| 820 | |
| 821 | static uint32_t mptsas_doorbell_read(MPTSASState *s) |
| 822 | { |
| 823 | uint32_t ret; |
| 824 | |
Paolo Bonzini | 9155b76 | 2016-02-16 08:49:15 +0100 | [diff] [blame] | 825 | ret = (s->who_init << MPI_DOORBELL_WHO_INIT_SHIFT) & MPI_DOORBELL_WHO_INIT_MASK; |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 826 | ret |= s->state; |
| 827 | switch (s->doorbell_state) { |
| 828 | case DOORBELL_NONE: |
| 829 | break; |
| 830 | |
| 831 | case DOORBELL_WRITE: |
| 832 | ret |= MPI_DOORBELL_ACTIVE; |
| 833 | break; |
| 834 | |
| 835 | case DOORBELL_READ: |
| 836 | /* Get rid of the IOC fault code. */ |
| 837 | ret &= ~MPI_DOORBELL_DATA_MASK; |
| 838 | |
| 839 | assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); |
| 840 | assert(s->doorbell_reply_idx <= s->doorbell_reply_size); |
| 841 | |
| 842 | ret |= MPI_DOORBELL_ACTIVE; |
| 843 | if (s->doorbell_reply_idx < s->doorbell_reply_size) { |
| 844 | /* For more information about this endian switch, see the |
| 845 | * commit message for commit 36b62ae ("fw_cfg: fix endianness in |
| 846 | * fw_cfg_data_mem_read() / _write()", 2015-01-16). |
| 847 | */ |
| 848 | ret |= le16_to_cpu(s->doorbell_reply[s->doorbell_reply_idx++]); |
| 849 | } |
| 850 | break; |
| 851 | |
| 852 | default: |
| 853 | abort(); |
| 854 | } |
| 855 | |
| 856 | return ret; |
| 857 | } |
| 858 | |
| 859 | static void mptsas_doorbell_write(MPTSASState *s, uint32_t val) |
| 860 | { |
| 861 | if (s->doorbell_state == DOORBELL_WRITE) { |
| 862 | if (s->doorbell_idx < s->doorbell_cnt) { |
| 863 | /* For more information about this endian switch, see the |
| 864 | * commit message for commit 36b62ae ("fw_cfg: fix endianness in |
| 865 | * fw_cfg_data_mem_read() / _write()", 2015-01-16). |
| 866 | */ |
| 867 | s->doorbell_msg[s->doorbell_idx++] = cpu_to_le32(val); |
| 868 | if (s->doorbell_idx == s->doorbell_cnt) { |
| 869 | mptsas_process_message(s, (MPIRequestHeader *)s->doorbell_msg); |
| 870 | } |
| 871 | } |
| 872 | return; |
| 873 | } |
| 874 | |
| 875 | switch ((val & MPI_DOORBELL_FUNCTION_MASK) >> MPI_DOORBELL_FUNCTION_SHIFT) { |
| 876 | case MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET: |
| 877 | mptsas_soft_reset(s); |
| 878 | break; |
| 879 | case MPI_FUNCTION_IO_UNIT_RESET: |
| 880 | break; |
| 881 | case MPI_FUNCTION_HANDSHAKE: |
| 882 | s->doorbell_state = DOORBELL_WRITE; |
| 883 | s->doorbell_idx = 0; |
| 884 | s->doorbell_cnt = (val & MPI_DOORBELL_ADD_DWORDS_MASK) |
| 885 | >> MPI_DOORBELL_ADD_DWORDS_SHIFT; |
| 886 | s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT; |
| 887 | mptsas_update_interrupt(s); |
| 888 | break; |
| 889 | default: |
| 890 | trace_mptsas_unhandled_doorbell_cmd(s, val); |
| 891 | break; |
| 892 | } |
| 893 | } |
| 894 | |
| 895 | static void mptsas_write_sequence_write(MPTSASState *s, uint32_t val) |
| 896 | { |
| 897 | /* If the diagnostic register is enabled, any write to this register |
| 898 | * will disable it. Otherwise, the guest has to do a magic five-write |
| 899 | * sequence. |
| 900 | */ |
| 901 | if (s->diagnostic & MPI_DIAG_DRWE) { |
| 902 | goto disable; |
| 903 | } |
| 904 | |
| 905 | switch (s->diagnostic_idx) { |
| 906 | case 0: |
| 907 | if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_1ST_KEY_VALUE) { |
| 908 | goto disable; |
| 909 | } |
| 910 | break; |
| 911 | case 1: |
| 912 | if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_2ND_KEY_VALUE) { |
| 913 | goto disable; |
| 914 | } |
| 915 | break; |
| 916 | case 2: |
| 917 | if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_3RD_KEY_VALUE) { |
| 918 | goto disable; |
| 919 | } |
| 920 | break; |
| 921 | case 3: |
| 922 | if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_4TH_KEY_VALUE) { |
| 923 | goto disable; |
| 924 | } |
| 925 | break; |
| 926 | case 4: |
| 927 | if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_5TH_KEY_VALUE) { |
| 928 | goto disable; |
| 929 | } |
| 930 | /* Prepare Spaceball One for departure, and change the |
| 931 | * combination on my luggage! |
| 932 | */ |
| 933 | s->diagnostic |= MPI_DIAG_DRWE; |
| 934 | break; |
| 935 | } |
| 936 | s->diagnostic_idx++; |
| 937 | return; |
| 938 | |
| 939 | disable: |
| 940 | s->diagnostic &= ~MPI_DIAG_DRWE; |
| 941 | s->diagnostic_idx = 0; |
| 942 | } |
| 943 | |
| 944 | static int mptsas_hard_reset(MPTSASState *s) |
| 945 | { |
| 946 | mptsas_soft_reset(s); |
| 947 | |
| 948 | s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM; |
| 949 | |
| 950 | s->host_mfa_high_addr = 0; |
| 951 | s->sense_buffer_high_addr = 0; |
| 952 | s->reply_frame_size = 0; |
| 953 | s->max_devices = MPTSAS_NUM_PORTS; |
| 954 | s->max_buses = 1; |
| 955 | |
| 956 | return 0; |
| 957 | } |
| 958 | |
| 959 | static void mptsas_interrupt_status_write(MPTSASState *s) |
| 960 | { |
| 961 | switch (s->doorbell_state) { |
| 962 | case DOORBELL_NONE: |
| 963 | case DOORBELL_WRITE: |
| 964 | s->intr_status &= ~MPI_HIS_DOORBELL_INTERRUPT; |
| 965 | break; |
| 966 | |
| 967 | case DOORBELL_READ: |
| 968 | /* The reply can be read continuously, so leave the interrupt up. */ |
| 969 | assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT); |
| 970 | if (s->doorbell_reply_idx == s->doorbell_reply_size) { |
| 971 | s->doorbell_state = DOORBELL_NONE; |
| 972 | } |
| 973 | break; |
| 974 | |
| 975 | default: |
| 976 | abort(); |
| 977 | } |
| 978 | mptsas_update_interrupt(s); |
| 979 | } |
| 980 | |
| 981 | static uint32_t mptsas_reply_post_read(MPTSASState *s) |
| 982 | { |
| 983 | uint32_t ret; |
| 984 | |
| 985 | if (!MPTSAS_FIFO_EMPTY(s, reply_post)) { |
| 986 | ret = MPTSAS_FIFO_GET(s, reply_post); |
| 987 | } else { |
| 988 | ret = -1; |
| 989 | s->intr_status &= ~MPI_HIS_REPLY_MESSAGE_INTERRUPT; |
| 990 | mptsas_update_interrupt(s); |
| 991 | } |
| 992 | |
| 993 | return ret; |
| 994 | } |
| 995 | |
| 996 | static uint64_t mptsas_mmio_read(void *opaque, hwaddr addr, |
| 997 | unsigned size) |
| 998 | { |
| 999 | MPTSASState *s = opaque; |
| 1000 | uint32_t ret = 0; |
| 1001 | |
| 1002 | switch (addr & ~3) { |
| 1003 | case MPI_DOORBELL_OFFSET: |
| 1004 | ret = mptsas_doorbell_read(s); |
| 1005 | break; |
| 1006 | |
| 1007 | case MPI_DIAGNOSTIC_OFFSET: |
| 1008 | ret = s->diagnostic; |
| 1009 | break; |
| 1010 | |
| 1011 | case MPI_HOST_INTERRUPT_STATUS_OFFSET: |
| 1012 | ret = s->intr_status; |
| 1013 | break; |
| 1014 | |
| 1015 | case MPI_HOST_INTERRUPT_MASK_OFFSET: |
| 1016 | ret = s->intr_mask; |
| 1017 | break; |
| 1018 | |
| 1019 | case MPI_REPLY_POST_FIFO_OFFSET: |
| 1020 | ret = mptsas_reply_post_read(s); |
| 1021 | break; |
| 1022 | |
| 1023 | default: |
| 1024 | trace_mptsas_mmio_unhandled_read(s, addr); |
| 1025 | break; |
| 1026 | } |
| 1027 | trace_mptsas_mmio_read(s, addr, ret); |
| 1028 | return ret; |
| 1029 | } |
| 1030 | |
| 1031 | static void mptsas_mmio_write(void *opaque, hwaddr addr, |
| 1032 | uint64_t val, unsigned size) |
| 1033 | { |
| 1034 | MPTSASState *s = opaque; |
| 1035 | |
| 1036 | trace_mptsas_mmio_write(s, addr, val); |
| 1037 | switch (addr) { |
| 1038 | case MPI_DOORBELL_OFFSET: |
| 1039 | mptsas_doorbell_write(s, val); |
| 1040 | break; |
| 1041 | |
| 1042 | case MPI_WRITE_SEQUENCE_OFFSET: |
| 1043 | mptsas_write_sequence_write(s, val); |
| 1044 | break; |
| 1045 | |
| 1046 | case MPI_DIAGNOSTIC_OFFSET: |
| 1047 | if (val & MPI_DIAG_RESET_ADAPTER) { |
| 1048 | mptsas_hard_reset(s); |
| 1049 | } |
| 1050 | break; |
| 1051 | |
| 1052 | case MPI_HOST_INTERRUPT_STATUS_OFFSET: |
| 1053 | mptsas_interrupt_status_write(s); |
| 1054 | break; |
| 1055 | |
| 1056 | case MPI_HOST_INTERRUPT_MASK_OFFSET: |
| 1057 | s->intr_mask = val & (MPI_HIM_RIM | MPI_HIM_DIM); |
| 1058 | mptsas_update_interrupt(s); |
| 1059 | break; |
| 1060 | |
| 1061 | case MPI_REQUEST_POST_FIFO_OFFSET: |
| 1062 | if (MPTSAS_FIFO_FULL(s, request_post)) { |
| 1063 | mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); |
| 1064 | } else { |
| 1065 | MPTSAS_FIFO_PUT(s, request_post, val & ~0x03); |
| 1066 | qemu_bh_schedule(s->request_bh); |
| 1067 | } |
| 1068 | break; |
| 1069 | |
| 1070 | case MPI_REPLY_FREE_FIFO_OFFSET: |
| 1071 | if (MPTSAS_FIFO_FULL(s, reply_free)) { |
| 1072 | mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES); |
| 1073 | } else { |
| 1074 | MPTSAS_FIFO_PUT(s, reply_free, val); |
| 1075 | } |
| 1076 | break; |
| 1077 | |
| 1078 | default: |
| 1079 | trace_mptsas_mmio_unhandled_write(s, addr, val); |
| 1080 | break; |
| 1081 | } |
| 1082 | } |
| 1083 | |
| 1084 | static const MemoryRegionOps mptsas_mmio_ops = { |
| 1085 | .read = mptsas_mmio_read, |
| 1086 | .write = mptsas_mmio_write, |
| 1087 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1088 | .impl = { |
| 1089 | .min_access_size = 4, |
| 1090 | .max_access_size = 4, |
| 1091 | } |
| 1092 | }; |
| 1093 | |
| 1094 | static const MemoryRegionOps mptsas_port_ops = { |
| 1095 | .read = mptsas_mmio_read, |
| 1096 | .write = mptsas_mmio_write, |
| 1097 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1098 | .impl = { |
| 1099 | .min_access_size = 4, |
| 1100 | .max_access_size = 4, |
| 1101 | } |
| 1102 | }; |
| 1103 | |
| 1104 | static uint64_t mptsas_diag_read(void *opaque, hwaddr addr, |
| 1105 | unsigned size) |
| 1106 | { |
| 1107 | MPTSASState *s = opaque; |
| 1108 | trace_mptsas_diag_read(s, addr, 0); |
| 1109 | return 0; |
| 1110 | } |
| 1111 | |
| 1112 | static void mptsas_diag_write(void *opaque, hwaddr addr, |
| 1113 | uint64_t val, unsigned size) |
| 1114 | { |
| 1115 | MPTSASState *s = opaque; |
| 1116 | trace_mptsas_diag_write(s, addr, val); |
| 1117 | } |
| 1118 | |
| 1119 | static const MemoryRegionOps mptsas_diag_ops = { |
| 1120 | .read = mptsas_diag_read, |
| 1121 | .write = mptsas_diag_write, |
| 1122 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1123 | .impl = { |
| 1124 | .min_access_size = 4, |
| 1125 | .max_access_size = 4, |
| 1126 | } |
| 1127 | }; |
| 1128 | |
| 1129 | static QEMUSGList *mptsas_get_sg_list(SCSIRequest *sreq) |
| 1130 | { |
| 1131 | MPTSASRequest *req = sreq->hba_private; |
| 1132 | |
| 1133 | return &req->qsg; |
| 1134 | } |
| 1135 | |
| 1136 | static void mptsas_command_complete(SCSIRequest *sreq, |
| 1137 | uint32_t status, size_t resid) |
| 1138 | { |
| 1139 | MPTSASRequest *req = sreq->hba_private; |
| 1140 | MPTSASState *s = req->dev; |
| 1141 | uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; |
| 1142 | uint8_t sense_len; |
| 1143 | |
| 1144 | hwaddr sense_buffer_addr = req->dev->sense_buffer_high_addr | |
| 1145 | req->scsi_io.SenseBufferLowAddr; |
| 1146 | |
| 1147 | trace_mptsas_command_complete(s, req->scsi_io.MsgContext, status, resid); |
| 1148 | |
| 1149 | sense_len = scsi_req_get_sense(sreq, sense_buf, SCSI_SENSE_BUF_SIZE); |
| 1150 | if (sense_len > 0) { |
| 1151 | pci_dma_write(PCI_DEVICE(s), sense_buffer_addr, sense_buf, |
| 1152 | MIN(req->scsi_io.SenseBufferLength, sense_len)); |
| 1153 | } |
| 1154 | |
| 1155 | if (sreq->status != GOOD || resid || |
| 1156 | req->dev->doorbell_state == DOORBELL_WRITE) { |
| 1157 | MPIMsgSCSIIOReply reply; |
| 1158 | |
| 1159 | memset(&reply, 0, sizeof(reply)); |
| 1160 | reply.TargetID = req->scsi_io.TargetID; |
| 1161 | reply.Bus = req->scsi_io.Bus; |
| 1162 | reply.MsgLength = sizeof(reply) / 4; |
| 1163 | reply.Function = req->scsi_io.Function; |
| 1164 | reply.CDBLength = req->scsi_io.CDBLength; |
| 1165 | reply.SenseBufferLength = req->scsi_io.SenseBufferLength; |
| 1166 | reply.MsgFlags = req->scsi_io.MsgFlags; |
| 1167 | reply.MsgContext = req->scsi_io.MsgContext; |
| 1168 | reply.SCSIStatus = sreq->status; |
| 1169 | if (sreq->status == GOOD) { |
| 1170 | reply.TransferCount = req->scsi_io.DataLength - resid; |
| 1171 | if (resid) { |
| 1172 | reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; |
| 1173 | } |
| 1174 | } else { |
| 1175 | reply.SCSIState = MPI_SCSI_STATE_AUTOSENSE_VALID; |
| 1176 | reply.SenseCount = sense_len; |
| 1177 | reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN; |
| 1178 | } |
| 1179 | |
| 1180 | mptsas_fix_scsi_io_reply_endianness(&reply); |
| 1181 | mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); |
| 1182 | } else { |
| 1183 | mptsas_turbo_reply(req->dev, req->scsi_io.MsgContext); |
| 1184 | } |
| 1185 | |
| 1186 | mptsas_free_request(req); |
| 1187 | } |
| 1188 | |
| 1189 | static void mptsas_request_cancelled(SCSIRequest *sreq) |
| 1190 | { |
| 1191 | MPTSASRequest *req = sreq->hba_private; |
| 1192 | MPIMsgSCSIIOReply reply; |
| 1193 | |
| 1194 | memset(&reply, 0, sizeof(reply)); |
| 1195 | reply.TargetID = req->scsi_io.TargetID; |
| 1196 | reply.Bus = req->scsi_io.Bus; |
| 1197 | reply.MsgLength = sizeof(reply) / 4; |
| 1198 | reply.Function = req->scsi_io.Function; |
| 1199 | reply.CDBLength = req->scsi_io.CDBLength; |
| 1200 | reply.SenseBufferLength = req->scsi_io.SenseBufferLength; |
| 1201 | reply.MsgFlags = req->scsi_io.MsgFlags; |
| 1202 | reply.MsgContext = req->scsi_io.MsgContext; |
| 1203 | reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS; |
| 1204 | reply.IOCStatus = MPI_IOCSTATUS_SCSI_TASK_TERMINATED; |
| 1205 | |
| 1206 | mptsas_fix_scsi_io_reply_endianness(&reply); |
| 1207 | mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply); |
| 1208 | mptsas_free_request(req); |
| 1209 | } |
| 1210 | |
| 1211 | static void mptsas_save_request(QEMUFile *f, SCSIRequest *sreq) |
| 1212 | { |
| 1213 | MPTSASRequest *req = sreq->hba_private; |
| 1214 | int i; |
| 1215 | |
| 1216 | qemu_put_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); |
| 1217 | qemu_put_be32(f, req->qsg.nsg); |
| 1218 | for (i = 0; i < req->qsg.nsg; i++) { |
| 1219 | qemu_put_be64(f, req->qsg.sg[i].base); |
| 1220 | qemu_put_be64(f, req->qsg.sg[i].len); |
| 1221 | } |
| 1222 | } |
| 1223 | |
| 1224 | static void *mptsas_load_request(QEMUFile *f, SCSIRequest *sreq) |
| 1225 | { |
| 1226 | SCSIBus *bus = sreq->bus; |
| 1227 | MPTSASState *s = container_of(bus, MPTSASState, bus); |
| 1228 | PCIDevice *pci = PCI_DEVICE(s); |
| 1229 | MPTSASRequest *req; |
| 1230 | int i, n; |
| 1231 | |
| 1232 | req = g_new(MPTSASRequest, 1); |
| 1233 | qemu_get_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io)); |
| 1234 | |
| 1235 | n = qemu_get_be32(f); |
| 1236 | /* TODO: add a way for SCSIBusInfo's load_request to fail, |
| 1237 | * and fail migration instead of asserting here. |
Eric Blake | 262a69f | 2017-09-11 16:13:20 -0500 | [diff] [blame] | 1238 | * This is just one thing (there are probably more) that must be |
| 1239 | * fixed before we can allow NDEBUG compilation. |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1240 | */ |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1241 | assert(n >= 0); |
| 1242 | |
| 1243 | pci_dma_sglist_init(&req->qsg, pci, n); |
| 1244 | for (i = 0; i < n; i++) { |
| 1245 | uint64_t base = qemu_get_be64(f); |
| 1246 | uint64_t len = qemu_get_be64(f); |
| 1247 | qemu_sglist_add(&req->qsg, base, len); |
| 1248 | } |
| 1249 | |
| 1250 | scsi_req_ref(sreq); |
| 1251 | req->sreq = sreq; |
| 1252 | req->dev = s; |
| 1253 | |
| 1254 | return req; |
| 1255 | } |
| 1256 | |
| 1257 | static const struct SCSIBusInfo mptsas_scsi_info = { |
| 1258 | .tcq = true, |
| 1259 | .max_target = MPTSAS_NUM_PORTS, |
| 1260 | .max_lun = 1, |
| 1261 | |
| 1262 | .get_sg_list = mptsas_get_sg_list, |
| 1263 | .complete = mptsas_command_complete, |
| 1264 | .cancel = mptsas_request_cancelled, |
| 1265 | .save_request = mptsas_save_request, |
| 1266 | .load_request = mptsas_load_request, |
| 1267 | }; |
| 1268 | |
Cao jin | afe4c95 | 2016-06-20 14:13:33 +0800 | [diff] [blame] | 1269 | static void mptsas_scsi_realize(PCIDevice *dev, Error **errp) |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1270 | { |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1271 | MPTSASState *s = MPT_SAS(dev); |
Cao jin | 1108b2f | 2016-06-20 14:13:39 +0800 | [diff] [blame] | 1272 | Error *err = NULL; |
| 1273 | int ret; |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1274 | |
| 1275 | dev->config[PCI_LATENCY_TIMER] = 0; |
| 1276 | dev->config[PCI_INTERRUPT_PIN] = 0x01; |
| 1277 | |
Cao jin | 1108b2f | 2016-06-20 14:13:39 +0800 | [diff] [blame] | 1278 | if (s->msi != ON_OFF_AUTO_OFF) { |
| 1279 | ret = msi_init(dev, 0, 1, true, false, &err); |
| 1280 | /* Any error other than -ENOTSUP(board's MSI support is broken) |
| 1281 | * is a programming error */ |
| 1282 | assert(!ret || ret == -ENOTSUP); |
| 1283 | if (ret && s->msi == ON_OFF_AUTO_ON) { |
| 1284 | /* Can't satisfy user's explicit msi=on request, fail */ |
| 1285 | error_append_hint(&err, "You have to use msi=auto (default) or " |
| 1286 | "msi=off with this machine type.\n"); |
| 1287 | error_propagate(errp, err); |
Cao jin | 1108b2f | 2016-06-20 14:13:39 +0800 | [diff] [blame] | 1288 | return; |
Cao jin | 1108b2f | 2016-06-20 14:13:39 +0800 | [diff] [blame] | 1289 | } |
Cao jin | 2e2aa31 | 2016-06-20 14:13:41 +0800 | [diff] [blame] | 1290 | assert(!err || s->msi == ON_OFF_AUTO_AUTO); |
| 1291 | /* With msi=auto, we fall back to MSI off silently */ |
| 1292 | error_free(err); |
| 1293 | |
Paolo Bonzini | 0b646f4 | 2016-08-01 10:25:05 +0200 | [diff] [blame] | 1294 | /* Only used for migration. */ |
| 1295 | s->msi_in_use = (ret == 0); |
Cao jin | 1108b2f | 2016-06-20 14:13:39 +0800 | [diff] [blame] | 1296 | } |
| 1297 | |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1298 | memory_region_init_io(&s->mmio_io, OBJECT(s), &mptsas_mmio_ops, s, |
| 1299 | "mptsas-mmio", 0x4000); |
| 1300 | memory_region_init_io(&s->port_io, OBJECT(s), &mptsas_port_ops, s, |
| 1301 | "mptsas-io", 256); |
| 1302 | memory_region_init_io(&s->diag_io, OBJECT(s), &mptsas_diag_ops, s, |
| 1303 | "mptsas-diag", 0x10000); |
| 1304 | |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1305 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io); |
| 1306 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY | |
| 1307 | PCI_BASE_ADDRESS_MEM_TYPE_32, &s->mmio_io); |
| 1308 | pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY | |
| 1309 | PCI_BASE_ADDRESS_MEM_TYPE_32, &s->diag_io); |
| 1310 | |
| 1311 | if (!s->sas_addr) { |
| 1312 | s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) | |
| 1313 | IEEE_COMPANY_LOCALLY_ASSIGNED) << 36; |
David Gibson | cdc5747 | 2017-11-29 19:46:26 +1100 | [diff] [blame] | 1314 | s->sas_addr |= (pci_dev_bus_num(dev) << 16); |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1315 | s->sas_addr |= (PCI_SLOT(dev->devfn) << 8); |
| 1316 | s->sas_addr |= PCI_FUNC(dev->devfn); |
| 1317 | } |
| 1318 | s->max_devices = MPTSAS_NUM_PORTS; |
| 1319 | |
| 1320 | s->request_bh = qemu_bh_new(mptsas_fetch_requests, s); |
| 1321 | |
| 1322 | QTAILQ_INIT(&s->pending); |
| 1323 | |
| 1324 | scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL); |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1325 | } |
| 1326 | |
| 1327 | static void mptsas_scsi_uninit(PCIDevice *dev) |
| 1328 | { |
| 1329 | MPTSASState *s = MPT_SAS(dev); |
| 1330 | |
| 1331 | qemu_bh_delete(s->request_bh); |
Cao jin | 2e2aa31 | 2016-06-20 14:13:41 +0800 | [diff] [blame] | 1332 | msi_uninit(dev); |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1333 | } |
| 1334 | |
| 1335 | static void mptsas_reset(DeviceState *dev) |
| 1336 | { |
| 1337 | MPTSASState *s = MPT_SAS(dev); |
| 1338 | |
| 1339 | mptsas_hard_reset(s); |
| 1340 | } |
| 1341 | |
| 1342 | static int mptsas_post_load(void *opaque, int version_id) |
| 1343 | { |
| 1344 | MPTSASState *s = opaque; |
| 1345 | |
| 1346 | if (s->doorbell_idx > s->doorbell_cnt || |
| 1347 | s->doorbell_cnt > ARRAY_SIZE(s->doorbell_msg) || |
| 1348 | s->doorbell_reply_idx > s->doorbell_reply_size || |
| 1349 | s->doorbell_reply_size > ARRAY_SIZE(s->doorbell_reply) || |
| 1350 | MPTSAS_FIFO_INVALID(s, request_post) || |
| 1351 | MPTSAS_FIFO_INVALID(s, reply_post) || |
| 1352 | MPTSAS_FIFO_INVALID(s, reply_free) || |
| 1353 | s->diagnostic_idx > 4) { |
| 1354 | return -EINVAL; |
| 1355 | } |
| 1356 | |
| 1357 | return 0; |
| 1358 | } |
| 1359 | |
| 1360 | static const VMStateDescription vmstate_mptsas = { |
| 1361 | .name = "mptsas", |
| 1362 | .version_id = 0, |
| 1363 | .minimum_version_id = 0, |
| 1364 | .minimum_version_id_old = 0, |
| 1365 | .post_load = mptsas_post_load, |
| 1366 | .fields = (VMStateField[]) { |
| 1367 | VMSTATE_PCI_DEVICE(dev, MPTSASState), |
Paolo Bonzini | 0b646f4 | 2016-08-01 10:25:05 +0200 | [diff] [blame] | 1368 | VMSTATE_BOOL(msi_in_use, MPTSASState), |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1369 | VMSTATE_UINT32(state, MPTSASState), |
| 1370 | VMSTATE_UINT8(who_init, MPTSASState), |
| 1371 | VMSTATE_UINT8(doorbell_state, MPTSASState), |
| 1372 | VMSTATE_UINT32_ARRAY(doorbell_msg, MPTSASState, 256), |
| 1373 | VMSTATE_INT32(doorbell_idx, MPTSASState), |
| 1374 | VMSTATE_INT32(doorbell_cnt, MPTSASState), |
| 1375 | |
| 1376 | VMSTATE_UINT16_ARRAY(doorbell_reply, MPTSASState, 256), |
| 1377 | VMSTATE_INT32(doorbell_reply_idx, MPTSASState), |
| 1378 | VMSTATE_INT32(doorbell_reply_size, MPTSASState), |
| 1379 | |
| 1380 | VMSTATE_UINT32(diagnostic, MPTSASState), |
| 1381 | VMSTATE_UINT8(diagnostic_idx, MPTSASState), |
| 1382 | |
| 1383 | VMSTATE_UINT32(intr_status, MPTSASState), |
| 1384 | VMSTATE_UINT32(intr_mask, MPTSASState), |
| 1385 | |
| 1386 | VMSTATE_UINT32_ARRAY(request_post, MPTSASState, |
| 1387 | MPTSAS_REQUEST_QUEUE_DEPTH + 1), |
| 1388 | VMSTATE_UINT16(request_post_head, MPTSASState), |
| 1389 | VMSTATE_UINT16(request_post_tail, MPTSASState), |
| 1390 | |
| 1391 | VMSTATE_UINT32_ARRAY(reply_post, MPTSASState, |
| 1392 | MPTSAS_REPLY_QUEUE_DEPTH + 1), |
| 1393 | VMSTATE_UINT16(reply_post_head, MPTSASState), |
| 1394 | VMSTATE_UINT16(reply_post_tail, MPTSASState), |
| 1395 | |
| 1396 | VMSTATE_UINT32_ARRAY(reply_free, MPTSASState, |
| 1397 | MPTSAS_REPLY_QUEUE_DEPTH + 1), |
| 1398 | VMSTATE_UINT16(reply_free_head, MPTSASState), |
| 1399 | VMSTATE_UINT16(reply_free_tail, MPTSASState), |
| 1400 | |
| 1401 | VMSTATE_UINT16(max_buses, MPTSASState), |
| 1402 | VMSTATE_UINT16(max_devices, MPTSASState), |
| 1403 | VMSTATE_UINT16(reply_frame_size, MPTSASState), |
| 1404 | VMSTATE_UINT64(host_mfa_high_addr, MPTSASState), |
| 1405 | VMSTATE_UINT64(sense_buffer_high_addr, MPTSASState), |
| 1406 | VMSTATE_END_OF_LIST() |
| 1407 | } |
| 1408 | }; |
| 1409 | |
| 1410 | static Property mptsas_properties[] = { |
| 1411 | DEFINE_PROP_UINT64("sas_address", MPTSASState, sas_addr, 0), |
| 1412 | /* TODO: test MSI support under Windows */ |
Cao jin | 444dd1a | 2016-06-20 14:13:36 +0800 | [diff] [blame] | 1413 | DEFINE_PROP_ON_OFF_AUTO("msi", MPTSASState, msi, ON_OFF_AUTO_AUTO), |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1414 | DEFINE_PROP_END_OF_LIST(), |
| 1415 | }; |
| 1416 | |
| 1417 | static void mptsas1068_class_init(ObjectClass *oc, void *data) |
| 1418 | { |
| 1419 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 1420 | PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); |
| 1421 | |
Cao jin | afe4c95 | 2016-06-20 14:13:33 +0800 | [diff] [blame] | 1422 | pc->realize = mptsas_scsi_realize; |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1423 | pc->exit = mptsas_scsi_uninit; |
| 1424 | pc->romfile = 0; |
| 1425 | pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; |
| 1426 | pc->device_id = PCI_DEVICE_ID_LSI_SAS1068; |
| 1427 | pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; |
| 1428 | pc->subsystem_id = 0x8000; |
| 1429 | pc->class_id = PCI_CLASS_STORAGE_SCSI; |
| 1430 | dc->props = mptsas_properties; |
| 1431 | dc->reset = mptsas_reset; |
| 1432 | dc->vmsd = &vmstate_mptsas; |
| 1433 | dc->desc = "LSI SAS 1068"; |
| 1434 | } |
| 1435 | |
| 1436 | static const TypeInfo mptsas_info = { |
| 1437 | .name = TYPE_MPTSAS1068, |
| 1438 | .parent = TYPE_PCI_DEVICE, |
| 1439 | .instance_size = sizeof(MPTSASState), |
| 1440 | .class_init = mptsas1068_class_init, |
Eduardo Habkost | fd3b02c | 2017-09-27 16:56:34 -0300 | [diff] [blame] | 1441 | .interfaces = (InterfaceInfo[]) { |
| 1442 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 1443 | { }, |
| 1444 | }, |
Paolo Bonzini | e351b82 | 2015-10-27 18:26:06 +0100 | [diff] [blame] | 1445 | }; |
| 1446 | |
| 1447 | static void mptsas_register_types(void) |
| 1448 | { |
| 1449 | type_register(&mptsas_info); |
| 1450 | } |
| 1451 | |
| 1452 | type_init(mptsas_register_types) |