Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 1 | /* |
| 2 | * MicroBlaze helper routines. |
| 3 | * |
| 4 | * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com> |
Peter A. G. Crosthwaite | dadc106 | 2012-04-12 14:30:30 +1000 | [diff] [blame] | 5 | * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
Chetan Pant | ee45203 | 2020-10-23 12:18:21 +0000 | [diff] [blame] | 10 | * version 2.1 of the License, or (at your option) any later version. |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 19 | */ |
| 20 | |
Peter Maydell | 8fd9dec | 2016-01-26 18:05:31 +0000 | [diff] [blame] | 21 | #include "qemu/osdep.h" |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 22 | #include "cpu.h" |
Paolo Bonzini | 63c9155 | 2016-03-15 13:18:37 +0100 | [diff] [blame] | 23 | #include "exec/exec-all.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 24 | #include "qemu/host-utils.h" |
Paolo Bonzini | 508127e | 2016-01-07 16:55:28 +0300 | [diff] [blame] | 25 | #include "exec/log.h" |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 26 | |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 27 | #if defined(CONFIG_USER_ONLY) |
| 28 | |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 29 | void mb_cpu_do_interrupt(CPUState *cs) |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 30 | { |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 31 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
| 32 | CPUMBState *env = &cpu->env; |
| 33 | |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 34 | cs->exception_index = -1; |
Peter A. G. Crosthwaite | 8cc9b43 | 2012-06-01 13:23:28 +1000 | [diff] [blame] | 35 | env->res_addr = RES_ADDR_NONE; |
Richard Henderson | 76e8187 | 2020-08-19 21:33:32 -0700 | [diff] [blame] | 36 | env->regs[14] = env->pc; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 37 | } |
| 38 | |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 39 | bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 40 | MMUAccessType access_type, int mmu_idx, |
| 41 | bool probe, uintptr_t retaddr) |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 42 | { |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 43 | cs->exception_index = 0xaa; |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 44 | cpu_loop_exit_restore(cs, retaddr); |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 45 | } |
| 46 | |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 47 | #else /* !CONFIG_USER_ONLY */ |
| 48 | |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 49 | bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 50 | MMUAccessType access_type, int mmu_idx, |
| 51 | bool probe, uintptr_t retaddr) |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 52 | { |
Andreas Färber | 7510454 | 2013-08-26 03:01:33 +0200 | [diff] [blame] | 53 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
| 54 | CPUMBState *env = &cpu->env; |
Richard Henderson | 8ce97bc | 2020-09-02 23:18:35 -0700 | [diff] [blame] | 55 | MicroBlazeMMULookup lu; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 56 | unsigned int hit; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 57 | int prot; |
| 58 | |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 59 | if (mmu_idx == MMU_NOMMU_IDX) { |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 60 | /* MMU disabled or not available. */ |
| 61 | address &= TARGET_PAGE_MASK; |
| 62 | prot = PAGE_BITS; |
Andreas Färber | 0c591eb | 2013-09-03 13:59:37 +0200 | [diff] [blame] | 63 | tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 64 | return true; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 65 | } |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 66 | |
Richard Henderson | de73ee1 | 2020-09-04 11:31:57 -0700 | [diff] [blame] | 67 | hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx); |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 68 | if (likely(hit)) { |
| 69 | uint32_t vaddr = address & TARGET_PAGE_MASK; |
| 70 | uint32_t paddr = lu.paddr + vaddr - lu.vaddr; |
| 71 | |
| 72 | qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", |
| 73 | mmu_idx, vaddr, paddr, lu.prot); |
| 74 | tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); |
| 75 | return true; |
| 76 | } |
| 77 | |
| 78 | /* TLB miss. */ |
| 79 | if (probe) { |
| 80 | return false; |
| 81 | } |
| 82 | |
| 83 | qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", |
| 84 | mmu_idx, address); |
| 85 | |
Richard Henderson | b2e80a3 | 2020-08-19 21:46:10 -0700 | [diff] [blame] | 86 | env->ear = address; |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 87 | switch (lu.err) { |
| 88 | case ERR_PROT: |
Richard Henderson | 78e9caf | 2020-08-19 21:50:35 -0700 | [diff] [blame] | 89 | env->esr = access_type == MMU_INST_FETCH ? 17 : 16; |
| 90 | env->esr |= (access_type == MMU_DATA_STORE) << 10; |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 91 | break; |
| 92 | case ERR_MISS: |
Richard Henderson | 78e9caf | 2020-08-19 21:50:35 -0700 | [diff] [blame] | 93 | env->esr = access_type == MMU_INST_FETCH ? 19 : 18; |
| 94 | env->esr |= (access_type == MMU_DATA_STORE) << 10; |
Richard Henderson | f429d60 | 2019-04-02 16:06:02 +0700 | [diff] [blame] | 95 | break; |
| 96 | default: |
| 97 | abort(); |
| 98 | } |
| 99 | |
| 100 | if (cs->exception_index == EXCP_MMU) { |
| 101 | cpu_abort(cs, "recursive faults\n"); |
| 102 | } |
| 103 | |
| 104 | /* TLB miss. */ |
| 105 | cs->exception_index = EXCP_MMU; |
| 106 | cpu_loop_exit_restore(cs, retaddr); |
| 107 | } |
| 108 | |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 109 | void mb_cpu_do_interrupt(CPUState *cs) |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 110 | { |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 111 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
| 112 | CPUMBState *env = &cpu->env; |
Richard Henderson | 1074c0f | 2020-08-18 11:58:23 -0700 | [diff] [blame] | 113 | uint32_t t, msr = mb_cpu_read_msr(env); |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 114 | bool set_esr; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 115 | |
Stefan Weil | 5225d66 | 2011-04-28 17:20:26 +0200 | [diff] [blame] | 116 | /* IMM flag cannot propagate across a branch and into the dslot. */ |
Richard Henderson | 88e74b6 | 2020-09-04 12:08:24 -0700 | [diff] [blame] | 117 | assert((env->iflags & (D_FLAG | IMM_FLAG)) != (D_FLAG | IMM_FLAG)); |
| 118 | /* BIMM flag cannot be set without D_FLAG. */ |
| 119 | assert((env->iflags & (D_FLAG | BIMM_FLAG)) != BIMM_FLAG); |
| 120 | /* RTI flags are private to translate. */ |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 121 | assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 122 | |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 123 | switch (cs->exception_index) { |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 124 | case EXCP_HW_EXCP: |
Richard Henderson | a4bcfc3 | 2020-09-04 11:11:28 -0700 | [diff] [blame] | 125 | if (!(cpu->cfg.pvr_regs[0] & PVR0_USE_EXC_MASK)) { |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 126 | qemu_log_mask(LOG_GUEST_ERROR, |
| 127 | "Exception raised on system without exceptions!\n"); |
| 128 | return; |
| 129 | } |
Edgar E. Iglesias | cedb936 | 2009-09-03 10:25:00 +0200 | [diff] [blame] | 130 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 131 | qemu_log_mask(CPU_LOG_INT, |
| 132 | "INT: HWE at pc=%08x msr=%08x iflags=%x\n", |
| 133 | env->pc, msr, env->iflags); |
Edgar E. Iglesias | cedb936 | 2009-09-03 10:25:00 +0200 | [diff] [blame] | 134 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 135 | /* Exception breaks branch + dslot sequence? */ |
| 136 | set_esr = true; |
| 137 | env->esr &= ~D_FLAG; |
| 138 | if (env->iflags & D_FLAG) { |
| 139 | env->esr |= D_FLAG; |
| 140 | env->btr = env->btarget; |
| 141 | } |
Edgar E. Iglesias | cedb936 | 2009-09-03 10:25:00 +0200 | [diff] [blame] | 142 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 143 | /* Exception in progress. */ |
| 144 | msr |= MSR_EIP; |
| 145 | env->regs[17] = env->pc + 4; |
| 146 | env->pc = cpu->cfg.base_vectors + 0x20; |
| 147 | break; |
Edgar E. Iglesias | cedb936 | 2009-09-03 10:25:00 +0200 | [diff] [blame] | 148 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 149 | case EXCP_MMU: |
| 150 | qemu_log_mask(CPU_LOG_INT, |
| 151 | "INT: MMU at pc=%08x msr=%08x " |
| 152 | "ear=%" PRIx64 " iflags=%x\n", |
| 153 | env->pc, msr, env->ear, env->iflags); |
Edgar E. Iglesias | cedb936 | 2009-09-03 10:25:00 +0200 | [diff] [blame] | 154 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 155 | /* Exception breaks branch + dslot sequence? */ |
| 156 | set_esr = true; |
| 157 | env->esr &= ~D_FLAG; |
| 158 | if (env->iflags & D_FLAG) { |
| 159 | env->esr |= D_FLAG; |
| 160 | env->btr = env->btarget; |
| 161 | /* Reexecute the branch. */ |
| 162 | env->regs[17] = env->pc - (env->iflags & BIMM_FLAG ? 8 : 4); |
| 163 | } else if (env->iflags & IMM_FLAG) { |
| 164 | /* Reexecute the imm. */ |
| 165 | env->regs[17] = env->pc - 4; |
| 166 | } else { |
Richard Henderson | 76e8187 | 2020-08-19 21:33:32 -0700 | [diff] [blame] | 167 | env->regs[17] = env->pc; |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 168 | } |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 169 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 170 | /* Exception in progress. */ |
| 171 | msr |= MSR_EIP; |
| 172 | env->pc = cpu->cfg.base_vectors + 0x20; |
| 173 | break; |
Richard Henderson | e3f8d19 | 2020-08-17 21:01:30 -0700 | [diff] [blame] | 174 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 175 | case EXCP_IRQ: |
| 176 | assert(!(msr & (MSR_EIP | MSR_BIP))); |
| 177 | assert(msr & MSR_IE); |
| 178 | assert(!(env->iflags & (D_FLAG | IMM_FLAG))); |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 179 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 180 | qemu_log_mask(CPU_LOG_INT, |
| 181 | "INT: DEV at pc=%08x msr=%08x iflags=%x\n", |
| 182 | env->pc, msr, env->iflags); |
| 183 | set_esr = false; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 184 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 185 | /* Disable interrupts. */ |
| 186 | msr &= ~MSR_IE; |
| 187 | env->regs[14] = env->pc; |
| 188 | env->pc = cpu->cfg.base_vectors + 0x10; |
| 189 | break; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 190 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 191 | case EXCP_HW_BREAK: |
| 192 | assert(!(env->iflags & (D_FLAG | IMM_FLAG))); |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 193 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 194 | qemu_log_mask(CPU_LOG_INT, |
| 195 | "INT: BRK at pc=%08x msr=%08x iflags=%x\n", |
| 196 | env->pc, msr, env->iflags); |
| 197 | set_esr = false; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 198 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 199 | /* Break in progress. */ |
| 200 | msr |= MSR_BIP; |
| 201 | env->regs[16] = env->pc; |
| 202 | env->pc = cpu->cfg.base_vectors + 0x18; |
| 203 | break; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 204 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 205 | default: |
| 206 | cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); |
| 207 | /* not reached */ |
| 208 | } |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 209 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 210 | /* Save previous mode, disable mmu, disable user-mode. */ |
| 211 | t = (msr & (MSR_VM | MSR_UM)) << 1; |
| 212 | msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); |
| 213 | msr |= t; |
| 214 | mb_cpu_write_msr(env, msr); |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 215 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 216 | env->res_addr = RES_ADDR_NONE; |
| 217 | env->iflags = 0; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 218 | |
Richard Henderson | a9f6145 | 2020-09-02 23:11:00 -0700 | [diff] [blame] | 219 | if (!set_esr) { |
| 220 | qemu_log_mask(CPU_LOG_INT, |
| 221 | " to pc=%08x msr=%08x\n", env->pc, msr); |
| 222 | } else if (env->esr & D_FLAG) { |
| 223 | qemu_log_mask(CPU_LOG_INT, |
| 224 | " to pc=%08x msr=%08x esr=%04x btr=%08x\n", |
| 225 | env->pc, msr, env->esr, env->btr); |
| 226 | } else { |
| 227 | qemu_log_mask(CPU_LOG_INT, |
| 228 | " to pc=%08x msr=%08x esr=%04x\n", |
| 229 | env->pc, msr, env->esr); |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 230 | } |
| 231 | } |
| 232 | |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 233 | hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 234 | { |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 235 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
| 236 | CPUMBState *env = &cpu->env; |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 237 | target_ulong vaddr, paddr = 0; |
Richard Henderson | 8ce97bc | 2020-09-02 23:18:35 -0700 | [diff] [blame] | 238 | MicroBlazeMMULookup lu; |
Edgar E. Iglesias | d10367e | 2018-05-15 23:44:28 +0200 | [diff] [blame] | 239 | int mmu_idx = cpu_mmu_index(env, false); |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 240 | unsigned int hit; |
| 241 | |
Edgar E. Iglesias | d10367e | 2018-05-15 23:44:28 +0200 | [diff] [blame] | 242 | if (mmu_idx != MMU_NOMMU_IDX) { |
Richard Henderson | de73ee1 | 2020-09-04 11:31:57 -0700 | [diff] [blame] | 243 | hit = mmu_translate(cpu, &lu, addr, 0, 0); |
Edgar E. Iglesias | 4acb54b | 2009-05-20 19:37:39 +0200 | [diff] [blame] | 244 | if (hit) { |
| 245 | vaddr = addr & TARGET_PAGE_MASK; |
| 246 | paddr = lu.paddr + vaddr - lu.vaddr; |
| 247 | } else |
| 248 | paddr = 0; /* ???. */ |
| 249 | } else |
| 250 | paddr = addr & TARGET_PAGE_MASK; |
| 251 | |
| 252 | return paddr; |
| 253 | } |
| 254 | #endif |
Richard Henderson | 29cd33d | 2014-09-13 09:45:30 -0700 | [diff] [blame] | 255 | |
| 256 | bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
| 257 | { |
| 258 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
| 259 | CPUMBState *env = &cpu->env; |
| 260 | |
| 261 | if ((interrupt_request & CPU_INTERRUPT_HARD) |
Richard Henderson | 2e5282c | 2020-08-19 21:41:10 -0700 | [diff] [blame] | 262 | && (env->msr & MSR_IE) |
| 263 | && !(env->msr & (MSR_EIP | MSR_BIP)) |
Richard Henderson | 29cd33d | 2014-09-13 09:45:30 -0700 | [diff] [blame] | 264 | && !(env->iflags & (D_FLAG | IMM_FLAG))) { |
| 265 | cs->exception_index = EXCP_IRQ; |
| 266 | mb_cpu_do_interrupt(cs); |
| 267 | return true; |
| 268 | } |
| 269 | return false; |
| 270 | } |
Richard Henderson | ab0c8d0 | 2020-08-20 20:29:01 -0700 | [diff] [blame] | 271 | |
| 272 | void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
| 273 | MMUAccessType access_type, |
| 274 | int mmu_idx, uintptr_t retaddr) |
| 275 | { |
| 276 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
| 277 | uint32_t esr, iflags; |
| 278 | |
| 279 | /* Recover the pc and iflags from the corresponding insn_start. */ |
| 280 | cpu_restore_state(cs, retaddr, true); |
| 281 | iflags = cpu->env.iflags; |
| 282 | |
| 283 | qemu_log_mask(CPU_LOG_INT, |
Richard Henderson | 19f27b6 | 2020-08-25 12:37:12 -0700 | [diff] [blame] | 284 | "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n", |
| 285 | (target_ulong)addr, cpu->env.pc, iflags); |
Richard Henderson | ab0c8d0 | 2020-08-20 20:29:01 -0700 | [diff] [blame] | 286 | |
| 287 | esr = ESR_EC_UNALIGNED_DATA; |
| 288 | if (likely(iflags & ESR_ESS_FLAG)) { |
| 289 | esr |= iflags & ESR_ESS_MASK; |
| 290 | } else { |
| 291 | qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n"); |
| 292 | } |
| 293 | |
| 294 | cpu->env.ear = addr; |
| 295 | cpu->env.esr = esr; |
| 296 | cs->exception_index = EXCP_HW_EXCP; |
| 297 | cpu_loop_exit(cs); |
| 298 | } |