pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1 | /** |
| 2 | * QEMU RTL8139 emulation |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 4 | * Copyright (c) 2006 Igor Kovalenko |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 5 | * |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 23 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 24 | * Modifications: |
| 25 | * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 26 | * |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 27 | * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver |
| 28 | * HW revision ID changes for FreeBSD driver |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 29 | * |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 30 | * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver |
| 31 | * Corrected packet transfer reassembly routine for 8139C+ mode |
| 32 | * Rearranged debugging print statements |
| 33 | * Implemented PCI timer interrupt (disabled by default) |
| 34 | * Implemented Tally Counters, increased VM load/save version |
| 35 | * Implemented IP/TCP/UDP checksum task offloading |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 36 | * |
| 37 | * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading |
| 38 | * Fixed MTU=1500 for produced ethernet frames |
| 39 | * |
| 40 | * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing |
| 41 | * segmentation offloading |
| 42 | * Removed slirp.h dependency |
| 43 | * Added rx/tx buffer reset when enabling rx/tx operation |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 44 | */ |
| 45 | |
pbrook | 87ecb68 | 2007-11-17 17:14:51 +0000 | [diff] [blame] | 46 | #include "hw.h" |
| 47 | #include "pci.h" |
| 48 | #include "qemu-timer.h" |
| 49 | #include "net.h" |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 50 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 51 | /* debug RTL8139 card */ |
| 52 | //#define DEBUG_RTL8139 1 |
| 53 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 54 | #define PCI_FREQUENCY 33000000L |
| 55 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 56 | /* debug RTL8139 card C+ mode only */ |
| 57 | //#define DEBUG_RTL8139CP 1 |
| 58 | |
ths | ccf1d14 | 2007-08-01 13:10:29 +0000 | [diff] [blame] | 59 | /* Calculate CRCs properly on Rx packets */ |
| 60 | #define RTL8139_CALCULATE_RXCRC 1 |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 61 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 62 | /* Uncomment to enable on-board timer interrupts */ |
| 63 | //#define RTL8139_ONBOARD_TIMER 1 |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 64 | |
| 65 | #if defined(RTL8139_CALCULATE_RXCRC) |
| 66 | /* For crc32 */ |
| 67 | #include <zlib.h> |
| 68 | #endif |
| 69 | |
| 70 | #define SET_MASKED(input, mask, curr) \ |
| 71 | ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) |
| 72 | |
| 73 | /* arg % size for size which is a power of 2 */ |
| 74 | #define MOD2(input, size) \ |
| 75 | ( ( input ) & ( size - 1 ) ) |
| 76 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 77 | #if defined (DEBUG_RTL8139) |
| 78 | # define DEBUG_PRINT(x) do { printf x ; } while (0) |
| 79 | #else |
| 80 | # define DEBUG_PRINT(x) |
| 81 | #endif |
| 82 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 83 | /* Symbolic offsets to registers. */ |
| 84 | enum RTL8139_registers { |
| 85 | MAC0 = 0, /* Ethernet hardware address. */ |
| 86 | MAR0 = 8, /* Multicast filter. */ |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 87 | TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ |
| 88 | /* Dump Tally Conter control register(64bit). C+ mode only */ |
| 89 | TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 90 | RxBuf = 0x30, |
| 91 | ChipCmd = 0x37, |
| 92 | RxBufPtr = 0x38, |
| 93 | RxBufAddr = 0x3A, |
| 94 | IntrMask = 0x3C, |
| 95 | IntrStatus = 0x3E, |
| 96 | TxConfig = 0x40, |
| 97 | RxConfig = 0x44, |
| 98 | Timer = 0x48, /* A general-purpose counter. */ |
| 99 | RxMissed = 0x4C, /* 24 bits valid, write clears. */ |
| 100 | Cfg9346 = 0x50, |
| 101 | Config0 = 0x51, |
| 102 | Config1 = 0x52, |
| 103 | FlashReg = 0x54, |
| 104 | MediaStatus = 0x58, |
| 105 | Config3 = 0x59, |
| 106 | Config4 = 0x5A, /* absent on RTL-8139A */ |
| 107 | HltClk = 0x5B, |
| 108 | MultiIntr = 0x5C, |
| 109 | PCIRevisionID = 0x5E, |
| 110 | TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ |
| 111 | BasicModeCtrl = 0x62, |
| 112 | BasicModeStatus = 0x64, |
| 113 | NWayAdvert = 0x66, |
| 114 | NWayLPAR = 0x68, |
| 115 | NWayExpansion = 0x6A, |
| 116 | /* Undocumented registers, but required for proper operation. */ |
| 117 | FIFOTMS = 0x70, /* FIFO Control and test. */ |
| 118 | CSCR = 0x74, /* Chip Status and Configuration Register. */ |
| 119 | PARA78 = 0x78, |
| 120 | PARA7c = 0x7c, /* Magic transceiver parameter register. */ |
| 121 | Config5 = 0xD8, /* absent on RTL-8139A */ |
| 122 | /* C+ mode */ |
| 123 | TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ |
| 124 | RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ |
| 125 | CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ |
| 126 | IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ |
| 127 | RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ |
| 128 | RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ |
| 129 | TxThresh = 0xEC, /* Early Tx threshold */ |
| 130 | }; |
| 131 | |
| 132 | enum ClearBitMasks { |
| 133 | MultiIntrClear = 0xF000, |
| 134 | ChipCmdClear = 0xE2, |
| 135 | Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), |
| 136 | }; |
| 137 | |
| 138 | enum ChipCmdBits { |
| 139 | CmdReset = 0x10, |
| 140 | CmdRxEnb = 0x08, |
| 141 | CmdTxEnb = 0x04, |
| 142 | RxBufEmpty = 0x01, |
| 143 | }; |
| 144 | |
| 145 | /* C+ mode */ |
| 146 | enum CplusCmdBits { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 147 | CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ |
| 148 | CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ |
| 149 | CPlusRxEnb = 0x0002, |
| 150 | CPlusTxEnb = 0x0001, |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 151 | }; |
| 152 | |
| 153 | /* Interrupt register bits, using my own meaningful names. */ |
| 154 | enum IntrStatusBits { |
| 155 | PCIErr = 0x8000, |
| 156 | PCSTimeout = 0x4000, |
| 157 | RxFIFOOver = 0x40, |
| 158 | RxUnderrun = 0x20, |
| 159 | RxOverflow = 0x10, |
| 160 | TxErr = 0x08, |
| 161 | TxOK = 0x04, |
| 162 | RxErr = 0x02, |
| 163 | RxOK = 0x01, |
| 164 | |
| 165 | RxAckBits = RxFIFOOver | RxOverflow | RxOK, |
| 166 | }; |
| 167 | |
| 168 | enum TxStatusBits { |
| 169 | TxHostOwns = 0x2000, |
| 170 | TxUnderrun = 0x4000, |
| 171 | TxStatOK = 0x8000, |
| 172 | TxOutOfWindow = 0x20000000, |
| 173 | TxAborted = 0x40000000, |
| 174 | TxCarrierLost = 0x80000000, |
| 175 | }; |
| 176 | enum RxStatusBits { |
| 177 | RxMulticast = 0x8000, |
| 178 | RxPhysical = 0x4000, |
| 179 | RxBroadcast = 0x2000, |
| 180 | RxBadSymbol = 0x0020, |
| 181 | RxRunt = 0x0010, |
| 182 | RxTooLong = 0x0008, |
| 183 | RxCRCErr = 0x0004, |
| 184 | RxBadAlign = 0x0002, |
| 185 | RxStatusOK = 0x0001, |
| 186 | }; |
| 187 | |
| 188 | /* Bits in RxConfig. */ |
| 189 | enum rx_mode_bits { |
| 190 | AcceptErr = 0x20, |
| 191 | AcceptRunt = 0x10, |
| 192 | AcceptBroadcast = 0x08, |
| 193 | AcceptMulticast = 0x04, |
| 194 | AcceptMyPhys = 0x02, |
| 195 | AcceptAllPhys = 0x01, |
| 196 | }; |
| 197 | |
| 198 | /* Bits in TxConfig. */ |
| 199 | enum tx_config_bits { |
| 200 | |
| 201 | /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ |
| 202 | TxIFGShift = 24, |
| 203 | TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ |
| 204 | TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ |
| 205 | TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ |
| 206 | TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ |
| 207 | |
| 208 | TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ |
| 209 | TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ |
| 210 | TxClearAbt = (1 << 0), /* Clear abort (WO) */ |
| 211 | TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ |
| 212 | TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ |
| 213 | |
| 214 | TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ |
| 215 | }; |
| 216 | |
| 217 | |
| 218 | /* Transmit Status of All Descriptors (TSAD) Register */ |
| 219 | enum TSAD_bits { |
| 220 | TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 |
| 221 | TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 |
| 222 | TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 |
| 223 | TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 |
| 224 | TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 |
| 225 | TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 |
| 226 | TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 |
| 227 | TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 |
| 228 | TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 |
| 229 | TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 |
| 230 | TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 |
| 231 | TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 |
| 232 | TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 |
| 233 | TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 |
| 234 | TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 |
| 235 | TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 |
| 236 | }; |
| 237 | |
| 238 | |
| 239 | /* Bits in Config1 */ |
| 240 | enum Config1Bits { |
| 241 | Cfg1_PM_Enable = 0x01, |
| 242 | Cfg1_VPD_Enable = 0x02, |
| 243 | Cfg1_PIO = 0x04, |
| 244 | Cfg1_MMIO = 0x08, |
| 245 | LWAKE = 0x10, /* not on 8139, 8139A */ |
| 246 | Cfg1_Driver_Load = 0x20, |
| 247 | Cfg1_LED0 = 0x40, |
| 248 | Cfg1_LED1 = 0x80, |
| 249 | SLEEP = (1 << 1), /* only on 8139, 8139A */ |
| 250 | PWRDN = (1 << 0), /* only on 8139, 8139A */ |
| 251 | }; |
| 252 | |
| 253 | /* Bits in Config3 */ |
| 254 | enum Config3Bits { |
| 255 | Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ |
| 256 | Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ |
| 257 | Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ |
| 258 | Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ |
| 259 | Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ |
| 260 | Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ |
| 261 | Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ |
| 262 | Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ |
| 263 | }; |
| 264 | |
| 265 | /* Bits in Config4 */ |
| 266 | enum Config4Bits { |
| 267 | LWPTN = (1 << 2), /* not on 8139, 8139A */ |
| 268 | }; |
| 269 | |
| 270 | /* Bits in Config5 */ |
| 271 | enum Config5Bits { |
| 272 | Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ |
| 273 | Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ |
| 274 | Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ |
| 275 | Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ |
| 276 | Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ |
| 277 | Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ |
| 278 | Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ |
| 279 | }; |
| 280 | |
| 281 | enum RxConfigBits { |
| 282 | /* rx fifo threshold */ |
| 283 | RxCfgFIFOShift = 13, |
| 284 | RxCfgFIFONone = (7 << RxCfgFIFOShift), |
| 285 | |
| 286 | /* Max DMA burst */ |
| 287 | RxCfgDMAShift = 8, |
| 288 | RxCfgDMAUnlimited = (7 << RxCfgDMAShift), |
| 289 | |
| 290 | /* rx ring buffer length */ |
| 291 | RxCfgRcv8K = 0, |
| 292 | RxCfgRcv16K = (1 << 11), |
| 293 | RxCfgRcv32K = (1 << 12), |
| 294 | RxCfgRcv64K = (1 << 11) | (1 << 12), |
| 295 | |
| 296 | /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ |
| 297 | RxNoWrap = (1 << 7), |
| 298 | }; |
| 299 | |
| 300 | /* Twister tuning parameters from RealTek. |
| 301 | Completely undocumented, but required to tune bad links on some boards. */ |
| 302 | /* |
| 303 | enum CSCRBits { |
| 304 | CSCR_LinkOKBit = 0x0400, |
| 305 | CSCR_LinkChangeBit = 0x0800, |
| 306 | CSCR_LinkStatusBits = 0x0f000, |
| 307 | CSCR_LinkDownOffCmd = 0x003c0, |
| 308 | CSCR_LinkDownCmd = 0x0f3c0, |
| 309 | */ |
| 310 | enum CSCRBits { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 311 | CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 312 | CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ |
| 313 | CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ |
| 314 | CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 315 | CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 316 | CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ |
| 317 | CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ |
| 318 | CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ |
| 319 | CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ |
| 320 | }; |
| 321 | |
| 322 | enum Cfg9346Bits { |
| 323 | Cfg9346_Lock = 0x00, |
| 324 | Cfg9346_Unlock = 0xC0, |
| 325 | }; |
| 326 | |
| 327 | typedef enum { |
| 328 | CH_8139 = 0, |
| 329 | CH_8139_K, |
| 330 | CH_8139A, |
| 331 | CH_8139A_G, |
| 332 | CH_8139B, |
| 333 | CH_8130, |
| 334 | CH_8139C, |
| 335 | CH_8100, |
| 336 | CH_8100B_8139D, |
| 337 | CH_8101, |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 338 | } chip_t; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 339 | |
| 340 | enum chip_flags { |
| 341 | HasHltClk = (1 << 0), |
| 342 | HasLWake = (1 << 1), |
| 343 | }; |
| 344 | |
| 345 | #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ |
| 346 | (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) |
| 347 | #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) |
| 348 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 349 | #define RTL8139_PCI_REVID_8139 0x10 |
| 350 | #define RTL8139_PCI_REVID_8139CPLUS 0x20 |
| 351 | |
| 352 | #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS |
| 353 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 354 | /* Size is 64 * 16bit words */ |
| 355 | #define EEPROM_9346_ADDR_BITS 6 |
| 356 | #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) |
| 357 | #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) |
| 358 | |
| 359 | enum Chip9346Operation |
| 360 | { |
| 361 | Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ |
| 362 | Chip9346_op_read = 0x80, /* 10 AAAAAA */ |
| 363 | Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ |
| 364 | Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ |
| 365 | Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ |
| 366 | Chip9346_op_write_all = 0x10, /* 00 01zzzz */ |
| 367 | Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ |
| 368 | }; |
| 369 | |
| 370 | enum Chip9346Mode |
| 371 | { |
| 372 | Chip9346_none = 0, |
| 373 | Chip9346_enter_command_mode, |
| 374 | Chip9346_read_command, |
| 375 | Chip9346_data_read, /* from output register */ |
| 376 | Chip9346_data_write, /* to input register, then to contents at specified address */ |
| 377 | Chip9346_data_write_all, /* to input register, then filling contents */ |
| 378 | }; |
| 379 | |
| 380 | typedef struct EEprom9346 |
| 381 | { |
| 382 | uint16_t contents[EEPROM_9346_SIZE]; |
| 383 | int mode; |
| 384 | uint32_t tick; |
| 385 | uint8_t address; |
| 386 | uint16_t input; |
| 387 | uint16_t output; |
| 388 | |
| 389 | uint8_t eecs; |
| 390 | uint8_t eesk; |
| 391 | uint8_t eedi; |
| 392 | uint8_t eedo; |
| 393 | } EEprom9346; |
| 394 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 395 | typedef struct RTL8139TallyCounters |
| 396 | { |
| 397 | /* Tally counters */ |
| 398 | uint64_t TxOk; |
| 399 | uint64_t RxOk; |
| 400 | uint64_t TxERR; |
| 401 | uint32_t RxERR; |
| 402 | uint16_t MissPkt; |
| 403 | uint16_t FAE; |
| 404 | uint32_t Tx1Col; |
| 405 | uint32_t TxMCol; |
| 406 | uint64_t RxOkPhy; |
| 407 | uint64_t RxOkBrd; |
| 408 | uint32_t RxOkMul; |
| 409 | uint16_t TxAbt; |
| 410 | uint16_t TxUndrn; |
| 411 | } RTL8139TallyCounters; |
| 412 | |
| 413 | /* Clears all tally counters */ |
| 414 | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); |
| 415 | |
| 416 | /* Writes tally counters to specified physical memory address */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 417 | static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 418 | |
| 419 | /* Loads values of tally counters from VM state file */ |
| 420 | static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters); |
| 421 | |
| 422 | /* Saves values of tally counters to VM state file */ |
| 423 | static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters); |
| 424 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 425 | typedef struct RTL8139State { |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 426 | PCIDevice dev; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 427 | uint8_t phys[8]; /* mac address */ |
| 428 | uint8_t mult[8]; /* multicast mask array */ |
| 429 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 430 | uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 431 | uint32_t TxAddr[4]; /* TxAddr0 */ |
| 432 | uint32_t RxBuf; /* Receive buffer */ |
| 433 | uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ |
| 434 | uint32_t RxBufPtr; |
| 435 | uint32_t RxBufAddr; |
| 436 | |
| 437 | uint16_t IntrStatus; |
| 438 | uint16_t IntrMask; |
| 439 | |
| 440 | uint32_t TxConfig; |
| 441 | uint32_t RxConfig; |
| 442 | uint32_t RxMissed; |
| 443 | |
| 444 | uint16_t CSCR; |
| 445 | |
| 446 | uint8_t Cfg9346; |
| 447 | uint8_t Config0; |
| 448 | uint8_t Config1; |
| 449 | uint8_t Config3; |
| 450 | uint8_t Config4; |
| 451 | uint8_t Config5; |
| 452 | |
| 453 | uint8_t clock_enabled; |
| 454 | uint8_t bChipCmdState; |
| 455 | |
| 456 | uint16_t MultiIntr; |
| 457 | |
| 458 | uint16_t BasicModeCtrl; |
| 459 | uint16_t BasicModeStatus; |
| 460 | uint16_t NWayAdvert; |
| 461 | uint16_t NWayLPAR; |
| 462 | uint16_t NWayExpansion; |
| 463 | |
| 464 | uint16_t CpCmd; |
| 465 | uint8_t TxThresh; |
| 466 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 467 | VLANClientState *vc; |
| 468 | uint8_t macaddr[6]; |
| 469 | int rtl8139_mmio_io_addr; |
| 470 | |
| 471 | /* C ring mode */ |
| 472 | uint32_t currTxDesc; |
| 473 | |
| 474 | /* C+ mode */ |
aliguori | 2c3891a | 2009-01-13 15:20:14 +0000 | [diff] [blame] | 475 | uint32_t cplus_enabled; |
| 476 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 477 | uint32_t currCPlusRxDesc; |
| 478 | uint32_t currCPlusTxDesc; |
| 479 | |
| 480 | uint32_t RxRingAddrLO; |
| 481 | uint32_t RxRingAddrHI; |
| 482 | |
| 483 | EEprom9346 eeprom; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 484 | |
| 485 | uint32_t TCTR; |
| 486 | uint32_t TimerInt; |
| 487 | int64_t TCTR_base; |
| 488 | |
| 489 | /* Tally counters */ |
| 490 | RTL8139TallyCounters tally_counters; |
| 491 | |
| 492 | /* Non-persistent data */ |
| 493 | uint8_t *cplus_txbuffer; |
| 494 | int cplus_txbuffer_len; |
| 495 | int cplus_txbuffer_offset; |
| 496 | |
| 497 | /* PCI interrupt timer */ |
| 498 | QEMUTimer *timer; |
| 499 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 500 | } RTL8139State; |
| 501 | |
pbrook | 9596ebb | 2007-11-18 01:44:38 +0000 | [diff] [blame] | 502 | static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 503 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 504 | DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 505 | |
| 506 | switch (command & Chip9346_op_mask) |
| 507 | { |
| 508 | case Chip9346_op_read: |
| 509 | { |
| 510 | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
| 511 | eeprom->output = eeprom->contents[eeprom->address]; |
| 512 | eeprom->eedo = 0; |
| 513 | eeprom->tick = 0; |
| 514 | eeprom->mode = Chip9346_data_read; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 515 | DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n", |
| 516 | eeprom->address, eeprom->output)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 517 | } |
| 518 | break; |
| 519 | |
| 520 | case Chip9346_op_write: |
| 521 | { |
| 522 | eeprom->address = command & EEPROM_9346_ADDR_MASK; |
| 523 | eeprom->input = 0; |
| 524 | eeprom->tick = 0; |
| 525 | eeprom->mode = Chip9346_none; /* Chip9346_data_write */ |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 526 | DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n", |
| 527 | eeprom->address)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 528 | } |
| 529 | break; |
| 530 | default: |
| 531 | eeprom->mode = Chip9346_none; |
| 532 | switch (command & Chip9346_op_ext_mask) |
| 533 | { |
| 534 | case Chip9346_op_write_enable: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 535 | DEBUG_PRINT(("RTL8139: eeprom write enabled\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 536 | break; |
| 537 | case Chip9346_op_write_all: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 538 | DEBUG_PRINT(("RTL8139: eeprom begin write all\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 539 | break; |
| 540 | case Chip9346_op_write_disable: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 541 | DEBUG_PRINT(("RTL8139: eeprom write disabled\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 542 | break; |
| 543 | } |
| 544 | break; |
| 545 | } |
| 546 | } |
| 547 | |
pbrook | 9596ebb | 2007-11-18 01:44:38 +0000 | [diff] [blame] | 548 | static void prom9346_shift_clock(EEprom9346 *eeprom) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 549 | { |
| 550 | int bit = eeprom->eedi?1:0; |
| 551 | |
| 552 | ++ eeprom->tick; |
| 553 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 554 | DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 555 | |
| 556 | switch (eeprom->mode) |
| 557 | { |
| 558 | case Chip9346_enter_command_mode: |
| 559 | if (bit) |
| 560 | { |
| 561 | eeprom->mode = Chip9346_read_command; |
| 562 | eeprom->tick = 0; |
| 563 | eeprom->input = 0; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 564 | DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 565 | } |
| 566 | break; |
| 567 | |
| 568 | case Chip9346_read_command: |
| 569 | eeprom->input = (eeprom->input << 1) | (bit & 1); |
| 570 | if (eeprom->tick == 8) |
| 571 | { |
| 572 | prom9346_decode_command(eeprom, eeprom->input & 0xff); |
| 573 | } |
| 574 | break; |
| 575 | |
| 576 | case Chip9346_data_read: |
| 577 | eeprom->eedo = (eeprom->output & 0x8000)?1:0; |
| 578 | eeprom->output <<= 1; |
| 579 | if (eeprom->tick == 16) |
| 580 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 581 | #if 1 |
| 582 | // the FreeBSD drivers (rl and re) don't explicitly toggle |
| 583 | // CS between reads (or does setting Cfg9346 to 0 count too?), |
| 584 | // so we need to enter wait-for-command state here |
| 585 | eeprom->mode = Chip9346_enter_command_mode; |
| 586 | eeprom->input = 0; |
| 587 | eeprom->tick = 0; |
| 588 | |
| 589 | DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n")); |
| 590 | #else |
| 591 | // original behaviour |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 592 | ++eeprom->address; |
| 593 | eeprom->address &= EEPROM_9346_ADDR_MASK; |
| 594 | eeprom->output = eeprom->contents[eeprom->address]; |
| 595 | eeprom->tick = 0; |
| 596 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 597 | DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n", |
| 598 | eeprom->address, eeprom->output)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 599 | #endif |
| 600 | } |
| 601 | break; |
| 602 | |
| 603 | case Chip9346_data_write: |
| 604 | eeprom->input = (eeprom->input << 1) | (bit & 1); |
| 605 | if (eeprom->tick == 16) |
| 606 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 607 | DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n", |
| 608 | eeprom->address, eeprom->input)); |
| 609 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 610 | eeprom->contents[eeprom->address] = eeprom->input; |
| 611 | eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ |
| 612 | eeprom->tick = 0; |
| 613 | eeprom->input = 0; |
| 614 | } |
| 615 | break; |
| 616 | |
| 617 | case Chip9346_data_write_all: |
| 618 | eeprom->input = (eeprom->input << 1) | (bit & 1); |
| 619 | if (eeprom->tick == 16) |
| 620 | { |
| 621 | int i; |
| 622 | for (i = 0; i < EEPROM_9346_SIZE; i++) |
| 623 | { |
| 624 | eeprom->contents[i] = eeprom->input; |
| 625 | } |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 626 | DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n", |
| 627 | eeprom->input)); |
| 628 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 629 | eeprom->mode = Chip9346_enter_command_mode; |
| 630 | eeprom->tick = 0; |
| 631 | eeprom->input = 0; |
| 632 | } |
| 633 | break; |
| 634 | |
| 635 | default: |
| 636 | break; |
| 637 | } |
| 638 | } |
| 639 | |
pbrook | 9596ebb | 2007-11-18 01:44:38 +0000 | [diff] [blame] | 640 | static int prom9346_get_wire(RTL8139State *s) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 641 | { |
| 642 | EEprom9346 *eeprom = &s->eeprom; |
| 643 | if (!eeprom->eecs) |
| 644 | return 0; |
| 645 | |
| 646 | return eeprom->eedo; |
| 647 | } |
| 648 | |
pbrook | 9596ebb | 2007-11-18 01:44:38 +0000 | [diff] [blame] | 649 | /* FIXME: This should be merged into/replaced by eeprom93xx.c. */ |
| 650 | static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 651 | { |
| 652 | EEprom9346 *eeprom = &s->eeprom; |
| 653 | uint8_t old_eecs = eeprom->eecs; |
| 654 | uint8_t old_eesk = eeprom->eesk; |
| 655 | |
| 656 | eeprom->eecs = eecs; |
| 657 | eeprom->eesk = eesk; |
| 658 | eeprom->eedi = eedi; |
| 659 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 660 | DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", |
| 661 | eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 662 | |
| 663 | if (!old_eecs && eecs) |
| 664 | { |
| 665 | /* Synchronize start */ |
| 666 | eeprom->tick = 0; |
| 667 | eeprom->input = 0; |
| 668 | eeprom->output = 0; |
| 669 | eeprom->mode = Chip9346_enter_command_mode; |
| 670 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 671 | DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 672 | } |
| 673 | |
| 674 | if (!eecs) |
| 675 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 676 | DEBUG_PRINT(("=== eeprom: end access\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 677 | return; |
| 678 | } |
| 679 | |
| 680 | if (!old_eesk && eesk) |
| 681 | { |
| 682 | /* SK front rules */ |
| 683 | prom9346_shift_clock(eeprom); |
| 684 | } |
| 685 | } |
| 686 | |
| 687 | static void rtl8139_update_irq(RTL8139State *s) |
| 688 | { |
| 689 | int isr; |
| 690 | isr = (s->IntrStatus & s->IntrMask) & 0xffff; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 691 | |
pbrook | 80a34d6 | 2007-04-07 01:41:49 +0000 | [diff] [blame] | 692 | DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n", |
| 693 | isr ? 1 : 0, s->IntrStatus, s->IntrMask)); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 694 | |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 695 | qemu_set_irq(s->dev.irq[0], (isr != 0)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 696 | } |
| 697 | |
| 698 | #define POLYNOMIAL 0x04c11db6 |
| 699 | |
| 700 | /* From FreeBSD */ |
| 701 | /* XXX: optimize */ |
| 702 | static int compute_mcast_idx(const uint8_t *ep) |
| 703 | { |
| 704 | uint32_t crc; |
| 705 | int carry, i, j; |
| 706 | uint8_t b; |
| 707 | |
| 708 | crc = 0xffffffff; |
| 709 | for (i = 0; i < 6; i++) { |
| 710 | b = *ep++; |
| 711 | for (j = 0; j < 8; j++) { |
| 712 | carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
| 713 | crc <<= 1; |
| 714 | b >>= 1; |
| 715 | if (carry) |
| 716 | crc = ((crc ^ POLYNOMIAL) | carry); |
| 717 | } |
| 718 | } |
| 719 | return (crc >> 26); |
| 720 | } |
| 721 | |
| 722 | static int rtl8139_RxWrap(RTL8139State *s) |
| 723 | { |
| 724 | /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ |
| 725 | return (s->RxConfig & (1 << 7)); |
| 726 | } |
| 727 | |
| 728 | static int rtl8139_receiver_enabled(RTL8139State *s) |
| 729 | { |
| 730 | return s->bChipCmdState & CmdRxEnb; |
| 731 | } |
| 732 | |
| 733 | static int rtl8139_transmitter_enabled(RTL8139State *s) |
| 734 | { |
| 735 | return s->bChipCmdState & CmdTxEnb; |
| 736 | } |
| 737 | |
| 738 | static int rtl8139_cp_receiver_enabled(RTL8139State *s) |
| 739 | { |
| 740 | return s->CpCmd & CPlusRxEnb; |
| 741 | } |
| 742 | |
| 743 | static int rtl8139_cp_transmitter_enabled(RTL8139State *s) |
| 744 | { |
| 745 | return s->CpCmd & CPlusTxEnb; |
| 746 | } |
| 747 | |
| 748 | static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) |
| 749 | { |
| 750 | if (s->RxBufAddr + size > s->RxBufferSize) |
| 751 | { |
| 752 | int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); |
| 753 | |
| 754 | /* write packet data */ |
ths | ccf1d14 | 2007-08-01 13:10:29 +0000 | [diff] [blame] | 755 | if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 756 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 757 | DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 758 | |
| 759 | if (size > wrapped) |
| 760 | { |
| 761 | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
| 762 | buf, size-wrapped ); |
| 763 | } |
| 764 | |
| 765 | /* reset buffer pointer */ |
| 766 | s->RxBufAddr = 0; |
| 767 | |
| 768 | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, |
| 769 | buf + (size-wrapped), wrapped ); |
| 770 | |
| 771 | s->RxBufAddr = wrapped; |
| 772 | |
| 773 | return; |
| 774 | } |
| 775 | } |
| 776 | |
| 777 | /* non-wrapping path or overwrapping enabled */ |
| 778 | cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size ); |
| 779 | |
| 780 | s->RxBufAddr += size; |
| 781 | } |
| 782 | |
| 783 | #define MIN_BUF_SIZE 60 |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 784 | static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 785 | { |
| 786 | #if TARGET_PHYS_ADDR_BITS > 32 |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 787 | return low | ((target_phys_addr_t)high << 32); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 788 | #else |
| 789 | return low; |
| 790 | #endif |
| 791 | } |
| 792 | |
Mark McLoughlin | e3f5ec2 | 2009-05-18 13:33:03 +0100 | [diff] [blame] | 793 | static int rtl8139_can_receive(VLANClientState *vc) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 794 | { |
Mark McLoughlin | e3f5ec2 | 2009-05-18 13:33:03 +0100 | [diff] [blame] | 795 | RTL8139State *s = vc->opaque; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 796 | int avail; |
| 797 | |
ths | aa1f17c | 2007-07-11 22:48:58 +0000 | [diff] [blame] | 798 | /* Receive (drop) packets if card is disabled. */ |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 799 | if (!s->clock_enabled) |
| 800 | return 1; |
| 801 | if (!rtl8139_receiver_enabled(s)) |
| 802 | return 1; |
| 803 | |
| 804 | if (rtl8139_cp_receiver_enabled(s)) { |
| 805 | /* ??? Flow control not implemented in c+ mode. |
| 806 | This is a hack to work around slirp deficiencies anyway. */ |
| 807 | return 1; |
| 808 | } else { |
| 809 | avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, |
| 810 | s->RxBufferSize); |
| 811 | return (avail == 0 || avail >= 1514); |
| 812 | } |
| 813 | } |
| 814 | |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 815 | static ssize_t rtl8139_do_receive(VLANClientState *vc, const uint8_t *buf, size_t size_, int do_interrupt) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 816 | { |
Mark McLoughlin | e3f5ec2 | 2009-05-18 13:33:03 +0100 | [diff] [blame] | 817 | RTL8139State *s = vc->opaque; |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 818 | int size = size_; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 819 | |
| 820 | uint32_t packet_header = 0; |
| 821 | |
| 822 | uint8_t buf1[60]; |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 823 | static const uint8_t broadcast_macaddr[6] = |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 824 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
| 825 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 826 | DEBUG_PRINT((">>> RTL8139: received len=%d\n", size)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 827 | |
| 828 | /* test if board clock is stopped */ |
| 829 | if (!s->clock_enabled) |
| 830 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 831 | DEBUG_PRINT(("RTL8139: stopped ==========================\n")); |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 832 | return -1; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 833 | } |
| 834 | |
| 835 | /* first check if receiver is enabled */ |
| 836 | |
| 837 | if (!rtl8139_receiver_enabled(s)) |
| 838 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 839 | DEBUG_PRINT(("RTL8139: receiver disabled ================\n")); |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 840 | return -1; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 841 | } |
| 842 | |
| 843 | /* XXX: check this */ |
| 844 | if (s->RxConfig & AcceptAllPhys) { |
| 845 | /* promiscuous: receive all */ |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 846 | DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 847 | |
| 848 | } else { |
| 849 | if (!memcmp(buf, broadcast_macaddr, 6)) { |
| 850 | /* broadcast address */ |
| 851 | if (!(s->RxConfig & AcceptBroadcast)) |
| 852 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 853 | DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n")); |
| 854 | |
| 855 | /* update tally counter */ |
| 856 | ++s->tally_counters.RxERR; |
| 857 | |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 858 | return size; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 859 | } |
| 860 | |
| 861 | packet_header |= RxBroadcast; |
| 862 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 863 | DEBUG_PRINT((">>> RTL8139: broadcast packet received\n")); |
| 864 | |
| 865 | /* update tally counter */ |
| 866 | ++s->tally_counters.RxOkBrd; |
| 867 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 868 | } else if (buf[0] & 0x01) { |
| 869 | /* multicast */ |
| 870 | if (!(s->RxConfig & AcceptMulticast)) |
| 871 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 872 | DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n")); |
| 873 | |
| 874 | /* update tally counter */ |
| 875 | ++s->tally_counters.RxERR; |
| 876 | |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 877 | return size; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 878 | } |
| 879 | |
| 880 | int mcast_idx = compute_mcast_idx(buf); |
| 881 | |
| 882 | if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
| 883 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 884 | DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n")); |
| 885 | |
| 886 | /* update tally counter */ |
| 887 | ++s->tally_counters.RxERR; |
| 888 | |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 889 | return size; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 890 | } |
| 891 | |
| 892 | packet_header |= RxMulticast; |
| 893 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 894 | DEBUG_PRINT((">>> RTL8139: multicast packet received\n")); |
| 895 | |
| 896 | /* update tally counter */ |
| 897 | ++s->tally_counters.RxOkMul; |
| 898 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 899 | } else if (s->phys[0] == buf[0] && |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 900 | s->phys[1] == buf[1] && |
| 901 | s->phys[2] == buf[2] && |
| 902 | s->phys[3] == buf[3] && |
| 903 | s->phys[4] == buf[4] && |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 904 | s->phys[5] == buf[5]) { |
| 905 | /* match */ |
| 906 | if (!(s->RxConfig & AcceptMyPhys)) |
| 907 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 908 | DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n")); |
| 909 | |
| 910 | /* update tally counter */ |
| 911 | ++s->tally_counters.RxERR; |
| 912 | |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 913 | return size; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 914 | } |
| 915 | |
| 916 | packet_header |= RxPhysical; |
| 917 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 918 | DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n")); |
| 919 | |
| 920 | /* update tally counter */ |
| 921 | ++s->tally_counters.RxOkPhy; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 922 | |
| 923 | } else { |
| 924 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 925 | DEBUG_PRINT((">>> RTL8139: unknown packet\n")); |
| 926 | |
| 927 | /* update tally counter */ |
| 928 | ++s->tally_counters.RxERR; |
| 929 | |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 930 | return size; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 931 | } |
| 932 | } |
| 933 | |
| 934 | /* if too small buffer, then expand it */ |
| 935 | if (size < MIN_BUF_SIZE) { |
| 936 | memcpy(buf1, buf, size); |
| 937 | memset(buf1 + size, 0, MIN_BUF_SIZE - size); |
| 938 | buf = buf1; |
| 939 | size = MIN_BUF_SIZE; |
| 940 | } |
| 941 | |
| 942 | if (rtl8139_cp_receiver_enabled(s)) |
| 943 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 944 | DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 945 | |
| 946 | /* begin C+ receiver mode */ |
| 947 | |
| 948 | /* w0 ownership flag */ |
| 949 | #define CP_RX_OWN (1<<31) |
| 950 | /* w0 end of ring flag */ |
| 951 | #define CP_RX_EOR (1<<30) |
| 952 | /* w0 bits 0...12 : buffer size */ |
| 953 | #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) |
| 954 | /* w1 tag available flag */ |
| 955 | #define CP_RX_TAVA (1<<16) |
| 956 | /* w1 bits 0...15 : VLAN tag */ |
| 957 | #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) |
| 958 | /* w2 low 32bit of Rx buffer ptr */ |
| 959 | /* w3 high 32bit of Rx buffer ptr */ |
| 960 | |
| 961 | int descriptor = s->currCPlusRxDesc; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 962 | target_phys_addr_t cplus_rx_ring_desc; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 963 | |
| 964 | cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); |
| 965 | cplus_rx_ring_desc += 16 * descriptor; |
| 966 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 967 | DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n", |
| 968 | descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 969 | |
| 970 | uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; |
| 971 | |
| 972 | cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4); |
| 973 | rxdw0 = le32_to_cpu(val); |
| 974 | cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
| 975 | rxdw1 = le32_to_cpu(val); |
| 976 | cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4); |
| 977 | rxbufLO = le32_to_cpu(val); |
| 978 | cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4); |
| 979 | rxbufHI = le32_to_cpu(val); |
| 980 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 981 | DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 982 | descriptor, |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 983 | rxdw0, rxdw1, rxbufLO, rxbufHI)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 984 | |
| 985 | if (!(rxdw0 & CP_RX_OWN)) |
| 986 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 987 | DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor)); |
| 988 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 989 | s->IntrStatus |= RxOverflow; |
| 990 | ++s->RxMissed; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 991 | |
| 992 | /* update tally counter */ |
| 993 | ++s->tally_counters.RxERR; |
| 994 | ++s->tally_counters.MissPkt; |
| 995 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 996 | rtl8139_update_irq(s); |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 997 | return size_; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 998 | } |
| 999 | |
| 1000 | uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; |
| 1001 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1002 | /* TODO: scatter the packet over available receive ring descriptors space */ |
| 1003 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1004 | if (size+4 > rx_space) |
| 1005 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1006 | DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n", |
| 1007 | descriptor, rx_space, size)); |
| 1008 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1009 | s->IntrStatus |= RxOverflow; |
| 1010 | ++s->RxMissed; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1011 | |
| 1012 | /* update tally counter */ |
| 1013 | ++s->tally_counters.RxERR; |
| 1014 | ++s->tally_counters.MissPkt; |
| 1015 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1016 | rtl8139_update_irq(s); |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 1017 | return size_; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1018 | } |
| 1019 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1020 | target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1021 | |
| 1022 | /* receive/copy to target memory */ |
| 1023 | cpu_physical_memory_write( rx_addr, buf, size ); |
| 1024 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1025 | if (s->CpCmd & CPlusRxChkSum) |
| 1026 | { |
| 1027 | /* do some packet checksumming */ |
| 1028 | } |
| 1029 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1030 | /* write checksum */ |
| 1031 | #if defined (RTL8139_CALCULATE_RXCRC) |
ths | ccf1d14 | 2007-08-01 13:10:29 +0000 | [diff] [blame] | 1032 | val = cpu_to_le32(crc32(0, buf, size)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1033 | #else |
| 1034 | val = 0; |
| 1035 | #endif |
| 1036 | cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4); |
| 1037 | |
| 1038 | /* first segment of received packet flag */ |
| 1039 | #define CP_RX_STATUS_FS (1<<29) |
| 1040 | /* last segment of received packet flag */ |
| 1041 | #define CP_RX_STATUS_LS (1<<28) |
| 1042 | /* multicast packet flag */ |
| 1043 | #define CP_RX_STATUS_MAR (1<<26) |
| 1044 | /* physical-matching packet flag */ |
| 1045 | #define CP_RX_STATUS_PAM (1<<25) |
| 1046 | /* broadcast packet flag */ |
| 1047 | #define CP_RX_STATUS_BAR (1<<24) |
| 1048 | /* runt packet flag */ |
| 1049 | #define CP_RX_STATUS_RUNT (1<<19) |
| 1050 | /* crc error flag */ |
| 1051 | #define CP_RX_STATUS_CRC (1<<18) |
| 1052 | /* IP checksum error flag */ |
| 1053 | #define CP_RX_STATUS_IPF (1<<15) |
| 1054 | /* UDP checksum error flag */ |
| 1055 | #define CP_RX_STATUS_UDPF (1<<14) |
| 1056 | /* TCP checksum error flag */ |
| 1057 | #define CP_RX_STATUS_TCPF (1<<13) |
| 1058 | |
| 1059 | /* transfer ownership to target */ |
| 1060 | rxdw0 &= ~CP_RX_OWN; |
| 1061 | |
| 1062 | /* set first segment bit */ |
| 1063 | rxdw0 |= CP_RX_STATUS_FS; |
| 1064 | |
| 1065 | /* set last segment bit */ |
| 1066 | rxdw0 |= CP_RX_STATUS_LS; |
| 1067 | |
| 1068 | /* set received packet type flags */ |
| 1069 | if (packet_header & RxBroadcast) |
| 1070 | rxdw0 |= CP_RX_STATUS_BAR; |
| 1071 | if (packet_header & RxMulticast) |
| 1072 | rxdw0 |= CP_RX_STATUS_MAR; |
| 1073 | if (packet_header & RxPhysical) |
| 1074 | rxdw0 |= CP_RX_STATUS_PAM; |
| 1075 | |
| 1076 | /* set received size */ |
| 1077 | rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; |
| 1078 | rxdw0 |= (size+4); |
| 1079 | |
| 1080 | /* reset VLAN tag flag */ |
| 1081 | rxdw1 &= ~CP_RX_TAVA; |
| 1082 | |
| 1083 | /* update ring data */ |
| 1084 | val = cpu_to_le32(rxdw0); |
| 1085 | cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4); |
| 1086 | val = cpu_to_le32(rxdw1); |
| 1087 | cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4); |
| 1088 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1089 | /* update tally counter */ |
| 1090 | ++s->tally_counters.RxOk; |
| 1091 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1092 | /* seek to next Rx descriptor */ |
| 1093 | if (rxdw0 & CP_RX_EOR) |
| 1094 | { |
| 1095 | s->currCPlusRxDesc = 0; |
| 1096 | } |
| 1097 | else |
| 1098 | { |
| 1099 | ++s->currCPlusRxDesc; |
| 1100 | } |
| 1101 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1102 | DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1103 | |
| 1104 | } |
| 1105 | else |
| 1106 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1107 | DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n")); |
| 1108 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1109 | /* begin ring receiver mode */ |
| 1110 | int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); |
| 1111 | |
| 1112 | /* if receiver buffer is empty then avail == 0 */ |
| 1113 | |
| 1114 | if (avail != 0 && size + 8 >= avail) |
| 1115 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1116 | DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n", |
| 1117 | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8)); |
| 1118 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1119 | s->IntrStatus |= RxOverflow; |
| 1120 | ++s->RxMissed; |
| 1121 | rtl8139_update_irq(s); |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 1122 | return size_; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1123 | } |
| 1124 | |
| 1125 | packet_header |= RxStatusOK; |
| 1126 | |
| 1127 | packet_header |= (((size+4) << 16) & 0xffff0000); |
| 1128 | |
| 1129 | /* write header */ |
| 1130 | uint32_t val = cpu_to_le32(packet_header); |
| 1131 | |
| 1132 | rtl8139_write_buffer(s, (uint8_t *)&val, 4); |
| 1133 | |
| 1134 | rtl8139_write_buffer(s, buf, size); |
| 1135 | |
| 1136 | /* write checksum */ |
| 1137 | #if defined (RTL8139_CALCULATE_RXCRC) |
ths | ccf1d14 | 2007-08-01 13:10:29 +0000 | [diff] [blame] | 1138 | val = cpu_to_le32(crc32(0, buf, size)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1139 | #else |
| 1140 | val = 0; |
| 1141 | #endif |
| 1142 | |
| 1143 | rtl8139_write_buffer(s, (uint8_t *)&val, 4); |
| 1144 | |
| 1145 | /* correct buffer write pointer */ |
| 1146 | s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize); |
| 1147 | |
| 1148 | /* now we can signal we have received something */ |
| 1149 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1150 | DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n", |
| 1151 | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1152 | } |
| 1153 | |
| 1154 | s->IntrStatus |= RxOK; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1155 | |
| 1156 | if (do_interrupt) |
| 1157 | { |
| 1158 | rtl8139_update_irq(s); |
| 1159 | } |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 1160 | |
| 1161 | return size_; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1162 | } |
| 1163 | |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 1164 | static ssize_t rtl8139_receive(VLANClientState *vc, const uint8_t *buf, size_t size) |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1165 | { |
Mark McLoughlin | 4f1c942 | 2009-05-18 13:40:55 +0100 | [diff] [blame] | 1166 | return rtl8139_do_receive(vc, buf, size, 1); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1167 | } |
| 1168 | |
| 1169 | static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) |
| 1170 | { |
| 1171 | s->RxBufferSize = bufferSize; |
| 1172 | s->RxBufPtr = 0; |
| 1173 | s->RxBufAddr = 0; |
| 1174 | } |
| 1175 | |
Michael S. Tsirkin | 7f23f81 | 2009-09-16 13:40:27 +0300 | [diff] [blame] | 1176 | static void rtl8139_reset(DeviceState *d) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1177 | { |
Michael S. Tsirkin | 7f23f81 | 2009-09-16 13:40:27 +0300 | [diff] [blame] | 1178 | RTL8139State *s = container_of(d, RTL8139State, dev.qdev); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1179 | int i; |
| 1180 | |
| 1181 | /* restore MAC address */ |
| 1182 | memcpy(s->phys, s->macaddr, 6); |
| 1183 | |
| 1184 | /* reset interrupt mask */ |
| 1185 | s->IntrStatus = 0; |
| 1186 | s->IntrMask = 0; |
| 1187 | |
| 1188 | rtl8139_update_irq(s); |
| 1189 | |
| 1190 | /* prepare eeprom */ |
| 1191 | s->eeprom.contents[0] = 0x8129; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1192 | #if 1 |
| 1193 | // PCI vendor and device ID should be mirrored here |
aliguori | deb5439 | 2009-01-26 15:37:35 +0000 | [diff] [blame] | 1194 | s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; |
| 1195 | s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1196 | #endif |
ths | 290a093 | 2007-03-19 18:20:28 +0000 | [diff] [blame] | 1197 | |
| 1198 | s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8; |
| 1199 | s->eeprom.contents[8] = s->macaddr[2] | s->macaddr[3] << 8; |
| 1200 | s->eeprom.contents[9] = s->macaddr[4] | s->macaddr[5] << 8; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1201 | |
| 1202 | /* mark all status registers as owned by host */ |
| 1203 | for (i = 0; i < 4; ++i) |
| 1204 | { |
| 1205 | s->TxStatus[i] = TxHostOwns; |
| 1206 | } |
| 1207 | |
| 1208 | s->currTxDesc = 0; |
| 1209 | s->currCPlusRxDesc = 0; |
| 1210 | s->currCPlusTxDesc = 0; |
| 1211 | |
| 1212 | s->RxRingAddrLO = 0; |
| 1213 | s->RxRingAddrHI = 0; |
| 1214 | |
| 1215 | s->RxBuf = 0; |
| 1216 | |
| 1217 | rtl8139_reset_rxring(s, 8192); |
| 1218 | |
| 1219 | /* ACK the reset */ |
| 1220 | s->TxConfig = 0; |
| 1221 | |
| 1222 | #if 0 |
| 1223 | // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk |
| 1224 | s->clock_enabled = 0; |
| 1225 | #else |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1226 | s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1227 | s->clock_enabled = 1; |
| 1228 | #endif |
| 1229 | |
| 1230 | s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; |
| 1231 | |
| 1232 | /* set initial state data */ |
| 1233 | s->Config0 = 0x0; /* No boot ROM */ |
| 1234 | s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ |
| 1235 | s->Config3 = 0x1; /* fast back-to-back compatible */ |
| 1236 | s->Config5 = 0x0; |
| 1237 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1238 | s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1239 | |
| 1240 | s->CpCmd = 0x0; /* reset C+ mode */ |
aliguori | 2c3891a | 2009-01-13 15:20:14 +0000 | [diff] [blame] | 1241 | s->cplus_enabled = 0; |
| 1242 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1243 | |
| 1244 | // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation |
| 1245 | // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex |
| 1246 | s->BasicModeCtrl = 0x1000; // autonegotiation |
| 1247 | |
| 1248 | s->BasicModeStatus = 0x7809; |
| 1249 | //s->BasicModeStatus |= 0x0040; /* UTP medium */ |
| 1250 | s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ |
| 1251 | s->BasicModeStatus |= 0x0004; /* link is up */ |
| 1252 | |
| 1253 | s->NWayAdvert = 0x05e1; /* all modes, full duplex */ |
| 1254 | s->NWayLPAR = 0x05e1; /* all modes, full duplex */ |
| 1255 | s->NWayExpansion = 0x0001; /* autonegotiation supported */ |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1256 | |
| 1257 | /* also reset timer and disable timer interrupt */ |
| 1258 | s->TCTR = 0; |
| 1259 | s->TimerInt = 0; |
| 1260 | s->TCTR_base = 0; |
| 1261 | |
| 1262 | /* reset tally counters */ |
| 1263 | RTL8139TallyCounters_clear(&s->tally_counters); |
| 1264 | } |
| 1265 | |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 1266 | static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1267 | { |
| 1268 | counters->TxOk = 0; |
| 1269 | counters->RxOk = 0; |
| 1270 | counters->TxERR = 0; |
| 1271 | counters->RxERR = 0; |
| 1272 | counters->MissPkt = 0; |
| 1273 | counters->FAE = 0; |
| 1274 | counters->Tx1Col = 0; |
| 1275 | counters->TxMCol = 0; |
| 1276 | counters->RxOkPhy = 0; |
| 1277 | counters->RxOkBrd = 0; |
| 1278 | counters->RxOkMul = 0; |
| 1279 | counters->TxAbt = 0; |
| 1280 | counters->TxUndrn = 0; |
| 1281 | } |
| 1282 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1283 | static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters) |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1284 | { |
| 1285 | uint16_t val16; |
| 1286 | uint32_t val32; |
| 1287 | uint64_t val64; |
| 1288 | |
| 1289 | val64 = cpu_to_le64(tally_counters->TxOk); |
| 1290 | cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8); |
| 1291 | |
| 1292 | val64 = cpu_to_le64(tally_counters->RxOk); |
| 1293 | cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8); |
| 1294 | |
| 1295 | val64 = cpu_to_le64(tally_counters->TxERR); |
| 1296 | cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8); |
| 1297 | |
| 1298 | val32 = cpu_to_le32(tally_counters->RxERR); |
| 1299 | cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4); |
| 1300 | |
| 1301 | val16 = cpu_to_le16(tally_counters->MissPkt); |
| 1302 | cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2); |
| 1303 | |
| 1304 | val16 = cpu_to_le16(tally_counters->FAE); |
| 1305 | cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2); |
| 1306 | |
| 1307 | val32 = cpu_to_le32(tally_counters->Tx1Col); |
| 1308 | cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4); |
| 1309 | |
| 1310 | val32 = cpu_to_le32(tally_counters->TxMCol); |
| 1311 | cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4); |
| 1312 | |
| 1313 | val64 = cpu_to_le64(tally_counters->RxOkPhy); |
| 1314 | cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8); |
| 1315 | |
| 1316 | val64 = cpu_to_le64(tally_counters->RxOkBrd); |
| 1317 | cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8); |
| 1318 | |
| 1319 | val32 = cpu_to_le32(tally_counters->RxOkMul); |
| 1320 | cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4); |
| 1321 | |
| 1322 | val16 = cpu_to_le16(tally_counters->TxAbt); |
| 1323 | cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2); |
| 1324 | |
| 1325 | val16 = cpu_to_le16(tally_counters->TxUndrn); |
| 1326 | cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2); |
| 1327 | } |
| 1328 | |
| 1329 | /* Loads values of tally counters from VM state file */ |
| 1330 | static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters) |
| 1331 | { |
| 1332 | qemu_get_be64s(f, &tally_counters->TxOk); |
| 1333 | qemu_get_be64s(f, &tally_counters->RxOk); |
| 1334 | qemu_get_be64s(f, &tally_counters->TxERR); |
| 1335 | qemu_get_be32s(f, &tally_counters->RxERR); |
| 1336 | qemu_get_be16s(f, &tally_counters->MissPkt); |
| 1337 | qemu_get_be16s(f, &tally_counters->FAE); |
| 1338 | qemu_get_be32s(f, &tally_counters->Tx1Col); |
| 1339 | qemu_get_be32s(f, &tally_counters->TxMCol); |
| 1340 | qemu_get_be64s(f, &tally_counters->RxOkPhy); |
| 1341 | qemu_get_be64s(f, &tally_counters->RxOkBrd); |
| 1342 | qemu_get_be32s(f, &tally_counters->RxOkMul); |
| 1343 | qemu_get_be16s(f, &tally_counters->TxAbt); |
| 1344 | qemu_get_be16s(f, &tally_counters->TxUndrn); |
| 1345 | } |
| 1346 | |
| 1347 | /* Saves values of tally counters to VM state file */ |
| 1348 | static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters) |
| 1349 | { |
| 1350 | qemu_put_be64s(f, &tally_counters->TxOk); |
| 1351 | qemu_put_be64s(f, &tally_counters->RxOk); |
| 1352 | qemu_put_be64s(f, &tally_counters->TxERR); |
| 1353 | qemu_put_be32s(f, &tally_counters->RxERR); |
| 1354 | qemu_put_be16s(f, &tally_counters->MissPkt); |
| 1355 | qemu_put_be16s(f, &tally_counters->FAE); |
| 1356 | qemu_put_be32s(f, &tally_counters->Tx1Col); |
| 1357 | qemu_put_be32s(f, &tally_counters->TxMCol); |
| 1358 | qemu_put_be64s(f, &tally_counters->RxOkPhy); |
| 1359 | qemu_put_be64s(f, &tally_counters->RxOkBrd); |
| 1360 | qemu_put_be32s(f, &tally_counters->RxOkMul); |
| 1361 | qemu_put_be16s(f, &tally_counters->TxAbt); |
| 1362 | qemu_put_be16s(f, &tally_counters->TxUndrn); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1363 | } |
| 1364 | |
| 1365 | static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) |
| 1366 | { |
| 1367 | val &= 0xff; |
| 1368 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1369 | DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1370 | |
| 1371 | if (val & CmdReset) |
| 1372 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1373 | DEBUG_PRINT(("RTL8139: ChipCmd reset\n")); |
Michael S. Tsirkin | 7f23f81 | 2009-09-16 13:40:27 +0300 | [diff] [blame] | 1374 | rtl8139_reset(&s->dev.qdev); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1375 | } |
| 1376 | if (val & CmdRxEnb) |
| 1377 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1378 | DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n")); |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 1379 | |
| 1380 | s->currCPlusRxDesc = 0; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1381 | } |
| 1382 | if (val & CmdTxEnb) |
| 1383 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1384 | DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n")); |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 1385 | |
| 1386 | s->currCPlusTxDesc = 0; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1387 | } |
| 1388 | |
| 1389 | /* mask unwriteable bits */ |
| 1390 | val = SET_MASKED(val, 0xe3, s->bChipCmdState); |
| 1391 | |
| 1392 | /* Deassert reset pin before next read */ |
| 1393 | val &= ~CmdReset; |
| 1394 | |
| 1395 | s->bChipCmdState = val; |
| 1396 | } |
| 1397 | |
| 1398 | static int rtl8139_RxBufferEmpty(RTL8139State *s) |
| 1399 | { |
| 1400 | int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); |
| 1401 | |
| 1402 | if (unread != 0) |
| 1403 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1404 | DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1405 | return 0; |
| 1406 | } |
| 1407 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1408 | DEBUG_PRINT(("RTL8139: receiver buffer is empty\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1409 | |
| 1410 | return 1; |
| 1411 | } |
| 1412 | |
| 1413 | static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) |
| 1414 | { |
| 1415 | uint32_t ret = s->bChipCmdState; |
| 1416 | |
| 1417 | if (rtl8139_RxBufferEmpty(s)) |
| 1418 | ret |= RxBufEmpty; |
| 1419 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1420 | DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1421 | |
| 1422 | return ret; |
| 1423 | } |
| 1424 | |
| 1425 | static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) |
| 1426 | { |
| 1427 | val &= 0xffff; |
| 1428 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1429 | DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1430 | |
aliguori | 2c3891a | 2009-01-13 15:20:14 +0000 | [diff] [blame] | 1431 | s->cplus_enabled = 1; |
| 1432 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1433 | /* mask unwriteable bits */ |
| 1434 | val = SET_MASKED(val, 0xff84, s->CpCmd); |
| 1435 | |
| 1436 | s->CpCmd = val; |
| 1437 | } |
| 1438 | |
| 1439 | static uint32_t rtl8139_CpCmd_read(RTL8139State *s) |
| 1440 | { |
| 1441 | uint32_t ret = s->CpCmd; |
| 1442 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1443 | DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret)); |
| 1444 | |
| 1445 | return ret; |
| 1446 | } |
| 1447 | |
| 1448 | static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) |
| 1449 | { |
| 1450 | DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val)); |
| 1451 | } |
| 1452 | |
| 1453 | static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s) |
| 1454 | { |
| 1455 | uint32_t ret = 0; |
| 1456 | |
| 1457 | DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1458 | |
| 1459 | return ret; |
| 1460 | } |
| 1461 | |
pbrook | 9596ebb | 2007-11-18 01:44:38 +0000 | [diff] [blame] | 1462 | static int rtl8139_config_writeable(RTL8139State *s) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1463 | { |
| 1464 | if (s->Cfg9346 & Cfg9346_Unlock) |
| 1465 | { |
| 1466 | return 1; |
| 1467 | } |
| 1468 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1469 | DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1470 | |
| 1471 | return 0; |
| 1472 | } |
| 1473 | |
| 1474 | static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) |
| 1475 | { |
| 1476 | val &= 0xffff; |
| 1477 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1478 | DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1479 | |
| 1480 | /* mask unwriteable bits */ |
ths | e3d7e84 | 2007-11-09 18:17:50 +0000 | [diff] [blame] | 1481 | uint32_t mask = 0x4cff; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1482 | |
| 1483 | if (1 || !rtl8139_config_writeable(s)) |
| 1484 | { |
| 1485 | /* Speed setting and autonegotiation enable bits are read-only */ |
| 1486 | mask |= 0x3000; |
| 1487 | /* Duplex mode setting is read-only */ |
| 1488 | mask |= 0x0100; |
| 1489 | } |
| 1490 | |
| 1491 | val = SET_MASKED(val, mask, s->BasicModeCtrl); |
| 1492 | |
| 1493 | s->BasicModeCtrl = val; |
| 1494 | } |
| 1495 | |
| 1496 | static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) |
| 1497 | { |
| 1498 | uint32_t ret = s->BasicModeCtrl; |
| 1499 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1500 | DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1501 | |
| 1502 | return ret; |
| 1503 | } |
| 1504 | |
| 1505 | static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) |
| 1506 | { |
| 1507 | val &= 0xffff; |
| 1508 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1509 | DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1510 | |
| 1511 | /* mask unwriteable bits */ |
| 1512 | val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); |
| 1513 | |
| 1514 | s->BasicModeStatus = val; |
| 1515 | } |
| 1516 | |
| 1517 | static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) |
| 1518 | { |
| 1519 | uint32_t ret = s->BasicModeStatus; |
| 1520 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1521 | DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1522 | |
| 1523 | return ret; |
| 1524 | } |
| 1525 | |
| 1526 | static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) |
| 1527 | { |
| 1528 | val &= 0xff; |
| 1529 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1530 | DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1531 | |
| 1532 | /* mask unwriteable bits */ |
| 1533 | val = SET_MASKED(val, 0x31, s->Cfg9346); |
| 1534 | |
| 1535 | uint32_t opmode = val & 0xc0; |
| 1536 | uint32_t eeprom_val = val & 0xf; |
| 1537 | |
| 1538 | if (opmode == 0x80) { |
| 1539 | /* eeprom access */ |
| 1540 | int eecs = (eeprom_val & 0x08)?1:0; |
| 1541 | int eesk = (eeprom_val & 0x04)?1:0; |
| 1542 | int eedi = (eeprom_val & 0x02)?1:0; |
| 1543 | prom9346_set_wire(s, eecs, eesk, eedi); |
| 1544 | } else if (opmode == 0x40) { |
| 1545 | /* Reset. */ |
| 1546 | val = 0; |
Michael S. Tsirkin | 7f23f81 | 2009-09-16 13:40:27 +0300 | [diff] [blame] | 1547 | rtl8139_reset(&s->dev.qdev); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1548 | } |
| 1549 | |
| 1550 | s->Cfg9346 = val; |
| 1551 | } |
| 1552 | |
| 1553 | static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) |
| 1554 | { |
| 1555 | uint32_t ret = s->Cfg9346; |
| 1556 | |
| 1557 | uint32_t opmode = ret & 0xc0; |
| 1558 | |
| 1559 | if (opmode == 0x80) |
| 1560 | { |
| 1561 | /* eeprom access */ |
| 1562 | int eedo = prom9346_get_wire(s); |
| 1563 | if (eedo) |
| 1564 | { |
| 1565 | ret |= 0x01; |
| 1566 | } |
| 1567 | else |
| 1568 | { |
| 1569 | ret &= ~0x01; |
| 1570 | } |
| 1571 | } |
| 1572 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1573 | DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1574 | |
| 1575 | return ret; |
| 1576 | } |
| 1577 | |
| 1578 | static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) |
| 1579 | { |
| 1580 | val &= 0xff; |
| 1581 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1582 | DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1583 | |
| 1584 | if (!rtl8139_config_writeable(s)) |
| 1585 | return; |
| 1586 | |
| 1587 | /* mask unwriteable bits */ |
| 1588 | val = SET_MASKED(val, 0xf8, s->Config0); |
| 1589 | |
| 1590 | s->Config0 = val; |
| 1591 | } |
| 1592 | |
| 1593 | static uint32_t rtl8139_Config0_read(RTL8139State *s) |
| 1594 | { |
| 1595 | uint32_t ret = s->Config0; |
| 1596 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1597 | DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1598 | |
| 1599 | return ret; |
| 1600 | } |
| 1601 | |
| 1602 | static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) |
| 1603 | { |
| 1604 | val &= 0xff; |
| 1605 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1606 | DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1607 | |
| 1608 | if (!rtl8139_config_writeable(s)) |
| 1609 | return; |
| 1610 | |
| 1611 | /* mask unwriteable bits */ |
| 1612 | val = SET_MASKED(val, 0xC, s->Config1); |
| 1613 | |
| 1614 | s->Config1 = val; |
| 1615 | } |
| 1616 | |
| 1617 | static uint32_t rtl8139_Config1_read(RTL8139State *s) |
| 1618 | { |
| 1619 | uint32_t ret = s->Config1; |
| 1620 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1621 | DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1622 | |
| 1623 | return ret; |
| 1624 | } |
| 1625 | |
| 1626 | static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) |
| 1627 | { |
| 1628 | val &= 0xff; |
| 1629 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1630 | DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1631 | |
| 1632 | if (!rtl8139_config_writeable(s)) |
| 1633 | return; |
| 1634 | |
| 1635 | /* mask unwriteable bits */ |
| 1636 | val = SET_MASKED(val, 0x8F, s->Config3); |
| 1637 | |
| 1638 | s->Config3 = val; |
| 1639 | } |
| 1640 | |
| 1641 | static uint32_t rtl8139_Config3_read(RTL8139State *s) |
| 1642 | { |
| 1643 | uint32_t ret = s->Config3; |
| 1644 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1645 | DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1646 | |
| 1647 | return ret; |
| 1648 | } |
| 1649 | |
| 1650 | static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) |
| 1651 | { |
| 1652 | val &= 0xff; |
| 1653 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1654 | DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1655 | |
| 1656 | if (!rtl8139_config_writeable(s)) |
| 1657 | return; |
| 1658 | |
| 1659 | /* mask unwriteable bits */ |
| 1660 | val = SET_MASKED(val, 0x0a, s->Config4); |
| 1661 | |
| 1662 | s->Config4 = val; |
| 1663 | } |
| 1664 | |
| 1665 | static uint32_t rtl8139_Config4_read(RTL8139State *s) |
| 1666 | { |
| 1667 | uint32_t ret = s->Config4; |
| 1668 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1669 | DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1670 | |
| 1671 | return ret; |
| 1672 | } |
| 1673 | |
| 1674 | static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) |
| 1675 | { |
| 1676 | val &= 0xff; |
| 1677 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1678 | DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1679 | |
| 1680 | /* mask unwriteable bits */ |
| 1681 | val = SET_MASKED(val, 0x80, s->Config5); |
| 1682 | |
| 1683 | s->Config5 = val; |
| 1684 | } |
| 1685 | |
| 1686 | static uint32_t rtl8139_Config5_read(RTL8139State *s) |
| 1687 | { |
| 1688 | uint32_t ret = s->Config5; |
| 1689 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1690 | DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1691 | |
| 1692 | return ret; |
| 1693 | } |
| 1694 | |
| 1695 | static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) |
| 1696 | { |
| 1697 | if (!rtl8139_transmitter_enabled(s)) |
| 1698 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1699 | DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1700 | return; |
| 1701 | } |
| 1702 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1703 | DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1704 | |
| 1705 | val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); |
| 1706 | |
| 1707 | s->TxConfig = val; |
| 1708 | } |
| 1709 | |
| 1710 | static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) |
| 1711 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1712 | DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val)); |
| 1713 | |
| 1714 | uint32_t tc = s->TxConfig; |
| 1715 | tc &= 0xFFFFFF00; |
| 1716 | tc |= (val & 0x000000FF); |
| 1717 | rtl8139_TxConfig_write(s, tc); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1718 | } |
| 1719 | |
| 1720 | static uint32_t rtl8139_TxConfig_read(RTL8139State *s) |
| 1721 | { |
| 1722 | uint32_t ret = s->TxConfig; |
| 1723 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1724 | DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1725 | |
| 1726 | return ret; |
| 1727 | } |
| 1728 | |
| 1729 | static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) |
| 1730 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1731 | DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1732 | |
| 1733 | /* mask unwriteable bits */ |
| 1734 | val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); |
| 1735 | |
| 1736 | s->RxConfig = val; |
| 1737 | |
| 1738 | /* reset buffer size and read/write pointers */ |
| 1739 | rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); |
| 1740 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1741 | DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1742 | } |
| 1743 | |
| 1744 | static uint32_t rtl8139_RxConfig_read(RTL8139State *s) |
| 1745 | { |
| 1746 | uint32_t ret = s->RxConfig; |
| 1747 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1748 | DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1749 | |
| 1750 | return ret; |
| 1751 | } |
| 1752 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 1753 | static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt) |
| 1754 | { |
| 1755 | if (!size) |
| 1756 | { |
| 1757 | DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n")); |
| 1758 | return; |
| 1759 | } |
| 1760 | |
| 1761 | if (TxLoopBack == (s->TxConfig & TxLoopBack)) |
| 1762 | { |
| 1763 | DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n")); |
Mark McLoughlin | e3f5ec2 | 2009-05-18 13:33:03 +0100 | [diff] [blame] | 1764 | rtl8139_do_receive(s->vc, buf, size, do_interrupt); |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 1765 | } |
| 1766 | else |
| 1767 | { |
| 1768 | qemu_send_packet(s->vc, buf, size); |
| 1769 | } |
| 1770 | } |
| 1771 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1772 | static int rtl8139_transmit_one(RTL8139State *s, int descriptor) |
| 1773 | { |
| 1774 | if (!rtl8139_transmitter_enabled(s)) |
| 1775 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1776 | DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n", |
| 1777 | descriptor)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1778 | return 0; |
| 1779 | } |
| 1780 | |
| 1781 | if (s->TxStatus[descriptor] & TxHostOwns) |
| 1782 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1783 | DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n", |
| 1784 | descriptor, s->TxStatus[descriptor])); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1785 | return 0; |
| 1786 | } |
| 1787 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1788 | DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1789 | |
| 1790 | int txsize = s->TxStatus[descriptor] & 0x1fff; |
| 1791 | uint8_t txbuffer[0x2000]; |
| 1792 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1793 | DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n", |
| 1794 | txsize, s->TxAddr[descriptor])); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1795 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1796 | cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1797 | |
| 1798 | /* Mark descriptor as transferred */ |
| 1799 | s->TxStatus[descriptor] |= TxHostOwns; |
| 1800 | s->TxStatus[descriptor] |= TxStatOK; |
| 1801 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 1802 | rtl8139_transfer_frame(s, txbuffer, txsize, 0); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1803 | |
| 1804 | DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1805 | |
| 1806 | /* update interrupt */ |
| 1807 | s->IntrStatus |= TxOK; |
| 1808 | rtl8139_update_irq(s); |
| 1809 | |
| 1810 | return 1; |
| 1811 | } |
| 1812 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 1813 | /* structures and macros for task offloading */ |
| 1814 | typedef struct ip_header |
| 1815 | { |
| 1816 | uint8_t ip_ver_len; /* version and header length */ |
| 1817 | uint8_t ip_tos; /* type of service */ |
| 1818 | uint16_t ip_len; /* total length */ |
| 1819 | uint16_t ip_id; /* identification */ |
| 1820 | uint16_t ip_off; /* fragment offset field */ |
| 1821 | uint8_t ip_ttl; /* time to live */ |
| 1822 | uint8_t ip_p; /* protocol */ |
| 1823 | uint16_t ip_sum; /* checksum */ |
| 1824 | uint32_t ip_src,ip_dst; /* source and dest address */ |
| 1825 | } ip_header; |
| 1826 | |
| 1827 | #define IP_HEADER_VERSION_4 4 |
| 1828 | #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf) |
| 1829 | #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2) |
| 1830 | |
| 1831 | typedef struct tcp_header |
| 1832 | { |
| 1833 | uint16_t th_sport; /* source port */ |
| 1834 | uint16_t th_dport; /* destination port */ |
| 1835 | uint32_t th_seq; /* sequence number */ |
| 1836 | uint32_t th_ack; /* acknowledgement number */ |
| 1837 | uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */ |
| 1838 | uint16_t th_win; /* window */ |
| 1839 | uint16_t th_sum; /* checksum */ |
| 1840 | uint16_t th_urp; /* urgent pointer */ |
| 1841 | } tcp_header; |
| 1842 | |
| 1843 | typedef struct udp_header |
| 1844 | { |
| 1845 | uint16_t uh_sport; /* source port */ |
| 1846 | uint16_t uh_dport; /* destination port */ |
| 1847 | uint16_t uh_ulen; /* udp length */ |
| 1848 | uint16_t uh_sum; /* udp checksum */ |
| 1849 | } udp_header; |
| 1850 | |
| 1851 | typedef struct ip_pseudo_header |
| 1852 | { |
| 1853 | uint32_t ip_src; |
| 1854 | uint32_t ip_dst; |
| 1855 | uint8_t zeros; |
| 1856 | uint8_t ip_proto; |
| 1857 | uint16_t ip_payload; |
| 1858 | } ip_pseudo_header; |
| 1859 | |
| 1860 | #define IP_PROTO_TCP 6 |
| 1861 | #define IP_PROTO_UDP 17 |
| 1862 | |
| 1863 | #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2) |
| 1864 | #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f) |
| 1865 | #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags)) |
| 1866 | |
| 1867 | #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) |
| 1868 | |
| 1869 | #define TCP_FLAG_FIN 0x01 |
| 1870 | #define TCP_FLAG_PUSH 0x08 |
| 1871 | |
| 1872 | /* produces ones' complement sum of data */ |
| 1873 | static uint16_t ones_complement_sum(uint8_t *data, size_t len) |
| 1874 | { |
| 1875 | uint32_t result = 0; |
| 1876 | |
| 1877 | for (; len > 1; data+=2, len-=2) |
| 1878 | { |
| 1879 | result += *(uint16_t*)data; |
| 1880 | } |
| 1881 | |
| 1882 | /* add the remainder byte */ |
| 1883 | if (len) |
| 1884 | { |
| 1885 | uint8_t odd[2] = {*data, 0}; |
| 1886 | result += *(uint16_t*)odd; |
| 1887 | } |
| 1888 | |
| 1889 | while (result>>16) |
| 1890 | result = (result & 0xffff) + (result >> 16); |
| 1891 | |
| 1892 | return result; |
| 1893 | } |
| 1894 | |
| 1895 | static uint16_t ip_checksum(void *data, size_t len) |
| 1896 | { |
| 1897 | return ~ones_complement_sum((uint8_t*)data, len); |
| 1898 | } |
| 1899 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1900 | static int rtl8139_cplus_transmit_one(RTL8139State *s) |
| 1901 | { |
| 1902 | if (!rtl8139_transmitter_enabled(s)) |
| 1903 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1904 | DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1905 | return 0; |
| 1906 | } |
| 1907 | |
| 1908 | if (!rtl8139_cp_transmitter_enabled(s)) |
| 1909 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1910 | DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1911 | return 0 ; |
| 1912 | } |
| 1913 | |
| 1914 | int descriptor = s->currCPlusTxDesc; |
| 1915 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1916 | target_phys_addr_t cplus_tx_ring_desc = |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1917 | rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); |
| 1918 | |
| 1919 | /* Normal priority ring */ |
| 1920 | cplus_tx_ring_desc += 16 * descriptor; |
| 1921 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1922 | DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n", |
| 1923 | descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1924 | |
| 1925 | uint32_t val, txdw0,txdw1,txbufLO,txbufHI; |
| 1926 | |
| 1927 | cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4); |
| 1928 | txdw0 = le32_to_cpu(val); |
| 1929 | cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4); |
| 1930 | txdw1 = le32_to_cpu(val); |
| 1931 | cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4); |
| 1932 | txbufLO = le32_to_cpu(val); |
| 1933 | cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4); |
| 1934 | txbufHI = le32_to_cpu(val); |
| 1935 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1936 | DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1937 | descriptor, |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1938 | txdw0, txdw1, txbufLO, txbufHI)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1939 | |
| 1940 | /* w0 ownership flag */ |
| 1941 | #define CP_TX_OWN (1<<31) |
| 1942 | /* w0 end of ring flag */ |
| 1943 | #define CP_TX_EOR (1<<30) |
| 1944 | /* first segment of received packet flag */ |
| 1945 | #define CP_TX_FS (1<<29) |
| 1946 | /* last segment of received packet flag */ |
| 1947 | #define CP_TX_LS (1<<28) |
| 1948 | /* large send packet flag */ |
| 1949 | #define CP_TX_LGSEN (1<<27) |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 1950 | /* large send MSS mask, bits 16...25 */ |
| 1951 | #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) |
| 1952 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1953 | /* IP checksum offload flag */ |
| 1954 | #define CP_TX_IPCS (1<<18) |
| 1955 | /* UDP checksum offload flag */ |
| 1956 | #define CP_TX_UDPCS (1<<17) |
| 1957 | /* TCP checksum offload flag */ |
| 1958 | #define CP_TX_TCPCS (1<<16) |
| 1959 | |
| 1960 | /* w0 bits 0...15 : buffer size */ |
| 1961 | #define CP_TX_BUFFER_SIZE (1<<16) |
| 1962 | #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) |
| 1963 | /* w1 tag available flag */ |
| 1964 | #define CP_RX_TAGC (1<<17) |
| 1965 | /* w1 bits 0...15 : VLAN tag */ |
| 1966 | #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) |
| 1967 | /* w2 low 32bit of Rx buffer ptr */ |
| 1968 | /* w3 high 32bit of Rx buffer ptr */ |
| 1969 | |
| 1970 | /* set after transmission */ |
| 1971 | /* FIFO underrun flag */ |
| 1972 | #define CP_TX_STATUS_UNF (1<<25) |
| 1973 | /* transmit error summary flag, valid if set any of three below */ |
| 1974 | #define CP_TX_STATUS_TES (1<<23) |
| 1975 | /* out-of-window collision flag */ |
| 1976 | #define CP_TX_STATUS_OWC (1<<22) |
| 1977 | /* link failure flag */ |
| 1978 | #define CP_TX_STATUS_LNKF (1<<21) |
| 1979 | /* excessive collisions flag */ |
| 1980 | #define CP_TX_STATUS_EXC (1<<20) |
| 1981 | |
| 1982 | if (!(txdw0 & CP_TX_OWN)) |
| 1983 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1984 | DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1985 | return 0 ; |
| 1986 | } |
| 1987 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 1988 | DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor)); |
| 1989 | |
| 1990 | if (txdw0 & CP_TX_FS) |
| 1991 | { |
| 1992 | DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor)); |
| 1993 | |
| 1994 | /* reset internal buffer offset */ |
| 1995 | s->cplus_txbuffer_offset = 0; |
| 1996 | } |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 1997 | |
| 1998 | int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1999 | target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2000 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2001 | /* make sure we have enough space to assemble the packet */ |
| 2002 | if (!s->cplus_txbuffer) |
| 2003 | { |
| 2004 | s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; |
| 2005 | s->cplus_txbuffer = malloc(s->cplus_txbuffer_len); |
| 2006 | s->cplus_txbuffer_offset = 0; |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2007 | |
| 2008 | DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len)); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2009 | } |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2010 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2011 | while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) |
| 2012 | { |
| 2013 | s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE; |
ths | 2137b4c | 2008-08-06 08:37:17 +0000 | [diff] [blame] | 2014 | s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2015 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2016 | DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len)); |
| 2017 | } |
| 2018 | |
| 2019 | if (!s->cplus_txbuffer) |
| 2020 | { |
| 2021 | /* out of memory */ |
| 2022 | |
| 2023 | DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len)); |
| 2024 | |
| 2025 | /* update tally counter */ |
| 2026 | ++s->tally_counters.TxERR; |
| 2027 | ++s->tally_counters.TxAbt; |
| 2028 | |
| 2029 | return 0; |
| 2030 | } |
| 2031 | |
| 2032 | /* append more data to the packet */ |
| 2033 | |
| 2034 | DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n", |
| 2035 | txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset)); |
| 2036 | |
| 2037 | cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); |
| 2038 | s->cplus_txbuffer_offset += txsize; |
| 2039 | |
| 2040 | /* seek to next Rx descriptor */ |
| 2041 | if (txdw0 & CP_TX_EOR) |
| 2042 | { |
| 2043 | s->currCPlusTxDesc = 0; |
| 2044 | } |
| 2045 | else |
| 2046 | { |
| 2047 | ++s->currCPlusTxDesc; |
| 2048 | if (s->currCPlusTxDesc >= 64) |
| 2049 | s->currCPlusTxDesc = 0; |
| 2050 | } |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2051 | |
| 2052 | /* transfer ownership to target */ |
| 2053 | txdw0 &= ~CP_RX_OWN; |
| 2054 | |
| 2055 | /* reset error indicator bits */ |
| 2056 | txdw0 &= ~CP_TX_STATUS_UNF; |
| 2057 | txdw0 &= ~CP_TX_STATUS_TES; |
| 2058 | txdw0 &= ~CP_TX_STATUS_OWC; |
| 2059 | txdw0 &= ~CP_TX_STATUS_LNKF; |
| 2060 | txdw0 &= ~CP_TX_STATUS_EXC; |
| 2061 | |
| 2062 | /* update ring data */ |
| 2063 | val = cpu_to_le32(txdw0); |
| 2064 | cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4); |
| 2065 | // val = cpu_to_le32(txdw1); |
| 2066 | // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4); |
| 2067 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2068 | /* Now decide if descriptor being processed is holding the last segment of packet */ |
| 2069 | if (txdw0 & CP_TX_LS) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2070 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2071 | DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor)); |
| 2072 | |
| 2073 | /* can transfer fully assembled packet */ |
| 2074 | |
| 2075 | uint8_t *saved_buffer = s->cplus_txbuffer; |
| 2076 | int saved_size = s->cplus_txbuffer_offset; |
| 2077 | int saved_buffer_len = s->cplus_txbuffer_len; |
| 2078 | |
| 2079 | /* reset the card space to protect from recursive call */ |
| 2080 | s->cplus_txbuffer = NULL; |
| 2081 | s->cplus_txbuffer_offset = 0; |
| 2082 | s->cplus_txbuffer_len = 0; |
| 2083 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2084 | if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2085 | { |
| 2086 | DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n")); |
| 2087 | |
| 2088 | #define ETH_P_IP 0x0800 /* Internet Protocol packet */ |
| 2089 | #define ETH_HLEN 14 |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2090 | #define ETH_MTU 1500 |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2091 | |
| 2092 | /* ip packet header */ |
Blue Swirl | 660f11b | 2009-07-31 21:16:51 +0000 | [diff] [blame] | 2093 | ip_header *ip = NULL; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2094 | int hlen = 0; |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2095 | uint8_t ip_protocol = 0; |
| 2096 | uint16_t ip_data_len = 0; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2097 | |
Blue Swirl | 660f11b | 2009-07-31 21:16:51 +0000 | [diff] [blame] | 2098 | uint8_t *eth_payload_data = NULL; |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2099 | size_t eth_payload_len = 0; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2100 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2101 | int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2102 | if (proto == ETH_P_IP) |
| 2103 | { |
| 2104 | DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n")); |
| 2105 | |
| 2106 | /* not aligned */ |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2107 | eth_payload_data = saved_buffer + ETH_HLEN; |
| 2108 | eth_payload_len = saved_size - ETH_HLEN; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2109 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2110 | ip = (ip_header*)eth_payload_data; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2111 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2112 | if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { |
| 2113 | DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4)); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2114 | ip = NULL; |
| 2115 | } else { |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2116 | hlen = IP_HEADER_LENGTH(ip); |
| 2117 | ip_protocol = ip->ip_p; |
| 2118 | ip_data_len = be16_to_cpu(ip->ip_len) - hlen; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2119 | } |
| 2120 | } |
| 2121 | |
| 2122 | if (ip) |
| 2123 | { |
| 2124 | if (txdw0 & CP_TX_IPCS) |
| 2125 | { |
| 2126 | DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n")); |
| 2127 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2128 | if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */ |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2129 | /* bad packet header len */ |
| 2130 | /* or packet too short */ |
| 2131 | } |
| 2132 | else |
| 2133 | { |
| 2134 | ip->ip_sum = 0; |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2135 | ip->ip_sum = ip_checksum(ip, hlen); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2136 | DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum)); |
| 2137 | } |
| 2138 | } |
| 2139 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2140 | if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2141 | { |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2142 | #if defined (DEBUG_RTL8139) |
| 2143 | int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; |
| 2144 | #endif |
| 2145 | DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n", |
| 2146 | ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss)); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2147 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2148 | int tcp_send_offset = 0; |
| 2149 | int send_count = 0; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2150 | |
| 2151 | /* maximum IP header length is 60 bytes */ |
| 2152 | uint8_t saved_ip_header[60]; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2153 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2154 | /* save IP header template; data area is used in tcp checksum calculation */ |
| 2155 | memcpy(saved_ip_header, eth_payload_data, hlen); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2156 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2157 | /* a placeholder for checksum calculation routine in tcp case */ |
| 2158 | uint8_t *data_to_checksum = eth_payload_data + hlen - 12; |
| 2159 | // size_t data_to_checksum_len = eth_payload_len - hlen + 12; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2160 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2161 | /* pointer to TCP header */ |
| 2162 | tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2163 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2164 | int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); |
| 2165 | |
| 2166 | /* ETH_MTU = ip header len + tcp header len + payload */ |
| 2167 | int tcp_data_len = ip_data_len - tcp_hlen; |
| 2168 | int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen; |
| 2169 | |
| 2170 | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n", |
| 2171 | ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size)); |
| 2172 | |
| 2173 | /* note the cycle below overwrites IP header data, |
| 2174 | but restores it from saved_ip_header before sending packet */ |
| 2175 | |
| 2176 | int is_last_frame = 0; |
| 2177 | |
| 2178 | for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2179 | { |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2180 | uint16_t chunk_size = tcp_chunk_size; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2181 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2182 | /* check if this is the last frame */ |
| 2183 | if (tcp_send_offset + tcp_chunk_size >= tcp_data_len) |
| 2184 | { |
| 2185 | is_last_frame = 1; |
| 2186 | chunk_size = tcp_data_len - tcp_send_offset; |
| 2187 | } |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2188 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2189 | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq))); |
| 2190 | |
| 2191 | /* add 4 TCP pseudoheader fields */ |
| 2192 | /* copy IP source and destination fields */ |
| 2193 | memcpy(data_to_checksum, saved_ip_header + 12, 8); |
| 2194 | |
| 2195 | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size)); |
| 2196 | |
| 2197 | if (tcp_send_offset) |
| 2198 | { |
| 2199 | memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); |
| 2200 | } |
| 2201 | |
| 2202 | /* keep PUSH and FIN flags only for the last frame */ |
| 2203 | if (!is_last_frame) |
| 2204 | { |
| 2205 | TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN); |
| 2206 | } |
| 2207 | |
| 2208 | /* recalculate TCP checksum */ |
| 2209 | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
| 2210 | p_tcpip_hdr->zeros = 0; |
| 2211 | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
| 2212 | p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2213 | |
| 2214 | p_tcp_hdr->th_sum = 0; |
| 2215 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2216 | int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); |
| 2217 | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum)); |
| 2218 | |
| 2219 | p_tcp_hdr->th_sum = tcp_checksum; |
| 2220 | |
| 2221 | /* restore IP header */ |
| 2222 | memcpy(eth_payload_data, saved_ip_header, hlen); |
| 2223 | |
| 2224 | /* set IP data length and recalculate IP checksum */ |
| 2225 | ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); |
| 2226 | |
| 2227 | /* increment IP id for subsequent frames */ |
| 2228 | ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); |
| 2229 | |
| 2230 | ip->ip_sum = 0; |
| 2231 | ip->ip_sum = ip_checksum(eth_payload_data, hlen); |
| 2232 | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum)); |
| 2233 | |
| 2234 | int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; |
| 2235 | DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size)); |
| 2236 | rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0); |
| 2237 | |
| 2238 | /* add transferred count to TCP sequence number */ |
| 2239 | p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq)); |
| 2240 | ++send_count; |
| 2241 | } |
| 2242 | |
| 2243 | /* Stop sending this frame */ |
| 2244 | saved_size = 0; |
| 2245 | } |
| 2246 | else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) |
| 2247 | { |
| 2248 | DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n")); |
| 2249 | |
| 2250 | /* maximum IP header length is 60 bytes */ |
| 2251 | uint8_t saved_ip_header[60]; |
| 2252 | memcpy(saved_ip_header, eth_payload_data, hlen); |
| 2253 | |
| 2254 | uint8_t *data_to_checksum = eth_payload_data + hlen - 12; |
| 2255 | // size_t data_to_checksum_len = eth_payload_len - hlen + 12; |
| 2256 | |
| 2257 | /* add 4 TCP pseudoheader fields */ |
| 2258 | /* copy IP source and destination fields */ |
| 2259 | memcpy(data_to_checksum, saved_ip_header + 12, 8); |
| 2260 | |
| 2261 | if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) |
| 2262 | { |
| 2263 | DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len)); |
| 2264 | |
| 2265 | ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; |
| 2266 | p_tcpip_hdr->zeros = 0; |
| 2267 | p_tcpip_hdr->ip_proto = IP_PROTO_TCP; |
| 2268 | p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
| 2269 | |
| 2270 | tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); |
| 2271 | |
| 2272 | p_tcp_hdr->th_sum = 0; |
| 2273 | |
| 2274 | int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2275 | DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum)); |
| 2276 | |
| 2277 | p_tcp_hdr->th_sum = tcp_checksum; |
| 2278 | } |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2279 | else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2280 | { |
| 2281 | DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len)); |
| 2282 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2283 | ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; |
| 2284 | p_udpip_hdr->zeros = 0; |
| 2285 | p_udpip_hdr->ip_proto = IP_PROTO_UDP; |
| 2286 | p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2287 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2288 | udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2289 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2290 | p_udp_hdr->uh_sum = 0; |
| 2291 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2292 | int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2293 | DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum)); |
| 2294 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2295 | p_udp_hdr->uh_sum = udp_checksum; |
| 2296 | } |
| 2297 | |
| 2298 | /* restore IP header */ |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2299 | memcpy(eth_payload_data, saved_ip_header, hlen); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2300 | } |
| 2301 | } |
| 2302 | } |
| 2303 | |
| 2304 | /* update tally counter */ |
| 2305 | ++s->tally_counters.TxOk; |
| 2306 | |
| 2307 | DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size)); |
| 2308 | |
bellard | 718da2b | 2006-07-10 21:38:17 +0000 | [diff] [blame] | 2309 | rtl8139_transfer_frame(s, saved_buffer, saved_size, 1); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2310 | |
| 2311 | /* restore card space if there was no recursion and reset offset */ |
| 2312 | if (!s->cplus_txbuffer) |
| 2313 | { |
| 2314 | s->cplus_txbuffer = saved_buffer; |
| 2315 | s->cplus_txbuffer_len = saved_buffer_len; |
| 2316 | s->cplus_txbuffer_offset = 0; |
| 2317 | } |
| 2318 | else |
| 2319 | { |
| 2320 | free(saved_buffer); |
| 2321 | } |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2322 | } |
| 2323 | else |
| 2324 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2325 | DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2326 | } |
| 2327 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2328 | return 1; |
| 2329 | } |
| 2330 | |
| 2331 | static void rtl8139_cplus_transmit(RTL8139State *s) |
| 2332 | { |
| 2333 | int txcount = 0; |
| 2334 | |
| 2335 | while (rtl8139_cplus_transmit_one(s)) |
| 2336 | { |
| 2337 | ++txcount; |
| 2338 | } |
| 2339 | |
| 2340 | /* Mark transfer completed */ |
| 2341 | if (!txcount) |
| 2342 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2343 | DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n", |
| 2344 | s->currCPlusTxDesc)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2345 | } |
| 2346 | else |
| 2347 | { |
| 2348 | /* update interrupt status */ |
| 2349 | s->IntrStatus |= TxOK; |
| 2350 | rtl8139_update_irq(s); |
| 2351 | } |
| 2352 | } |
| 2353 | |
| 2354 | static void rtl8139_transmit(RTL8139State *s) |
| 2355 | { |
| 2356 | int descriptor = s->currTxDesc, txcount = 0; |
| 2357 | |
| 2358 | /*while*/ |
| 2359 | if (rtl8139_transmit_one(s, descriptor)) |
| 2360 | { |
| 2361 | ++s->currTxDesc; |
| 2362 | s->currTxDesc %= 4; |
| 2363 | ++txcount; |
| 2364 | } |
| 2365 | |
| 2366 | /* Mark transfer completed */ |
| 2367 | if (!txcount) |
| 2368 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2369 | DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2370 | } |
| 2371 | } |
| 2372 | |
| 2373 | static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) |
| 2374 | { |
| 2375 | |
| 2376 | int descriptor = txRegOffset/4; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2377 | |
| 2378 | /* handle C+ transmit mode register configuration */ |
| 2379 | |
aliguori | 2c3891a | 2009-01-13 15:20:14 +0000 | [diff] [blame] | 2380 | if (s->cplus_enabled) |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2381 | { |
| 2382 | DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor)); |
| 2383 | |
| 2384 | /* handle Dump Tally Counters command */ |
| 2385 | s->TxStatus[descriptor] = val; |
| 2386 | |
| 2387 | if (descriptor == 0 && (val & 0x8)) |
| 2388 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2389 | target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2390 | |
| 2391 | /* dump tally counters to specified memory location */ |
| 2392 | RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters); |
| 2393 | |
| 2394 | /* mark dump completed */ |
| 2395 | s->TxStatus[0] &= ~0x8; |
| 2396 | } |
| 2397 | |
| 2398 | return; |
| 2399 | } |
| 2400 | |
| 2401 | DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2402 | |
| 2403 | /* mask only reserved bits */ |
| 2404 | val &= ~0xff00c000; /* these bits are reset on write */ |
| 2405 | val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); |
| 2406 | |
| 2407 | s->TxStatus[descriptor] = val; |
| 2408 | |
| 2409 | /* attempt to start transmission */ |
| 2410 | rtl8139_transmit(s); |
| 2411 | } |
| 2412 | |
| 2413 | static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset) |
| 2414 | { |
| 2415 | uint32_t ret = s->TxStatus[txRegOffset/4]; |
| 2416 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2417 | DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2418 | |
| 2419 | return ret; |
| 2420 | } |
| 2421 | |
| 2422 | static uint16_t rtl8139_TSAD_read(RTL8139State *s) |
| 2423 | { |
| 2424 | uint16_t ret = 0; |
| 2425 | |
| 2426 | /* Simulate TSAD, it is read only anyway */ |
| 2427 | |
| 2428 | ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) |
| 2429 | |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) |
| 2430 | |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) |
| 2431 | |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) |
| 2432 | |
| 2433 | |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) |
| 2434 | |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) |
| 2435 | |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) |
| 2436 | |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2437 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2438 | |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) |
| 2439 | |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) |
| 2440 | |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) |
| 2441 | |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2442 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2443 | |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) |
| 2444 | |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) |
| 2445 | |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) |
| 2446 | |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2447 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2448 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2449 | DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2450 | |
| 2451 | return ret; |
| 2452 | } |
| 2453 | |
| 2454 | static uint16_t rtl8139_CSCR_read(RTL8139State *s) |
| 2455 | { |
| 2456 | uint16_t ret = s->CSCR; |
| 2457 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2458 | DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2459 | |
| 2460 | return ret; |
| 2461 | } |
| 2462 | |
| 2463 | static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) |
| 2464 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2465 | DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2466 | |
ths | 290a093 | 2007-03-19 18:20:28 +0000 | [diff] [blame] | 2467 | s->TxAddr[txAddrOffset/4] = val; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2468 | } |
| 2469 | |
| 2470 | static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) |
| 2471 | { |
ths | 290a093 | 2007-03-19 18:20:28 +0000 | [diff] [blame] | 2472 | uint32_t ret = s->TxAddr[txAddrOffset/4]; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2473 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2474 | DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2475 | |
| 2476 | return ret; |
| 2477 | } |
| 2478 | |
| 2479 | static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) |
| 2480 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2481 | DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2482 | |
| 2483 | /* this value is off by 16 */ |
| 2484 | s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); |
| 2485 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2486 | DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", |
| 2487 | s->RxBufferSize, s->RxBufAddr, s->RxBufPtr)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2488 | } |
| 2489 | |
| 2490 | static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) |
| 2491 | { |
| 2492 | /* this value is off by 16 */ |
| 2493 | uint32_t ret = s->RxBufPtr - 0x10; |
| 2494 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2495 | DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret)); |
| 2496 | |
| 2497 | return ret; |
| 2498 | } |
| 2499 | |
| 2500 | static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s) |
| 2501 | { |
| 2502 | /* this value is NOT off by 16 */ |
| 2503 | uint32_t ret = s->RxBufAddr; |
| 2504 | |
| 2505 | DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2506 | |
| 2507 | return ret; |
| 2508 | } |
| 2509 | |
| 2510 | static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) |
| 2511 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2512 | DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2513 | |
| 2514 | s->RxBuf = val; |
| 2515 | |
| 2516 | /* may need to reset rxring here */ |
| 2517 | } |
| 2518 | |
| 2519 | static uint32_t rtl8139_RxBuf_read(RTL8139State *s) |
| 2520 | { |
| 2521 | uint32_t ret = s->RxBuf; |
| 2522 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2523 | DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2524 | |
| 2525 | return ret; |
| 2526 | } |
| 2527 | |
| 2528 | static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) |
| 2529 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2530 | DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2531 | |
| 2532 | /* mask unwriteable bits */ |
| 2533 | val = SET_MASKED(val, 0x1e00, s->IntrMask); |
| 2534 | |
| 2535 | s->IntrMask = val; |
| 2536 | |
| 2537 | rtl8139_update_irq(s); |
| 2538 | } |
| 2539 | |
| 2540 | static uint32_t rtl8139_IntrMask_read(RTL8139State *s) |
| 2541 | { |
| 2542 | uint32_t ret = s->IntrMask; |
| 2543 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2544 | DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2545 | |
| 2546 | return ret; |
| 2547 | } |
| 2548 | |
| 2549 | static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) |
| 2550 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2551 | DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2552 | |
| 2553 | #if 0 |
| 2554 | |
| 2555 | /* writing to ISR has no effect */ |
| 2556 | |
| 2557 | return; |
| 2558 | |
| 2559 | #else |
| 2560 | uint16_t newStatus = s->IntrStatus & ~val; |
| 2561 | |
| 2562 | /* mask unwriteable bits */ |
| 2563 | newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); |
| 2564 | |
| 2565 | /* writing 1 to interrupt status register bit clears it */ |
| 2566 | s->IntrStatus = 0; |
| 2567 | rtl8139_update_irq(s); |
| 2568 | |
| 2569 | s->IntrStatus = newStatus; |
| 2570 | rtl8139_update_irq(s); |
| 2571 | #endif |
| 2572 | } |
| 2573 | |
| 2574 | static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) |
| 2575 | { |
| 2576 | uint32_t ret = s->IntrStatus; |
| 2577 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2578 | DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2579 | |
| 2580 | #if 0 |
| 2581 | |
| 2582 | /* reading ISR clears all interrupts */ |
| 2583 | s->IntrStatus = 0; |
| 2584 | |
| 2585 | rtl8139_update_irq(s); |
| 2586 | |
| 2587 | #endif |
| 2588 | |
| 2589 | return ret; |
| 2590 | } |
| 2591 | |
| 2592 | static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) |
| 2593 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2594 | DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2595 | |
| 2596 | /* mask unwriteable bits */ |
| 2597 | val = SET_MASKED(val, 0xf000, s->MultiIntr); |
| 2598 | |
| 2599 | s->MultiIntr = val; |
| 2600 | } |
| 2601 | |
| 2602 | static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) |
| 2603 | { |
| 2604 | uint32_t ret = s->MultiIntr; |
| 2605 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2606 | DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2607 | |
| 2608 | return ret; |
| 2609 | } |
| 2610 | |
| 2611 | static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) |
| 2612 | { |
| 2613 | RTL8139State *s = opaque; |
| 2614 | |
| 2615 | addr &= 0xff; |
| 2616 | |
| 2617 | switch (addr) |
| 2618 | { |
| 2619 | case MAC0 ... MAC0+5: |
| 2620 | s->phys[addr - MAC0] = val; |
| 2621 | break; |
| 2622 | case MAC0+6 ... MAC0+7: |
| 2623 | /* reserved */ |
| 2624 | break; |
| 2625 | case MAR0 ... MAR0+7: |
| 2626 | s->mult[addr - MAR0] = val; |
| 2627 | break; |
| 2628 | case ChipCmd: |
| 2629 | rtl8139_ChipCmd_write(s, val); |
| 2630 | break; |
| 2631 | case Cfg9346: |
| 2632 | rtl8139_Cfg9346_write(s, val); |
| 2633 | break; |
| 2634 | case TxConfig: /* windows driver sometimes writes using byte-lenth call */ |
| 2635 | rtl8139_TxConfig_writeb(s, val); |
| 2636 | break; |
| 2637 | case Config0: |
| 2638 | rtl8139_Config0_write(s, val); |
| 2639 | break; |
| 2640 | case Config1: |
| 2641 | rtl8139_Config1_write(s, val); |
| 2642 | break; |
| 2643 | case Config3: |
| 2644 | rtl8139_Config3_write(s, val); |
| 2645 | break; |
| 2646 | case Config4: |
| 2647 | rtl8139_Config4_write(s, val); |
| 2648 | break; |
| 2649 | case Config5: |
| 2650 | rtl8139_Config5_write(s, val); |
| 2651 | break; |
| 2652 | case MediaStatus: |
| 2653 | /* ignore */ |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2654 | DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2655 | break; |
| 2656 | |
| 2657 | case HltClk: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2658 | DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2659 | if (val == 'R') |
| 2660 | { |
| 2661 | s->clock_enabled = 1; |
| 2662 | } |
| 2663 | else if (val == 'H') |
| 2664 | { |
| 2665 | s->clock_enabled = 0; |
| 2666 | } |
| 2667 | break; |
| 2668 | |
| 2669 | case TxThresh: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2670 | DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2671 | s->TxThresh = val; |
| 2672 | break; |
| 2673 | |
| 2674 | case TxPoll: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2675 | DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2676 | if (val & (1 << 7)) |
| 2677 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2678 | DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2679 | //rtl8139_cplus_transmit(s); |
| 2680 | } |
| 2681 | if (val & (1 << 6)) |
| 2682 | { |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2683 | DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2684 | rtl8139_cplus_transmit(s); |
| 2685 | } |
| 2686 | |
| 2687 | break; |
| 2688 | |
| 2689 | default: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2690 | DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2691 | break; |
| 2692 | } |
| 2693 | } |
| 2694 | |
| 2695 | static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) |
| 2696 | { |
| 2697 | RTL8139State *s = opaque; |
| 2698 | |
| 2699 | addr &= 0xfe; |
| 2700 | |
| 2701 | switch (addr) |
| 2702 | { |
| 2703 | case IntrMask: |
| 2704 | rtl8139_IntrMask_write(s, val); |
| 2705 | break; |
| 2706 | |
| 2707 | case IntrStatus: |
| 2708 | rtl8139_IntrStatus_write(s, val); |
| 2709 | break; |
| 2710 | |
| 2711 | case MultiIntr: |
| 2712 | rtl8139_MultiIntr_write(s, val); |
| 2713 | break; |
| 2714 | |
| 2715 | case RxBufPtr: |
| 2716 | rtl8139_RxBufPtr_write(s, val); |
| 2717 | break; |
| 2718 | |
| 2719 | case BasicModeCtrl: |
| 2720 | rtl8139_BasicModeCtrl_write(s, val); |
| 2721 | break; |
| 2722 | case BasicModeStatus: |
| 2723 | rtl8139_BasicModeStatus_write(s, val); |
| 2724 | break; |
| 2725 | case NWayAdvert: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2726 | DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2727 | s->NWayAdvert = val; |
| 2728 | break; |
| 2729 | case NWayLPAR: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2730 | DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2731 | break; |
| 2732 | case NWayExpansion: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2733 | DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2734 | s->NWayExpansion = val; |
| 2735 | break; |
| 2736 | |
| 2737 | case CpCmd: |
| 2738 | rtl8139_CpCmd_write(s, val); |
| 2739 | break; |
| 2740 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2741 | case IntrMitigate: |
| 2742 | rtl8139_IntrMitigate_write(s, val); |
| 2743 | break; |
| 2744 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2745 | default: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2746 | DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2747 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2748 | rtl8139_io_writeb(opaque, addr, val & 0xff); |
| 2749 | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2750 | break; |
| 2751 | } |
| 2752 | } |
| 2753 | |
| 2754 | static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) |
| 2755 | { |
| 2756 | RTL8139State *s = opaque; |
| 2757 | |
| 2758 | addr &= 0xfc; |
| 2759 | |
| 2760 | switch (addr) |
| 2761 | { |
| 2762 | case RxMissed: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2763 | DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n")); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2764 | s->RxMissed = 0; |
| 2765 | break; |
| 2766 | |
| 2767 | case TxConfig: |
| 2768 | rtl8139_TxConfig_write(s, val); |
| 2769 | break; |
| 2770 | |
| 2771 | case RxConfig: |
| 2772 | rtl8139_RxConfig_write(s, val); |
| 2773 | break; |
| 2774 | |
| 2775 | case TxStatus0 ... TxStatus0+4*4-1: |
| 2776 | rtl8139_TxStatus_write(s, addr-TxStatus0, val); |
| 2777 | break; |
| 2778 | |
| 2779 | case TxAddr0 ... TxAddr0+4*4-1: |
| 2780 | rtl8139_TxAddr_write(s, addr-TxAddr0, val); |
| 2781 | break; |
| 2782 | |
| 2783 | case RxBuf: |
| 2784 | rtl8139_RxBuf_write(s, val); |
| 2785 | break; |
| 2786 | |
| 2787 | case RxRingAddrLO: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2788 | DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2789 | s->RxRingAddrLO = val; |
| 2790 | break; |
| 2791 | |
| 2792 | case RxRingAddrHI: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2793 | DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2794 | s->RxRingAddrHI = val; |
| 2795 | break; |
| 2796 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2797 | case Timer: |
| 2798 | DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n")); |
| 2799 | s->TCTR = 0; |
| 2800 | s->TCTR_base = qemu_get_clock(vm_clock); |
| 2801 | break; |
| 2802 | |
| 2803 | case FlashReg: |
| 2804 | DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val)); |
| 2805 | s->TimerInt = val; |
| 2806 | break; |
| 2807 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2808 | default: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2809 | DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2810 | rtl8139_io_writeb(opaque, addr, val & 0xff); |
| 2811 | rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
| 2812 | rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
| 2813 | rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2814 | break; |
| 2815 | } |
| 2816 | } |
| 2817 | |
| 2818 | static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) |
| 2819 | { |
| 2820 | RTL8139State *s = opaque; |
| 2821 | int ret; |
| 2822 | |
| 2823 | addr &= 0xff; |
| 2824 | |
| 2825 | switch (addr) |
| 2826 | { |
| 2827 | case MAC0 ... MAC0+5: |
| 2828 | ret = s->phys[addr - MAC0]; |
| 2829 | break; |
| 2830 | case MAC0+6 ... MAC0+7: |
| 2831 | ret = 0; |
| 2832 | break; |
| 2833 | case MAR0 ... MAR0+7: |
| 2834 | ret = s->mult[addr - MAR0]; |
| 2835 | break; |
| 2836 | case ChipCmd: |
| 2837 | ret = rtl8139_ChipCmd_read(s); |
| 2838 | break; |
| 2839 | case Cfg9346: |
| 2840 | ret = rtl8139_Cfg9346_read(s); |
| 2841 | break; |
| 2842 | case Config0: |
| 2843 | ret = rtl8139_Config0_read(s); |
| 2844 | break; |
| 2845 | case Config1: |
| 2846 | ret = rtl8139_Config1_read(s); |
| 2847 | break; |
| 2848 | case Config3: |
| 2849 | ret = rtl8139_Config3_read(s); |
| 2850 | break; |
| 2851 | case Config4: |
| 2852 | ret = rtl8139_Config4_read(s); |
| 2853 | break; |
| 2854 | case Config5: |
| 2855 | ret = rtl8139_Config5_read(s); |
| 2856 | break; |
| 2857 | |
| 2858 | case MediaStatus: |
| 2859 | ret = 0xd0; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2860 | DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2861 | break; |
| 2862 | |
| 2863 | case HltClk: |
| 2864 | ret = s->clock_enabled; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2865 | DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2866 | break; |
| 2867 | |
| 2868 | case PCIRevisionID: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2869 | ret = RTL8139_PCI_REVID; |
| 2870 | DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2871 | break; |
| 2872 | |
| 2873 | case TxThresh: |
| 2874 | ret = s->TxThresh; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2875 | DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2876 | break; |
| 2877 | |
| 2878 | case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ |
| 2879 | ret = s->TxConfig >> 24; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2880 | DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2881 | break; |
| 2882 | |
| 2883 | default: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2884 | DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2885 | ret = 0; |
| 2886 | break; |
| 2887 | } |
| 2888 | |
| 2889 | return ret; |
| 2890 | } |
| 2891 | |
| 2892 | static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) |
| 2893 | { |
| 2894 | RTL8139State *s = opaque; |
| 2895 | uint32_t ret; |
| 2896 | |
| 2897 | addr &= 0xfe; /* mask lower bit */ |
| 2898 | |
| 2899 | switch (addr) |
| 2900 | { |
| 2901 | case IntrMask: |
| 2902 | ret = rtl8139_IntrMask_read(s); |
| 2903 | break; |
| 2904 | |
| 2905 | case IntrStatus: |
| 2906 | ret = rtl8139_IntrStatus_read(s); |
| 2907 | break; |
| 2908 | |
| 2909 | case MultiIntr: |
| 2910 | ret = rtl8139_MultiIntr_read(s); |
| 2911 | break; |
| 2912 | |
| 2913 | case RxBufPtr: |
| 2914 | ret = rtl8139_RxBufPtr_read(s); |
| 2915 | break; |
| 2916 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2917 | case RxBufAddr: |
| 2918 | ret = rtl8139_RxBufAddr_read(s); |
| 2919 | break; |
| 2920 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2921 | case BasicModeCtrl: |
| 2922 | ret = rtl8139_BasicModeCtrl_read(s); |
| 2923 | break; |
| 2924 | case BasicModeStatus: |
| 2925 | ret = rtl8139_BasicModeStatus_read(s); |
| 2926 | break; |
| 2927 | case NWayAdvert: |
| 2928 | ret = s->NWayAdvert; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2929 | DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2930 | break; |
| 2931 | case NWayLPAR: |
| 2932 | ret = s->NWayLPAR; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2933 | DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2934 | break; |
| 2935 | case NWayExpansion: |
| 2936 | ret = s->NWayExpansion; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2937 | DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2938 | break; |
| 2939 | |
| 2940 | case CpCmd: |
| 2941 | ret = rtl8139_CpCmd_read(s); |
| 2942 | break; |
| 2943 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2944 | case IntrMitigate: |
| 2945 | ret = rtl8139_IntrMitigate_read(s); |
| 2946 | break; |
| 2947 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2948 | case TxSummary: |
| 2949 | ret = rtl8139_TSAD_read(s); |
| 2950 | break; |
| 2951 | |
| 2952 | case CSCR: |
| 2953 | ret = rtl8139_CSCR_read(s); |
| 2954 | break; |
| 2955 | |
| 2956 | default: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2957 | DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2958 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2959 | ret = rtl8139_io_readb(opaque, addr); |
| 2960 | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2961 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2962 | DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2963 | break; |
| 2964 | } |
| 2965 | |
| 2966 | return ret; |
| 2967 | } |
| 2968 | |
| 2969 | static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) |
| 2970 | { |
| 2971 | RTL8139State *s = opaque; |
| 2972 | uint32_t ret; |
| 2973 | |
| 2974 | addr &= 0xfc; /* also mask low 2 bits */ |
| 2975 | |
| 2976 | switch (addr) |
| 2977 | { |
| 2978 | case RxMissed: |
| 2979 | ret = s->RxMissed; |
| 2980 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 2981 | DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 2982 | break; |
| 2983 | |
| 2984 | case TxConfig: |
| 2985 | ret = rtl8139_TxConfig_read(s); |
| 2986 | break; |
| 2987 | |
| 2988 | case RxConfig: |
| 2989 | ret = rtl8139_RxConfig_read(s); |
| 2990 | break; |
| 2991 | |
| 2992 | case TxStatus0 ... TxStatus0+4*4-1: |
| 2993 | ret = rtl8139_TxStatus_read(s, addr-TxStatus0); |
| 2994 | break; |
| 2995 | |
| 2996 | case TxAddr0 ... TxAddr0+4*4-1: |
| 2997 | ret = rtl8139_TxAddr_read(s, addr-TxAddr0); |
| 2998 | break; |
| 2999 | |
| 3000 | case RxBuf: |
| 3001 | ret = rtl8139_RxBuf_read(s); |
| 3002 | break; |
| 3003 | |
| 3004 | case RxRingAddrLO: |
| 3005 | ret = s->RxRingAddrLO; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3006 | DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3007 | break; |
| 3008 | |
| 3009 | case RxRingAddrHI: |
| 3010 | ret = s->RxRingAddrHI; |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3011 | DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret)); |
| 3012 | break; |
| 3013 | |
| 3014 | case Timer: |
| 3015 | ret = s->TCTR; |
| 3016 | DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret)); |
| 3017 | break; |
| 3018 | |
| 3019 | case FlashReg: |
| 3020 | ret = s->TimerInt; |
| 3021 | DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3022 | break; |
| 3023 | |
| 3024 | default: |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3025 | DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3026 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3027 | ret = rtl8139_io_readb(opaque, addr); |
| 3028 | ret |= rtl8139_io_readb(opaque, addr + 1) << 8; |
| 3029 | ret |= rtl8139_io_readb(opaque, addr + 2) << 16; |
| 3030 | ret |= rtl8139_io_readb(opaque, addr + 3) << 24; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3031 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3032 | DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret)); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3033 | break; |
| 3034 | } |
| 3035 | |
| 3036 | return ret; |
| 3037 | } |
| 3038 | |
| 3039 | /* */ |
| 3040 | |
| 3041 | static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
| 3042 | { |
| 3043 | rtl8139_io_writeb(opaque, addr & 0xFF, val); |
| 3044 | } |
| 3045 | |
| 3046 | static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
| 3047 | { |
| 3048 | rtl8139_io_writew(opaque, addr & 0xFF, val); |
| 3049 | } |
| 3050 | |
| 3051 | static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
| 3052 | { |
| 3053 | rtl8139_io_writel(opaque, addr & 0xFF, val); |
| 3054 | } |
| 3055 | |
| 3056 | static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr) |
| 3057 | { |
| 3058 | return rtl8139_io_readb(opaque, addr & 0xFF); |
| 3059 | } |
| 3060 | |
| 3061 | static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr) |
| 3062 | { |
| 3063 | return rtl8139_io_readw(opaque, addr & 0xFF); |
| 3064 | } |
| 3065 | |
| 3066 | static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr) |
| 3067 | { |
| 3068 | return rtl8139_io_readl(opaque, addr & 0xFF); |
| 3069 | } |
| 3070 | |
| 3071 | /* */ |
| 3072 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3073 | static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3074 | { |
| 3075 | rtl8139_io_writeb(opaque, addr & 0xFF, val); |
| 3076 | } |
| 3077 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3078 | static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3079 | { |
aurel32 | 5fedc61 | 2008-03-13 19:17:40 +0000 | [diff] [blame] | 3080 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3081 | val = bswap16(val); |
| 3082 | #endif |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3083 | rtl8139_io_writew(opaque, addr & 0xFF, val); |
| 3084 | } |
| 3085 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3086 | static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3087 | { |
aurel32 | 5fedc61 | 2008-03-13 19:17:40 +0000 | [diff] [blame] | 3088 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3089 | val = bswap32(val); |
| 3090 | #endif |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3091 | rtl8139_io_writel(opaque, addr & 0xFF, val); |
| 3092 | } |
| 3093 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3094 | static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3095 | { |
| 3096 | return rtl8139_io_readb(opaque, addr & 0xFF); |
| 3097 | } |
| 3098 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3099 | static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3100 | { |
aurel32 | 5fedc61 | 2008-03-13 19:17:40 +0000 | [diff] [blame] | 3101 | uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF); |
| 3102 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3103 | val = bswap16(val); |
| 3104 | #endif |
| 3105 | return val; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3106 | } |
| 3107 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 3108 | static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3109 | { |
aurel32 | 5fedc61 | 2008-03-13 19:17:40 +0000 | [diff] [blame] | 3110 | uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF); |
| 3111 | #ifdef TARGET_WORDS_BIGENDIAN |
| 3112 | val = bswap32(val); |
| 3113 | #endif |
| 3114 | return val; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3115 | } |
| 3116 | |
| 3117 | /* */ |
| 3118 | |
| 3119 | static void rtl8139_save(QEMUFile* f,void* opaque) |
| 3120 | { |
Juan Quintela | 6597ebb | 2009-08-24 18:42:40 +0200 | [diff] [blame] | 3121 | RTL8139State* s = opaque; |
ths | 60fe76f | 2007-12-16 03:02:09 +0000 | [diff] [blame] | 3122 | unsigned int i; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3123 | |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 3124 | pci_device_save(&s->dev, f); |
bellard | 1941d19 | 2006-08-17 10:46:34 +0000 | [diff] [blame] | 3125 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3126 | qemu_put_buffer(f, s->phys, 6); |
| 3127 | qemu_put_buffer(f, s->mult, 8); |
| 3128 | |
| 3129 | for (i=0; i<4; ++i) |
| 3130 | { |
| 3131 | qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */ |
| 3132 | } |
| 3133 | for (i=0; i<4; ++i) |
| 3134 | { |
| 3135 | qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */ |
| 3136 | } |
| 3137 | |
| 3138 | qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */ |
| 3139 | qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */ |
| 3140 | qemu_put_be32s(f, &s->RxBufPtr); |
| 3141 | qemu_put_be32s(f, &s->RxBufAddr); |
| 3142 | |
| 3143 | qemu_put_be16s(f, &s->IntrStatus); |
| 3144 | qemu_put_be16s(f, &s->IntrMask); |
| 3145 | |
| 3146 | qemu_put_be32s(f, &s->TxConfig); |
| 3147 | qemu_put_be32s(f, &s->RxConfig); |
| 3148 | qemu_put_be32s(f, &s->RxMissed); |
| 3149 | qemu_put_be16s(f, &s->CSCR); |
| 3150 | |
| 3151 | qemu_put_8s(f, &s->Cfg9346); |
| 3152 | qemu_put_8s(f, &s->Config0); |
| 3153 | qemu_put_8s(f, &s->Config1); |
| 3154 | qemu_put_8s(f, &s->Config3); |
| 3155 | qemu_put_8s(f, &s->Config4); |
| 3156 | qemu_put_8s(f, &s->Config5); |
| 3157 | |
| 3158 | qemu_put_8s(f, &s->clock_enabled); |
| 3159 | qemu_put_8s(f, &s->bChipCmdState); |
| 3160 | |
| 3161 | qemu_put_be16s(f, &s->MultiIntr); |
| 3162 | |
| 3163 | qemu_put_be16s(f, &s->BasicModeCtrl); |
| 3164 | qemu_put_be16s(f, &s->BasicModeStatus); |
| 3165 | qemu_put_be16s(f, &s->NWayAdvert); |
| 3166 | qemu_put_be16s(f, &s->NWayLPAR); |
| 3167 | qemu_put_be16s(f, &s->NWayExpansion); |
| 3168 | |
| 3169 | qemu_put_be16s(f, &s->CpCmd); |
| 3170 | qemu_put_8s(f, &s->TxThresh); |
| 3171 | |
pbrook | 80a34d6 | 2007-04-07 01:41:49 +0000 | [diff] [blame] | 3172 | i = 0; |
| 3173 | qemu_put_be32s(f, &i); /* unused. */ |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3174 | qemu_put_buffer(f, s->macaddr, 6); |
ths | bee8d68 | 2007-12-16 23:41:11 +0000 | [diff] [blame] | 3175 | qemu_put_be32(f, s->rtl8139_mmio_io_addr); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3176 | |
| 3177 | qemu_put_be32s(f, &s->currTxDesc); |
| 3178 | qemu_put_be32s(f, &s->currCPlusRxDesc); |
| 3179 | qemu_put_be32s(f, &s->currCPlusTxDesc); |
| 3180 | qemu_put_be32s(f, &s->RxRingAddrLO); |
| 3181 | qemu_put_be32s(f, &s->RxRingAddrHI); |
| 3182 | |
| 3183 | for (i=0; i<EEPROM_9346_SIZE; ++i) |
| 3184 | { |
| 3185 | qemu_put_be16s(f, &s->eeprom.contents[i]); |
| 3186 | } |
ths | bee8d68 | 2007-12-16 23:41:11 +0000 | [diff] [blame] | 3187 | qemu_put_be32(f, s->eeprom.mode); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3188 | qemu_put_be32s(f, &s->eeprom.tick); |
| 3189 | qemu_put_8s(f, &s->eeprom.address); |
| 3190 | qemu_put_be16s(f, &s->eeprom.input); |
| 3191 | qemu_put_be16s(f, &s->eeprom.output); |
| 3192 | |
| 3193 | qemu_put_8s(f, &s->eeprom.eecs); |
| 3194 | qemu_put_8s(f, &s->eeprom.eesk); |
| 3195 | qemu_put_8s(f, &s->eeprom.eedi); |
| 3196 | qemu_put_8s(f, &s->eeprom.eedo); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3197 | |
| 3198 | qemu_put_be32s(f, &s->TCTR); |
| 3199 | qemu_put_be32s(f, &s->TimerInt); |
ths | bee8d68 | 2007-12-16 23:41:11 +0000 | [diff] [blame] | 3200 | qemu_put_be64(f, s->TCTR_base); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3201 | |
| 3202 | RTL8139TallyCounters_save(f, &s->tally_counters); |
aliguori | 2c3891a | 2009-01-13 15:20:14 +0000 | [diff] [blame] | 3203 | |
| 3204 | qemu_put_be32s(f, &s->cplus_enabled); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3205 | } |
| 3206 | |
| 3207 | static int rtl8139_load(QEMUFile* f,void* opaque,int version_id) |
| 3208 | { |
Juan Quintela | 6597ebb | 2009-08-24 18:42:40 +0200 | [diff] [blame] | 3209 | RTL8139State* s = opaque; |
ths | 60fe76f | 2007-12-16 03:02:09 +0000 | [diff] [blame] | 3210 | unsigned int i; |
| 3211 | int ret; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3212 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3213 | /* just 2 versions for now */ |
aliguori | 2c3891a | 2009-01-13 15:20:14 +0000 | [diff] [blame] | 3214 | if (version_id > 4) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3215 | return -EINVAL; |
| 3216 | |
bellard | 1941d19 | 2006-08-17 10:46:34 +0000 | [diff] [blame] | 3217 | if (version_id >= 3) { |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 3218 | ret = pci_device_load(&s->dev, f); |
bellard | 1941d19 | 2006-08-17 10:46:34 +0000 | [diff] [blame] | 3219 | if (ret < 0) |
| 3220 | return ret; |
| 3221 | } |
| 3222 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3223 | /* saved since version 1 */ |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3224 | qemu_get_buffer(f, s->phys, 6); |
| 3225 | qemu_get_buffer(f, s->mult, 8); |
| 3226 | |
| 3227 | for (i=0; i<4; ++i) |
| 3228 | { |
| 3229 | qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */ |
| 3230 | } |
| 3231 | for (i=0; i<4; ++i) |
| 3232 | { |
| 3233 | qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */ |
| 3234 | } |
| 3235 | |
| 3236 | qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */ |
| 3237 | qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */ |
| 3238 | qemu_get_be32s(f, &s->RxBufPtr); |
| 3239 | qemu_get_be32s(f, &s->RxBufAddr); |
| 3240 | |
| 3241 | qemu_get_be16s(f, &s->IntrStatus); |
| 3242 | qemu_get_be16s(f, &s->IntrMask); |
| 3243 | |
| 3244 | qemu_get_be32s(f, &s->TxConfig); |
| 3245 | qemu_get_be32s(f, &s->RxConfig); |
| 3246 | qemu_get_be32s(f, &s->RxMissed); |
| 3247 | qemu_get_be16s(f, &s->CSCR); |
| 3248 | |
| 3249 | qemu_get_8s(f, &s->Cfg9346); |
| 3250 | qemu_get_8s(f, &s->Config0); |
| 3251 | qemu_get_8s(f, &s->Config1); |
| 3252 | qemu_get_8s(f, &s->Config3); |
| 3253 | qemu_get_8s(f, &s->Config4); |
| 3254 | qemu_get_8s(f, &s->Config5); |
| 3255 | |
| 3256 | qemu_get_8s(f, &s->clock_enabled); |
| 3257 | qemu_get_8s(f, &s->bChipCmdState); |
| 3258 | |
| 3259 | qemu_get_be16s(f, &s->MultiIntr); |
| 3260 | |
| 3261 | qemu_get_be16s(f, &s->BasicModeCtrl); |
| 3262 | qemu_get_be16s(f, &s->BasicModeStatus); |
| 3263 | qemu_get_be16s(f, &s->NWayAdvert); |
| 3264 | qemu_get_be16s(f, &s->NWayLPAR); |
| 3265 | qemu_get_be16s(f, &s->NWayExpansion); |
| 3266 | |
| 3267 | qemu_get_be16s(f, &s->CpCmd); |
| 3268 | qemu_get_8s(f, &s->TxThresh); |
| 3269 | |
pbrook | 80a34d6 | 2007-04-07 01:41:49 +0000 | [diff] [blame] | 3270 | qemu_get_be32s(f, &i); /* unused. */ |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3271 | qemu_get_buffer(f, s->macaddr, 6); |
ths | bee8d68 | 2007-12-16 23:41:11 +0000 | [diff] [blame] | 3272 | s->rtl8139_mmio_io_addr=qemu_get_be32(f); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3273 | |
| 3274 | qemu_get_be32s(f, &s->currTxDesc); |
| 3275 | qemu_get_be32s(f, &s->currCPlusRxDesc); |
| 3276 | qemu_get_be32s(f, &s->currCPlusTxDesc); |
| 3277 | qemu_get_be32s(f, &s->RxRingAddrLO); |
| 3278 | qemu_get_be32s(f, &s->RxRingAddrHI); |
| 3279 | |
| 3280 | for (i=0; i<EEPROM_9346_SIZE; ++i) |
| 3281 | { |
| 3282 | qemu_get_be16s(f, &s->eeprom.contents[i]); |
| 3283 | } |
ths | bee8d68 | 2007-12-16 23:41:11 +0000 | [diff] [blame] | 3284 | s->eeprom.mode=qemu_get_be32(f); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3285 | qemu_get_be32s(f, &s->eeprom.tick); |
| 3286 | qemu_get_8s(f, &s->eeprom.address); |
| 3287 | qemu_get_be16s(f, &s->eeprom.input); |
| 3288 | qemu_get_be16s(f, &s->eeprom.output); |
| 3289 | |
| 3290 | qemu_get_8s(f, &s->eeprom.eecs); |
| 3291 | qemu_get_8s(f, &s->eeprom.eesk); |
| 3292 | qemu_get_8s(f, &s->eeprom.eedi); |
| 3293 | qemu_get_8s(f, &s->eeprom.eedo); |
| 3294 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3295 | /* saved since version 2 */ |
| 3296 | if (version_id >= 2) |
| 3297 | { |
| 3298 | qemu_get_be32s(f, &s->TCTR); |
| 3299 | qemu_get_be32s(f, &s->TimerInt); |
ths | bee8d68 | 2007-12-16 23:41:11 +0000 | [diff] [blame] | 3300 | s->TCTR_base=qemu_get_be64(f); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3301 | |
| 3302 | RTL8139TallyCounters_load(f, &s->tally_counters); |
| 3303 | } |
| 3304 | else |
| 3305 | { |
| 3306 | /* not saved, use default */ |
| 3307 | s->TCTR = 0; |
| 3308 | s->TimerInt = 0; |
| 3309 | s->TCTR_base = 0; |
| 3310 | |
| 3311 | RTL8139TallyCounters_clear(&s->tally_counters); |
| 3312 | } |
| 3313 | |
aliguori | 2c3891a | 2009-01-13 15:20:14 +0000 | [diff] [blame] | 3314 | if (version_id >= 4) { |
| 3315 | qemu_get_be32s(f, &s->cplus_enabled); |
| 3316 | } else { |
| 3317 | s->cplus_enabled = s->CpCmd != 0; |
| 3318 | } |
| 3319 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3320 | return 0; |
| 3321 | } |
| 3322 | |
| 3323 | /***********************************************************/ |
| 3324 | /* PCI RTL8139 definitions */ |
| 3325 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3326 | static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num, |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3327 | uint32_t addr, uint32_t size, int type) |
| 3328 | { |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 3329 | RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3330 | |
| 3331 | cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr); |
| 3332 | } |
| 3333 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3334 | static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num, |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3335 | uint32_t addr, uint32_t size, int type) |
| 3336 | { |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 3337 | RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3338 | |
| 3339 | register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s); |
| 3340 | register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s); |
| 3341 | |
| 3342 | register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s); |
| 3343 | register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s); |
| 3344 | |
| 3345 | register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s); |
| 3346 | register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s); |
| 3347 | } |
| 3348 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3349 | static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = { |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3350 | rtl8139_mmio_readb, |
| 3351 | rtl8139_mmio_readw, |
| 3352 | rtl8139_mmio_readl, |
| 3353 | }; |
| 3354 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 3355 | static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = { |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3356 | rtl8139_mmio_writeb, |
| 3357 | rtl8139_mmio_writew, |
| 3358 | rtl8139_mmio_writel, |
| 3359 | }; |
| 3360 | |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3361 | static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time) |
| 3362 | { |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3363 | int64_t next_time = current_time + |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 3364 | muldiv64(1, get_ticks_per_sec(), PCI_FREQUENCY); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3365 | if (next_time <= current_time) |
| 3366 | next_time = current_time + 1; |
| 3367 | return next_time; |
| 3368 | } |
| 3369 | |
blueswir1 | eb38c52 | 2008-09-06 17:47:39 +0000 | [diff] [blame] | 3370 | #ifdef RTL8139_ONBOARD_TIMER |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3371 | static void rtl8139_timer(void *opaque) |
| 3372 | { |
| 3373 | RTL8139State *s = opaque; |
| 3374 | |
| 3375 | int is_timeout = 0; |
| 3376 | |
| 3377 | int64_t curr_time; |
| 3378 | uint32_t curr_tick; |
| 3379 | |
| 3380 | if (!s->clock_enabled) |
| 3381 | { |
| 3382 | DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n")); |
| 3383 | return; |
| 3384 | } |
| 3385 | |
| 3386 | curr_time = qemu_get_clock(vm_clock); |
| 3387 | |
Juan Quintela | 6ee093c | 2009-09-10 03:04:26 +0200 | [diff] [blame] | 3388 | curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, |
| 3389 | get_ticks_per_sec()); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3390 | |
| 3391 | if (s->TimerInt && curr_tick >= s->TimerInt) |
| 3392 | { |
| 3393 | if (s->TCTR < s->TimerInt || curr_tick < s->TCTR) |
| 3394 | { |
| 3395 | is_timeout = 1; |
| 3396 | } |
| 3397 | } |
| 3398 | |
| 3399 | s->TCTR = curr_tick; |
| 3400 | |
| 3401 | // DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR)); |
| 3402 | |
| 3403 | if (is_timeout) |
| 3404 | { |
| 3405 | DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR)); |
| 3406 | s->IntrStatus |= PCSTimeout; |
| 3407 | rtl8139_update_irq(s); |
| 3408 | } |
| 3409 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3410 | qemu_mod_timer(s->timer, |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3411 | rtl8139_get_next_tctr_time(s,curr_time)); |
| 3412 | } |
| 3413 | #endif /* RTL8139_ONBOARD_TIMER */ |
| 3414 | |
aliguori | b946a15 | 2009-04-17 17:11:08 +0000 | [diff] [blame] | 3415 | static void rtl8139_cleanup(VLANClientState *vc) |
| 3416 | { |
| 3417 | RTL8139State *s = vc->opaque; |
| 3418 | |
| 3419 | if (s->cplus_txbuffer) { |
| 3420 | qemu_free(s->cplus_txbuffer); |
| 3421 | s->cplus_txbuffer = NULL; |
| 3422 | } |
| 3423 | |
| 3424 | #ifdef RTL8139_ONBOARD_TIMER |
| 3425 | qemu_del_timer(s->timer); |
| 3426 | qemu_free_timer(s->timer); |
| 3427 | #endif |
| 3428 | |
| 3429 | unregister_savevm("rtl8139", s); |
| 3430 | } |
| 3431 | |
| 3432 | static int pci_rtl8139_uninit(PCIDevice *dev) |
| 3433 | { |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 3434 | RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev); |
aliguori | b946a15 | 2009-04-17 17:11:08 +0000 | [diff] [blame] | 3435 | |
| 3436 | cpu_unregister_io_memory(s->rtl8139_mmio_io_addr); |
| 3437 | |
| 3438 | return 0; |
| 3439 | } |
| 3440 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 3441 | static int pci_rtl8139_init(PCIDevice *dev) |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3442 | { |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 3443 | RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3444 | uint8_t *pci_conf; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3445 | |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 3446 | pci_conf = s->dev.config; |
aliguori | deb5439 | 2009-01-26 15:37:35 +0000 | [diff] [blame] | 3447 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); |
| 3448 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3449 | pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */ |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3450 | pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */ |
blueswir1 | 173a543 | 2009-02-01 19:26:20 +0000 | [diff] [blame] | 3451 | pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
Isaku Yamahata | 6407f37 | 2009-05-03 19:03:00 +0000 | [diff] [blame] | 3452 | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */ |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3453 | pci_conf[0x3d] = 1; /* interrupt pin 0 */ |
| 3454 | pci_conf[0x34] = 0xdc; |
| 3455 | |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3456 | /* I/O handler for memory-mapped I/O */ |
| 3457 | s->rtl8139_mmio_io_addr = |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 3458 | cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3459 | |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 3460 | pci_register_bar(&s->dev, 0, 0x100, |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3461 | PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map); |
| 3462 | |
Juan Quintela | efd6dd4 | 2009-08-24 18:42:39 +0200 | [diff] [blame] | 3463 | pci_register_bar(&s->dev, 1, 0x100, |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3464 | PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map); |
| 3465 | |
Paul Brook | 9d07d75 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 3466 | qdev_get_macaddr(&dev->qdev, s->macaddr); |
Michael S. Tsirkin | 7f23f81 | 2009-09-16 13:40:27 +0300 | [diff] [blame] | 3467 | rtl8139_reset(&s->dev.qdev); |
Paul Brook | 9d07d75 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 3468 | s->vc = qdev_get_vlan_client(&dev->qdev, |
Mark McLoughlin | 463af53 | 2009-05-18 12:55:27 +0100 | [diff] [blame] | 3469 | rtl8139_can_receive, rtl8139_receive, NULL, |
aliguori | b946a15 | 2009-04-17 17:11:08 +0000 | [diff] [blame] | 3470 | rtl8139_cleanup, s); |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3471 | |
aliguori | 7cb7434b | 2009-01-07 17:46:21 +0000 | [diff] [blame] | 3472 | qemu_format_nic_info_str(s->vc, s->macaddr); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3473 | |
| 3474 | s->cplus_txbuffer = NULL; |
| 3475 | s->cplus_txbuffer_len = 0; |
| 3476 | s->cplus_txbuffer_offset = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 3477 | |
aliguori | 2c3891a | 2009-01-13 15:20:14 +0000 | [diff] [blame] | 3478 | register_savevm("rtl8139", -1, 4, rtl8139_save, rtl8139_load, s); |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3479 | |
blueswir1 | eb38c52 | 2008-09-06 17:47:39 +0000 | [diff] [blame] | 3480 | #ifdef RTL8139_ONBOARD_TIMER |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3481 | s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s); |
| 3482 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3483 | qemu_mod_timer(s->timer, |
bellard | 6cadb32 | 2006-07-04 10:08:36 +0000 | [diff] [blame] | 3484 | rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock))); |
| 3485 | #endif /* RTL8139_ONBOARD_TIMER */ |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 3486 | return 0; |
pbrook | a41b2ff | 2006-02-05 04:14:41 +0000 | [diff] [blame] | 3487 | } |
Paul Brook | 9d07d75 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 3488 | |
Gerd Hoffmann | 0aab0d3 | 2009-06-30 14:12:07 +0200 | [diff] [blame] | 3489 | static PCIDeviceInfo rtl8139_info = { |
Gerd Hoffmann | f82de8f | 2009-09-01 09:56:13 +0200 | [diff] [blame] | 3490 | .qdev.name = "rtl8139", |
| 3491 | .qdev.size = sizeof(RTL8139State), |
| 3492 | .qdev.reset = rtl8139_reset, |
| 3493 | .init = pci_rtl8139_init, |
Gerd Hoffmann | e3936fa | 2009-09-25 21:42:38 +0200 | [diff] [blame] | 3494 | .exit = pci_rtl8139_uninit, |
Gerd Hoffmann | 0aab0d3 | 2009-06-30 14:12:07 +0200 | [diff] [blame] | 3495 | }; |
| 3496 | |
Paul Brook | 9d07d75 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 3497 | static void rtl8139_register_devices(void) |
| 3498 | { |
Gerd Hoffmann | 0aab0d3 | 2009-06-30 14:12:07 +0200 | [diff] [blame] | 3499 | pci_qdev_register(&rtl8139_info); |
Paul Brook | 9d07d75 | 2009-05-14 22:35:07 +0100 | [diff] [blame] | 3500 | } |
| 3501 | |
| 3502 | device_init(rtl8139_register_devices) |