ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1 | /* |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 2 | * Arm PrimeCell PL080/PL081 DMA controller |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2006 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
| 7 | * This code is licenced under the GPL. |
| 8 | */ |
| 9 | |
Paul Brook | b4496b1 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 10 | #include "sysbus.h" |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 11 | |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 12 | #define PL080_MAX_CHANNELS 8 |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 13 | #define PL080_CONF_E 0x1 |
| 14 | #define PL080_CONF_M1 0x2 |
| 15 | #define PL080_CONF_M2 0x4 |
| 16 | |
| 17 | #define PL080_CCONF_H 0x40000 |
| 18 | #define PL080_CCONF_A 0x20000 |
| 19 | #define PL080_CCONF_L 0x10000 |
| 20 | #define PL080_CCONF_ITC 0x08000 |
| 21 | #define PL080_CCONF_IE 0x04000 |
| 22 | #define PL080_CCONF_E 0x00001 |
| 23 | |
| 24 | #define PL080_CCTRL_I 0x80000000 |
| 25 | #define PL080_CCTRL_DI 0x08000000 |
| 26 | #define PL080_CCTRL_SI 0x04000000 |
| 27 | #define PL080_CCTRL_D 0x02000000 |
| 28 | #define PL080_CCTRL_S 0x01000000 |
| 29 | |
| 30 | typedef struct { |
| 31 | uint32_t src; |
| 32 | uint32_t dest; |
| 33 | uint32_t lli; |
| 34 | uint32_t ctrl; |
| 35 | uint32_t conf; |
| 36 | } pl080_channel; |
| 37 | |
| 38 | typedef struct { |
Paul Brook | b4496b1 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 39 | SysBusDevice busdev; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 40 | uint8_t tc_int; |
| 41 | uint8_t tc_mask; |
| 42 | uint8_t err_int; |
| 43 | uint8_t err_mask; |
| 44 | uint32_t conf; |
| 45 | uint32_t sync; |
| 46 | uint32_t req_single; |
| 47 | uint32_t req_burst; |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 48 | pl080_channel chan[PL080_MAX_CHANNELS]; |
| 49 | int nchannels; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 50 | /* Flag to avoid recursive DMA invocations. */ |
| 51 | int running; |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 52 | qemu_irq irq; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 53 | } pl080_state; |
| 54 | |
| 55 | static const unsigned char pl080_id[] = |
| 56 | { 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
| 57 | |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 58 | static const unsigned char pl081_id[] = |
| 59 | { 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 }; |
| 60 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 61 | static void pl080_update(pl080_state *s) |
| 62 | { |
| 63 | if ((s->tc_int & s->tc_mask) |
| 64 | || (s->err_int & s->err_mask)) |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 65 | qemu_irq_raise(s->irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 66 | else |
pbrook | d537cf6 | 2007-04-07 18:14:41 +0000 | [diff] [blame] | 67 | qemu_irq_lower(s->irq); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 68 | } |
| 69 | |
| 70 | static void pl080_run(pl080_state *s) |
| 71 | { |
| 72 | int c; |
| 73 | int flow; |
| 74 | pl080_channel *ch; |
| 75 | int swidth; |
| 76 | int dwidth; |
| 77 | int xsize; |
| 78 | int n; |
| 79 | int src_id; |
| 80 | int dest_id; |
| 81 | int size; |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 82 | uint8_t buff[4]; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 83 | uint32_t req; |
| 84 | |
| 85 | s->tc_mask = 0; |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 86 | for (c = 0; c < s->nchannels; c++) { |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 87 | if (s->chan[c].conf & PL080_CCONF_ITC) |
| 88 | s->tc_mask |= 1 << c; |
| 89 | if (s->chan[c].conf & PL080_CCONF_IE) |
| 90 | s->err_mask |= 1 << c; |
| 91 | } |
| 92 | |
| 93 | if ((s->conf & PL080_CONF_E) == 0) |
| 94 | return; |
| 95 | |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 96 | hw_error("DMA active\n"); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 97 | /* If we are already in the middle of a DMA operation then indicate that |
| 98 | there may be new DMA requests and return immediately. */ |
| 99 | if (s->running) { |
| 100 | s->running++; |
| 101 | return; |
| 102 | } |
| 103 | s->running = 1; |
| 104 | while (s->running) { |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 105 | for (c = 0; c < s->nchannels; c++) { |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 106 | ch = &s->chan[c]; |
| 107 | again: |
| 108 | /* Test if thiws channel has any pending DMA requests. */ |
| 109 | if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E)) |
| 110 | != PL080_CCONF_E) |
| 111 | continue; |
| 112 | flow = (ch->conf >> 11) & 7; |
| 113 | if (flow >= 4) { |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 114 | hw_error( |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 115 | "pl080_run: Peripheral flow control not implemented\n"); |
| 116 | } |
| 117 | src_id = (ch->conf >> 1) & 0x1f; |
| 118 | dest_id = (ch->conf >> 6) & 0x1f; |
| 119 | size = ch->ctrl & 0xfff; |
| 120 | req = s->req_single | s->req_burst; |
| 121 | switch (flow) { |
| 122 | case 0: |
| 123 | break; |
| 124 | case 1: |
| 125 | if ((req & (1u << dest_id)) == 0) |
| 126 | size = 0; |
| 127 | break; |
| 128 | case 2: |
| 129 | if ((req & (1u << src_id)) == 0) |
| 130 | size = 0; |
| 131 | break; |
| 132 | case 3: |
| 133 | if ((req & (1u << src_id)) == 0 |
| 134 | || (req & (1u << dest_id)) == 0) |
| 135 | size = 0; |
| 136 | break; |
| 137 | } |
| 138 | if (!size) |
| 139 | continue; |
| 140 | |
| 141 | /* Transfer one element. */ |
| 142 | /* ??? Should transfer multiple elements for a burst request. */ |
| 143 | /* ??? Unclear what the proper behavior is when source and |
| 144 | destination widths are different. */ |
| 145 | swidth = 1 << ((ch->ctrl >> 18) & 7); |
| 146 | dwidth = 1 << ((ch->ctrl >> 21) & 7); |
| 147 | for (n = 0; n < dwidth; n+= swidth) { |
| 148 | cpu_physical_memory_read(ch->src, buff + n, swidth); |
| 149 | if (ch->ctrl & PL080_CCTRL_SI) |
| 150 | ch->src += swidth; |
| 151 | } |
| 152 | xsize = (dwidth < swidth) ? swidth : dwidth; |
| 153 | /* ??? This may pad the value incorrectly for dwidth < 32. */ |
| 154 | for (n = 0; n < xsize; n += dwidth) { |
| 155 | cpu_physical_memory_write(ch->dest + n, buff + n, dwidth); |
| 156 | if (ch->ctrl & PL080_CCTRL_DI) |
| 157 | ch->dest += swidth; |
| 158 | } |
| 159 | |
| 160 | size--; |
| 161 | ch->ctrl = (ch->ctrl & 0xfffff000) | size; |
| 162 | if (size == 0) { |
| 163 | /* Transfer complete. */ |
| 164 | if (ch->lli) { |
| 165 | ch->src = ldl_phys(ch->lli); |
| 166 | ch->dest = ldl_phys(ch->lli + 4); |
| 167 | ch->ctrl = ldl_phys(ch->lli + 12); |
| 168 | ch->lli = ldl_phys(ch->lli + 8); |
| 169 | } else { |
| 170 | ch->conf &= ~PL080_CCONF_E; |
| 171 | } |
| 172 | if (ch->ctrl & PL080_CCTRL_I) { |
| 173 | s->tc_int |= 1 << c; |
| 174 | } |
| 175 | } |
| 176 | goto again; |
| 177 | } |
| 178 | if (--s->running) |
| 179 | s->running = 1; |
| 180 | } |
| 181 | } |
| 182 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 183 | static uint32_t pl080_read(void *opaque, target_phys_addr_t offset) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 184 | { |
| 185 | pl080_state *s = (pl080_state *)opaque; |
| 186 | uint32_t i; |
| 187 | uint32_t mask; |
| 188 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 189 | if (offset >= 0xfe0 && offset < 0x1000) { |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 190 | if (s->nchannels == 8) { |
| 191 | return pl080_id[(offset - 0xfe0) >> 2]; |
| 192 | } else { |
| 193 | return pl081_id[(offset - 0xfe0) >> 2]; |
| 194 | } |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 195 | } |
| 196 | if (offset >= 0x100 && offset < 0x200) { |
| 197 | i = (offset & 0xe0) >> 5; |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 198 | if (i >= s->nchannels) |
| 199 | goto bad_offset; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 200 | switch (offset >> 2) { |
| 201 | case 0: /* SrcAddr */ |
| 202 | return s->chan[i].src; |
| 203 | case 1: /* DestAddr */ |
| 204 | return s->chan[i].dest; |
| 205 | case 2: /* LLI */ |
| 206 | return s->chan[i].lli; |
| 207 | case 3: /* Control */ |
| 208 | return s->chan[i].ctrl; |
| 209 | case 4: /* Configuration */ |
| 210 | return s->chan[i].conf; |
| 211 | default: |
| 212 | goto bad_offset; |
| 213 | } |
| 214 | } |
| 215 | switch (offset >> 2) { |
| 216 | case 0: /* IntStatus */ |
| 217 | return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask); |
| 218 | case 1: /* IntTCStatus */ |
| 219 | return (s->tc_int & s->tc_mask); |
| 220 | case 3: /* IntErrorStatus */ |
| 221 | return (s->err_int & s->err_mask); |
| 222 | case 5: /* RawIntTCStatus */ |
| 223 | return s->tc_int; |
| 224 | case 6: /* RawIntErrorStatus */ |
| 225 | return s->err_int; |
| 226 | case 7: /* EnbldChns */ |
| 227 | mask = 0; |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 228 | for (i = 0; i < s->nchannels; i++) { |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 229 | if (s->chan[i].conf & PL080_CCONF_E) |
| 230 | mask |= 1 << i; |
| 231 | } |
| 232 | return mask; |
| 233 | case 8: /* SoftBReq */ |
| 234 | case 9: /* SoftSReq */ |
| 235 | case 10: /* SoftLBReq */ |
| 236 | case 11: /* SoftLSReq */ |
| 237 | /* ??? Implement these. */ |
| 238 | return 0; |
| 239 | case 12: /* Configuration */ |
| 240 | return s->conf; |
| 241 | case 13: /* Sync */ |
| 242 | return s->sync; |
| 243 | default: |
| 244 | bad_offset: |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 245 | hw_error("pl080_read: Bad offset %x\n", (int)offset); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 246 | return 0; |
| 247 | } |
| 248 | } |
| 249 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 250 | static void pl080_write(void *opaque, target_phys_addr_t offset, |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 251 | uint32_t value) |
| 252 | { |
| 253 | pl080_state *s = (pl080_state *)opaque; |
| 254 | int i; |
| 255 | |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 256 | if (offset >= 0x100 && offset < 0x200) { |
| 257 | i = (offset & 0xe0) >> 5; |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 258 | if (i >= s->nchannels) |
| 259 | goto bad_offset; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 260 | switch (offset >> 2) { |
| 261 | case 0: /* SrcAddr */ |
| 262 | s->chan[i].src = value; |
| 263 | break; |
| 264 | case 1: /* DestAddr */ |
| 265 | s->chan[i].dest = value; |
| 266 | break; |
| 267 | case 2: /* LLI */ |
| 268 | s->chan[i].lli = value; |
| 269 | break; |
| 270 | case 3: /* Control */ |
| 271 | s->chan[i].ctrl = value; |
| 272 | break; |
| 273 | case 4: /* Configuration */ |
| 274 | s->chan[i].conf = value; |
| 275 | pl080_run(s); |
| 276 | break; |
| 277 | } |
| 278 | } |
| 279 | switch (offset >> 2) { |
| 280 | case 2: /* IntTCClear */ |
| 281 | s->tc_int &= ~value; |
| 282 | break; |
| 283 | case 4: /* IntErrorClear */ |
| 284 | s->err_int &= ~value; |
| 285 | break; |
| 286 | case 8: /* SoftBReq */ |
| 287 | case 9: /* SoftSReq */ |
| 288 | case 10: /* SoftLBReq */ |
| 289 | case 11: /* SoftLSReq */ |
| 290 | /* ??? Implement these. */ |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 291 | hw_error("pl080_write: Soft DMA not implemented\n"); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 292 | break; |
| 293 | case 12: /* Configuration */ |
| 294 | s->conf = value; |
| 295 | if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) { |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 296 | hw_error("pl080_write: Big-endian DMA not implemented\n"); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 297 | } |
| 298 | pl080_run(s); |
| 299 | break; |
| 300 | case 13: /* Sync */ |
| 301 | s->sync = value; |
| 302 | break; |
| 303 | default: |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 304 | bad_offset: |
Paul Brook | 2ac7117 | 2009-05-08 02:35:15 +0100 | [diff] [blame] | 305 | hw_error("pl080_write: Bad offset %x\n", (int)offset); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 306 | } |
| 307 | pl080_update(s); |
| 308 | } |
| 309 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 310 | static CPUReadMemoryFunc * const pl080_readfn[] = { |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 311 | pl080_read, |
| 312 | pl080_read, |
| 313 | pl080_read |
| 314 | }; |
| 315 | |
Blue Swirl | d60efc6 | 2009-08-25 18:29:31 +0000 | [diff] [blame] | 316 | static CPUWriteMemoryFunc * const pl080_writefn[] = { |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 317 | pl080_write, |
| 318 | pl080_write, |
| 319 | pl080_write |
| 320 | }; |
| 321 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 322 | static int pl08x_init(SysBusDevice *dev, int nchannels) |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 323 | { |
| 324 | int iomemtype; |
Paul Brook | b4496b1 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 325 | pl080_state *s = FROM_SYSBUS(pl080_state, dev); |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 326 | |
Avi Kivity | 1eed09c | 2009-06-14 11:38:51 +0300 | [diff] [blame] | 327 | iomemtype = cpu_register_io_memory(pl080_readfn, |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 328 | pl080_writefn, s); |
Paul Brook | b4496b1 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 329 | sysbus_init_mmio(dev, 0x1000, iomemtype); |
| 330 | sysbus_init_irq(dev, &s->irq); |
pbrook | e69954b | 2006-09-23 17:40:58 +0000 | [diff] [blame] | 331 | s->nchannels = nchannels; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 332 | /* ??? Save/restore. */ |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 333 | return 0; |
pbrook | cdbdb64 | 2006-04-09 01:32:52 +0000 | [diff] [blame] | 334 | } |
Paul Brook | b4496b1 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 335 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 336 | static int pl080_init(SysBusDevice *dev) |
Paul Brook | b4496b1 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 337 | { |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 338 | return pl08x_init(dev, 8); |
Paul Brook | b4496b1 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 339 | } |
| 340 | |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 341 | static int pl081_init(SysBusDevice *dev) |
Paul Brook | b4496b1 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 342 | { |
Gerd Hoffmann | 81a322d | 2009-08-14 10:36:05 +0200 | [diff] [blame] | 343 | return pl08x_init(dev, 2); |
Paul Brook | b4496b1 | 2009-05-14 22:35:08 +0100 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | /* The PL080 and PL081 are the same except for the number of channels |
| 347 | they implement (8 and 2 respectively). */ |
| 348 | static void pl080_register_devices(void) |
| 349 | { |
| 350 | sysbus_register_dev("pl080", sizeof(pl080_state), pl080_init); |
| 351 | sysbus_register_dev("pl081", sizeof(pl080_state), pl081_init); |
| 352 | } |
| 353 | |
| 354 | device_init(pl080_register_devices) |