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bellard6af0bf92005-07-02 14:58:51 +00001#if !defined (__QEMU_MIPS_DEFS_H__)
2#define __QEMU_MIPS_DEFS_H__
3
bellard6af0bf92005-07-02 14:58:51 +00004/* If we want to use host float regs... */
5//#define USE_HOST_FLOAT_REGS
6
thse9c71dd2007-12-25 20:46:56 +00007/* Real pages are variable size... */
bellard6af0bf92005-07-02 14:58:51 +00008#define TARGET_PAGE_BITS 12
ths814b9a42006-12-06 17:42:40 +00009#define MIPS_TLB_MAX 128
bellard6af0bf92005-07-02 14:58:51 +000010
thsd26bc212007-11-08 18:05:37 +000011#if defined(TARGET_MIPS64)
thsc570fd12006-12-21 01:19:56 +000012#define TARGET_LONG_BITS 64
Leon Alraee117f522015-04-14 10:09:38 +010013#define TARGET_PHYS_ADDR_SPACE_BITS 48
Yongbok Kim4dc89b72015-06-29 10:11:23 +010014#define TARGET_VIRT_ADDR_SPACE_BITS 48
thsc570fd12006-12-21 01:19:56 +000015#else
16#define TARGET_LONG_BITS 32
Leon Alraee117f522015-04-14 10:09:38 +010017#define TARGET_PHYS_ADDR_SPACE_BITS 40
Aurelien Jarno30724e72010-03-13 01:39:17 +010018#define TARGET_VIRT_ADDR_SPACE_BITS 32
thsc570fd12006-12-21 01:19:56 +000019#endif
20
thse189e742007-09-24 12:48:00 +000021/* Masks used to mark instructions to indicate which ISA level they
22 were introduced in. */
23#define ISA_MIPS1 0x00000001
24#define ISA_MIPS2 0x00000002
25#define ISA_MIPS3 0x00000004
26#define ISA_MIPS4 0x00000008
27#define ISA_MIPS5 0x00000010
28#define ISA_MIPS32 0x00000020
29#define ISA_MIPS32R2 0x00000040
30#define ISA_MIPS64 0x00000080
31#define ISA_MIPS64R2 0x00000100
Petar Jovanovice5275262014-01-15 17:01:46 +010032#define ISA_MIPS32R3 0x00000200
Leon Alraefa0d2f62014-06-27 08:49:00 +010033#define ISA_MIPS64R3 0x00000400
34#define ISA_MIPS32R5 0x00000800
35#define ISA_MIPS64R5 0x00001000
36#define ISA_MIPS32R6 0x00002000
37#define ISA_MIPS64R6 0x00004000
thse189e742007-09-24 12:48:00 +000038
thse9c71dd2007-12-25 20:46:56 +000039/* MIPS ASEs. */
Leon Alraefa0d2f62014-06-27 08:49:00 +010040#define ASE_MIPS16 0x00010000
41#define ASE_MIPS3D 0x00020000
42#define ASE_MDMX 0x00040000
43#define ASE_DSP 0x00080000
44#define ASE_DSPR2 0x00100000
45#define ASE_MT 0x00200000
46#define ASE_SMARTMIPS 0x00400000
47#define ASE_MICROMIPS 0x00800000
Yongbok Kime97a3912014-11-01 05:28:35 +000048#define ASE_MSA 0x01000000
thse189e742007-09-24 12:48:00 +000049
thse9c71dd2007-12-25 20:46:56 +000050/* Chip specific instructions. */
Huacai Chen5bc6fba2010-06-29 10:50:27 +080051#define INSN_LOONGSON2E 0x20000000
52#define INSN_LOONGSON2F 0x40000000
thse9c71dd2007-12-25 20:46:56 +000053#define INSN_VR54XX 0x80000000
thse189e742007-09-24 12:48:00 +000054
thse9c71dd2007-12-25 20:46:56 +000055/* MIPS CPU defines. */
thse189e742007-09-24 12:48:00 +000056#define CPU_MIPS1 (ISA_MIPS1)
57#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
58#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
59#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
thse9c71dd2007-12-25 20:46:56 +000060#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
Huacai Chen5bc6fba2010-06-29 10:50:27 +080061#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
62#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
thse9c71dd2007-12-25 20:46:56 +000063
thse189e742007-09-24 12:48:00 +000064#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
65
thse9c71dd2007-12-25 20:46:56 +000066/* MIPS Technologies "Release 1" */
thse189e742007-09-24 12:48:00 +000067#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
68#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
69
thse9c71dd2007-12-25 20:46:56 +000070/* MIPS Technologies "Release 2" */
thse189e742007-09-24 12:48:00 +000071#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
72#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
73
Petar Jovanovice5275262014-01-15 17:01:46 +010074/* MIPS Technologies "Release 3" */
75#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
Leon Alraefa0d2f62014-06-27 08:49:00 +010076#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
Petar Jovanovice5275262014-01-15 17:01:46 +010077
78/* MIPS Technologies "Release 5" */
79#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
Leon Alraefa0d2f62014-06-27 08:49:00 +010080#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
81
82/* MIPS Technologies "Release 6" */
83#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
84#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
Petar Jovanovice5275262014-01-15 17:01:46 +010085
ths19221bd2007-04-19 16:35:09 +000086/* Strictly follow the architecture standard:
87 - Disallow "special" instruction handling for PMON/SPIM.
88 Note that we still maintain Count/Compare to match the host clock. */
thsb48cfdf2007-04-11 02:24:14 +000089//#define MIPS_STRICT_STANDARD 1
90
bellard6af0bf92005-07-02 14:58:51 +000091#endif /* !defined (__QEMU_MIPS_DEFS_H__) */