Andreas Färber | dec9c2d | 2012-03-29 04:50:31 +0000 | [diff] [blame] | 1 | /* |
| 2 | * QEMU ARM CPU |
| 3 | * |
| 4 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see |
| 18 | * <http://www.gnu.org/licenses/gpl-2.0.html> |
| 19 | */ |
| 20 | #ifndef QEMU_ARM_CPU_QOM_H |
| 21 | #define QEMU_ARM_CPU_QOM_H |
| 22 | |
Paolo Bonzini | 14cccb6 | 2012-12-17 18:19:50 +0100 | [diff] [blame] | 23 | #include "qom/cpu.h" |
Andreas Färber | dec9c2d | 2012-03-29 04:50:31 +0000 | [diff] [blame] | 24 | |
Paolo Bonzini | 74e7556 | 2016-03-15 13:49:25 +0100 | [diff] [blame] | 25 | struct arm_boot_info; |
| 26 | |
Andreas Färber | dec9c2d | 2012-03-29 04:50:31 +0000 | [diff] [blame] | 27 | #define TYPE_ARM_CPU "arm-cpu" |
| 28 | |
| 29 | #define ARM_CPU_CLASS(klass) \ |
| 30 | OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU) |
| 31 | #define ARM_CPU(obj) \ |
| 32 | OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU) |
| 33 | #define ARM_CPU_GET_CLASS(obj) \ |
| 34 | OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) |
| 35 | |
| 36 | /** |
| 37 | * ARMCPUClass: |
Andreas Färber | 1496926 | 2013-01-05 10:18:18 +0100 | [diff] [blame] | 38 | * @parent_realize: The parent class' realize handler. |
Andreas Färber | dec9c2d | 2012-03-29 04:50:31 +0000 | [diff] [blame] | 39 | * @parent_reset: The parent class' reset handler. |
| 40 | * |
| 41 | * An ARM CPU model. |
| 42 | */ |
| 43 | typedef struct ARMCPUClass { |
| 44 | /*< private >*/ |
| 45 | CPUClass parent_class; |
| 46 | /*< public >*/ |
| 47 | |
Andreas Färber | 1496926 | 2013-01-05 10:18:18 +0100 | [diff] [blame] | 48 | DeviceRealize parent_realize; |
Andreas Färber | dec9c2d | 2012-03-29 04:50:31 +0000 | [diff] [blame] | 49 | void (*parent_reset)(CPUState *cpu); |
| 50 | } ARMCPUClass; |
| 51 | |
Paolo Bonzini | 74e7556 | 2016-03-15 13:49:25 +0100 | [diff] [blame] | 52 | typedef struct ARMCPU ARMCPU; |
Andreas Färber | dec9c2d | 2012-03-29 04:50:31 +0000 | [diff] [blame] | 53 | |
Peter Maydell | d14d42f | 2013-09-03 20:12:07 +0100 | [diff] [blame] | 54 | #define TYPE_AARCH64_CPU "aarch64-cpu" |
| 55 | #define AARCH64_CPU_CLASS(klass) \ |
| 56 | OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU) |
| 57 | #define AARCH64_CPU_GET_CLASS(obj) \ |
| 58 | OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU) |
| 59 | |
| 60 | typedef struct AArch64CPUClass { |
| 61 | /*< private >*/ |
| 62 | ARMCPUClass parent_class; |
| 63 | /*< public >*/ |
| 64 | } AArch64CPUClass; |
| 65 | |
Peter Maydell | 2ceb98c | 2012-06-20 11:57:09 +0000 | [diff] [blame] | 66 | void register_cp_regs_for_features(ARMCPU *cpu); |
Peter Maydell | 721fae1 | 2013-06-25 18:16:07 +0100 | [diff] [blame] | 67 | void init_cpreg_list(ARMCPU *cpu); |
Andreas Färber | dec9c2d | 2012-03-29 04:50:31 +0000 | [diff] [blame] | 68 | |
Peter Maydell | 55d284a | 2013-08-20 14:54:31 +0100 | [diff] [blame] | 69 | /* Callback functions for the generic timer's timers. */ |
| 70 | void arm_gt_ptimer_cb(void *opaque); |
| 71 | void arm_gt_vtimer_cb(void *opaque); |
Edgar E. Iglesias | b0e66d9 | 2015-08-13 11:26:18 +0100 | [diff] [blame] | 72 | void arm_gt_htimer_cb(void *opaque); |
Peter Maydell | b4d3978 | 2015-08-13 11:26:22 +0100 | [diff] [blame] | 73 | void arm_gt_stimer_cb(void *opaque); |
Peter Maydell | 55d284a | 2013-08-20 14:54:31 +0100 | [diff] [blame] | 74 | |
Pavel Fedin | 0f4a9e4 | 2015-09-07 10:39:31 +0100 | [diff] [blame] | 75 | #define ARM_AFF0_SHIFT 0 |
| 76 | #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) |
| 77 | #define ARM_AFF1_SHIFT 8 |
| 78 | #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) |
| 79 | #define ARM_AFF2_SHIFT 16 |
| 80 | #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) |
| 81 | #define ARM_AFF3_SHIFT 32 |
| 82 | #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) |
| 83 | |
| 84 | #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) |
| 85 | #define ARM64_AFFINITY_MASK \ |
| 86 | (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) |
| 87 | |
Andreas Färber | dec9c2d | 2012-03-29 04:50:31 +0000 | [diff] [blame] | 88 | #endif |