commit | f900da7691db16b534d5b4abcab2fdb29673aaa9 | [log] [tgz] |
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author | Siarhei Volkau <lis8215@gmail.com> | Thu Jun 08 13:42:13 2023 +0300 |
committer | Philippe Mathieu-Daudé <philmd@linaro.org> | Mon Jul 10 23:33:38 2023 +0200 |
tree | 17d5e605e6d7fad63f0c28781d4e18b28e0164d5 | |
parent | 5925963476d65ce1a74651bbf48865977ff0c1b0 [diff] |
target/mips/mxu: Add D32SARL D32SARW instructions These instructions are dual 32-bit arithmetic shift right and pack LSBs to 2x 16-bit into a MXU register. The difference is the shift amount source: immediate or GP reg. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-25-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>