)]}'
{
  "commit": "f900da7691db16b534d5b4abcab2fdb29673aaa9",
  "tree": "17d5e605e6d7fad63f0c28781d4e18b28e0164d5",
  "parents": [
    "5925963476d65ce1a74651bbf48865977ff0c1b0"
  ],
  "author": {
    "name": "Siarhei Volkau",
    "email": "lis8215@gmail.com",
    "time": "Thu Jun 08 13:42:13 2023 +0300"
  },
  "committer": {
    "name": "Philippe Mathieu-Daudé",
    "email": "philmd@linaro.org",
    "time": "Mon Jul 10 23:33:38 2023 +0200"
  },
  "message": "target/mips/mxu: Add D32SARL D32SARW instructions\n\nThese instructions are dual 32-bit arithmetic shift right and\npack LSBs to 2x 16-bit into a MXU register.\nThe difference is the shift amount source: immediate or GP reg.\n\nSigned-off-by: Siarhei Volkau \u003clis8215@gmail.com\u003e\nMessage-Id: \u003c20230608104222.1520143-25-lis8215@gmail.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4f07201fccf13cf87080ab2c4b21265a893223fa",
      "old_mode": 33188,
      "old_path": "target/mips/tcg/mxu_translate.c",
      "new_id": "36fb4232cd6b9e47942d57c8c58070780f1332b2",
      "new_mode": 33188,
      "new_path": "target/mips/tcg/mxu_translate.c"
    }
  ]
}