Sign in
qemu
/
qemu
/
f84aad4d718b83d2a4d90485992e5421430032e1
/
.
/
tcg
/
aarch64
/
tcg-target-reg-bits.h
blob: 3b57a1aafb93fa41a8df41b0743db6cef8979157 [
file
] [
log
] [
blame
]
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Define target-specific register size
* Copyright (c) 2023 Linaro
*/
#ifndef
TCG_TARGET_REG_BITS_H
#define
TCG_TARGET_REG_BITS_H
#define
TCG_TARGET_REG_BITS
64
#endif