Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2020-03-17' into staging
QAPI patches for 2020-03-17
# gpg: Signature made Tue 17 Mar 2020 20:50:54 GMT
# gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg: issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* remotes/armbru/tags/pull-qapi-2020-03-17: (30 commits)
net: Track netdevs in NetClientState rather than QemuOpt
net: Complete qapi-fication of netdev_add
qmp: constify QmpCommand and list
qapi: Mark deprecated QMP parts with feature 'deprecated'
qapi: New special feature flag "deprecated"
qapi: Replace qmp_dispatch()'s TODO comment by an explanation
qapi: Simplify how qmp_dispatch() gets the request ID
qapi: Simplify how qmp_dispatch() deals with QCO_NO_SUCCESS_RESP
qapi: Inline do_qmp_dispatch() into qmp_dispatch()
qapi: Add feature flags to struct members
qapi/schema: Call QAPIDoc.connect_member() in just one place
qapi/schema: Rename QAPISchemaObjectType{Variant,Variants}
qapi/schema: Reorder classes so related ones are together
qapi/schema: Change _make_features() to a take feature list
qapi/introspect: Factor out _make_tree()
qapi/introspect: Rename *qlit* to reduce confusion
qapi: Consistently put @features parameter right after @ifcond
qapi: Add feature flags to remaining definitions
qapi/schema: Clean up around QAPISchemaEntity.connect_doc()
tests/test-qmp-event: Check event is actually emitted
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/.mailmap b/.mailmap
index 76154c7..6412067 100644
--- a/.mailmap
+++ b/.mailmap
@@ -39,8 +39,9 @@
Justin Terry (VM) <juterry@microsoft.com> Justin Terry (VM) via Qemu-devel <qemu-devel@nongnu.org>
# Next, replace old addresses by a more recent one.
-Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>
-Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>
+Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <aleksandar.markovic@mips.com>
+Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <aleksandar.markovic@imgtec.com>
+Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <amarkovic@wavecomp.com>
Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> <arikalo@wavecomp.com>
Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
diff --git a/.travis.yml b/.travis.yml
index b92798a..ccf68aa 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -79,6 +79,7 @@
- MAIN_SOFTMMU_TARGETS="aarch64-softmmu,mips64-softmmu,ppc64-softmmu,riscv64-softmmu,s390x-softmmu,x86_64-softmmu"
- CCACHE_SLOPPINESS="include_file_ctime,include_file_mtime"
- CCACHE_MAXSIZE=1G
+ - G_MESSAGES_DEBUG=error
git:
diff --git a/MAINTAINERS b/MAINTAINERS
index 32867bc..7364af0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -209,8 +209,8 @@
F: disas/microblaze.c
MIPS TCG CPUs
-M: Aurelien Jarno <aurelien@aurel32.net>
-M: Aleksandar Markovic <amarkovic@wavecomp.com>
+M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
+R: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: target/mips/
@@ -226,6 +226,7 @@
F: include/hw/misc/mips_*
F: include/hw/timer/mips_gictimer.h
F: tests/acceptance/linux_ssh_mips_malta.py
+F: tests/acceptance/machine_mips_malta.py
F: tests/tcg/mips/
K: ^Subject:.*(?i)mips
@@ -367,7 +368,7 @@
F: target/arm/kvm.c
MIPS KVM CPUs
-M: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
+M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
S: Odd Fixes
F: target/mips/kvm.c
@@ -436,6 +437,17 @@
F: include/hw/xen/
F: include/sysemu/xen-mapcache.h
+Guest CPU Cores (HAXM)
+---------------------
+X86 HAXM CPUs
+M: Wenchao Wang <wenchao.wang@intel.com>
+M: Colin Xu <colin.xu@intel.com>
+L: haxm-team@intel.com
+W: https://github.com/intel/haxm/issues
+S: Maintained
+F: include/sysemu/hax.h
+F: target/i386/hax-*
+
Hosts
-----
LINUX
@@ -764,6 +776,8 @@
F: hw/arm/fsl-imx6.c
F: hw/misc/imx6_*.c
F: hw/ssi/imx_spi.c
+F: hw/usb/imx-usb-phy.c
+F: include/hw/usb/imx-usb-phy.h
F: include/hw/arm/fsl-imx6.h
F: include/hw/misc/imx6_*.h
F: include/hw/ssi/imx_spi.h
@@ -1016,7 +1030,7 @@
F: hw/dma/rc4030.c
Malta
-M: Aleksandar Markovic <amarkovic@wavecomp.com>
+M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
R: Aurelien Jarno <aurelien@aurel32.net>
S: Maintained
@@ -1029,21 +1043,22 @@
F: tests/acceptance/machine_mips_malta.py
Mipssim
-M: Aleksandar Markovic <amarkovic@wavecomp.com>
+M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/net/mipsnet.c
R4000
-M: Aurelien Jarno <aurelien@aurel32.net>
+M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
+R: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Obsolete
F: hw/mips/mips_r4k.c
Fulong 2E
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
-M: Aleksandar Markovic <amarkovic@wavecomp.com>
+M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/isa/vt82c686.c
@@ -2036,6 +2051,7 @@
F: memory.c
F: include/exec/memory-internal.h
F: exec.c
+F: scripts/coccinelle/memory-region-housekeeping.cocci
SPICE
M: Gerd Hoffmann <kraxel@redhat.com>
@@ -2507,7 +2523,8 @@
F: disas/i386.c
MIPS TCG target
-M: Aurelien Jarno <aurelien@aurel32.net>
+M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
+R: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: tcg/mips/
@@ -2835,7 +2852,7 @@
F: scripts/git-submodule.sh
UI translations
-M: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
+M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
F: po/*.po
Sphinx documentation configuration and build machinery
diff --git a/Makefile b/Makefile
index ea0e08f..fc2808f 100644
--- a/Makefile
+++ b/Makefile
@@ -1235,50 +1235,57 @@
include $(SRC_PATH)/tests/docker/Makefile.include
include $(SRC_PATH)/tests/vm/Makefile.include
+print-help-run = printf " %-30s - %s\\n" "$1" "$2"
+print-help = $(quiet-@)$(call print-help-run,$1,$2)
+
.PHONY: help
help:
@echo 'Generic targets:'
- @echo ' all - Build all'
+ $(call print-help,all,Build all)
ifdef CONFIG_MODULES
- @echo ' modules - Build all modules'
+ $(call print-help,modules,Build all modules)
endif
- @echo ' dir/file.o - Build specified target only'
- @echo ' install - Install QEMU, documentation and tools'
- @echo ' ctags/TAGS - Generate tags file for editors'
- @echo ' cscope - Generate cscope index'
+ $(call print-help,dir/file.o,Build specified target only)
+ $(call print-help,install,Install QEMU, documentation and tools)
+ $(call print-help,ctags/TAGS,Generate tags file for editors)
+ $(call print-help,cscope,Generate cscope index)
@echo ''
@$(if $(TARGET_DIRS), \
echo 'Architecture specific targets:'; \
$(foreach t, $(TARGET_DIRS), \
- printf " %-30s - Build for %s\\n" $(t)/all $(t);) \
+ $(call print-help-run,$(t)/all,Build for $(t));) \
+ echo '')
+ @$(if $(TOOLS), \
+ echo 'Tools targets:'; \
+ $(foreach t, $(TOOLS), \
+ $(call print-help-run,$(t),Build $(shell basename $(t)) tool);) \
echo '')
@echo 'Cleaning targets:'
- @echo ' clean - Remove most generated files but keep the config'
+ $(call print-help,clean,Remove most generated files but keep the config)
ifdef CONFIG_GCOV
- @echo ' clean-coverage - Remove coverage files'
+ $(call print-help,clean-coverage,Remove coverage files)
endif
- @echo ' distclean - Remove all generated files'
- @echo ' dist - Build a distributable tarball'
+ $(call print-help,distclean,Remove all generated files)
+ $(call print-help,dist,Build a distributable tarball)
@echo ''
@echo 'Test targets:'
- @echo ' check - Run all tests (check-help for details)'
- @echo ' docker - Help about targets running tests inside containers'
- @echo ' vm-help - Help about targets running tests inside VM'
+ $(call print-help,check,Run all tests (check-help for details))
+ $(call print-help,docker,Help about targets running tests inside containers)
+ $(call print-help,vm-help,Help about targets running tests inside VM)
@echo ''
@echo 'Documentation targets:'
- @echo ' html info pdf txt'
- @echo ' - Build documentation in specified format'
+ $(call print-help,html info pdf txt,Build documentation in specified format)
ifdef CONFIG_GCOV
- @echo ' coverage-report - Create code coverage report'
+ $(call print-help,coverage-report,Create code coverage report)
endif
@echo ''
ifdef CONFIG_WIN32
@echo 'Windows targets:'
- @echo ' installer - Build NSIS-based installer for QEMU'
+ $(call print-help,installer,Build NSIS-based installer for QEMU)
ifdef QEMU_GA_MSI_ENABLED
- @echo ' msi - Build MSI-based installer for qemu-ga'
+ $(call print-help,msi,Build MSI-based installer for qemu-ga)
endif
@echo ''
endif
- @echo ' $(MAKE) [targets] (quiet build, default)'
- @echo ' $(MAKE) V=1 [targets] (verbose build)'
+ $(call print-help,$(MAKE) [targets],(quiet build, default))
+ $(call print-help,$(MAKE) V=1 [targets],(verbose build))
diff --git a/Makefile.target b/Makefile.target
index 2d43dc5..934a9f7 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -12,7 +12,7 @@
$(call set-vpath, $(SRC_PATH):$(BUILD_DIR))
ifdef CONFIG_LINUX
-QEMU_CFLAGS += -I../linux-headers
+QEMU_CFLAGS += -isystem ../linux-headers
endif
QEMU_CFLAGS += -iquote .. -iquote $(SRC_PATH)/target/$(TARGET_BASE_ARCH) -DNEED_CPU_H
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 5b1902d..ca44970 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -24,48 +24,6 @@
#include "tcg/tcg-gvec-desc.h"
-/* Virtually all hosts support 16-byte vectors. Those that don't can emulate
- * them via GCC's generic vector extension. This turns out to be simpler and
- * more reliable than getting the compiler to autovectorize.
- *
- * In tcg-op-gvec.c, we asserted that both the size and alignment of the data
- * are multiples of 16.
- *
- * When the compiler does not support all of the operations we require, the
- * loops are written so that we can always fall back on the base types.
- */
-#ifdef CONFIG_VECTOR16
-typedef uint8_t vec8 __attribute__((vector_size(16)));
-typedef uint16_t vec16 __attribute__((vector_size(16)));
-typedef uint32_t vec32 __attribute__((vector_size(16)));
-typedef uint64_t vec64 __attribute__((vector_size(16)));
-
-typedef int8_t svec8 __attribute__((vector_size(16)));
-typedef int16_t svec16 __attribute__((vector_size(16)));
-typedef int32_t svec32 __attribute__((vector_size(16)));
-typedef int64_t svec64 __attribute__((vector_size(16)));
-
-#define DUP16(X) { X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X }
-#define DUP8(X) { X, X, X, X, X, X, X, X }
-#define DUP4(X) { X, X, X, X }
-#define DUP2(X) { X, X }
-#else
-typedef uint8_t vec8;
-typedef uint16_t vec16;
-typedef uint32_t vec32;
-typedef uint64_t vec64;
-
-typedef int8_t svec8;
-typedef int16_t svec16;
-typedef int32_t svec32;
-typedef int64_t svec64;
-
-#define DUP16(X) X
-#define DUP8(X) X
-#define DUP4(X) X
-#define DUP2(X) X
-#endif /* CONFIG_VECTOR16 */
-
static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc)
{
intptr_t maxsz = simd_maxsz(desc);
@@ -83,8 +41,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) + *(vec8 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + *(uint8_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -94,8 +52,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) + *(vec16 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + *(uint16_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -105,8 +63,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) + *(vec32 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + *(uint32_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -116,8 +74,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) + *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -125,11 +83,10 @@
void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec8 vecb = (vec8)DUP16(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) + vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + (uint8_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -137,11 +94,10 @@
void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec16 vecb = (vec16)DUP8(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) + vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + (uint16_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -149,11 +105,10 @@
void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec32 vecb = (vec32)DUP4(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) + vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + (uint32_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -161,11 +116,10 @@
void HELPER(gvec_adds64)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) + vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + b;
}
clear_high(d, oprsz, desc);
}
@@ -175,8 +129,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) - *(vec8 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - *(uint8_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -186,8 +140,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) - *(vec16 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - *(uint16_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -197,8 +151,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) - *(vec32 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - *(uint32_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -208,8 +162,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) - *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -217,11 +171,10 @@
void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec8 vecb = (vec8)DUP16(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) - vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - (uint8_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -229,11 +182,10 @@
void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec16 vecb = (vec16)DUP8(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) - vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - (uint16_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -241,11 +193,10 @@
void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec32 vecb = (vec32)DUP4(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) - vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - (uint32_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -253,11 +204,10 @@
void HELPER(gvec_subs64)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) - vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - b;
}
clear_high(d, oprsz, desc);
}
@@ -267,8 +217,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) * *(vec8 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * *(uint8_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -278,8 +228,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) * *(vec16 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * *(uint16_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -289,8 +239,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) * *(vec32 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * *(uint32_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -300,8 +250,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) * *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -309,11 +259,10 @@
void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec8 vecb = (vec8)DUP16(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) * vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * (uint8_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -321,11 +270,10 @@
void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec16 vecb = (vec16)DUP8(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) * vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * (uint16_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -333,11 +281,10 @@
void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec32 vecb = (vec32)DUP4(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) * vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * (uint32_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -345,11 +292,10 @@
void HELPER(gvec_muls64)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) * vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * b;
}
clear_high(d, oprsz, desc);
}
@@ -359,8 +305,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = -*(vec8 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = -*(uint8_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -370,8 +316,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = -*(vec16 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = -*(uint16_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -381,8 +327,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = -*(vec32 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = -*(uint32_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -392,8 +338,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = -*(vec64 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = -*(uint64_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -499,8 +445,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = ~*(vec64 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = ~*(uint64_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -510,8 +456,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) & *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -521,8 +467,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) | *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -532,8 +478,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -543,8 +489,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) &~ *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -554,8 +500,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) |~ *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -565,8 +511,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = ~(*(vec64 *)(a + i) & *(vec64 *)(b + i));
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = ~(*(uint64_t *)(a + i) & *(uint64_t *)(b + i));
}
clear_high(d, oprsz, desc);
}
@@ -576,8 +522,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = ~(*(vec64 *)(a + i) | *(vec64 *)(b + i));
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = ~(*(uint64_t *)(a + i) | *(uint64_t *)(b + i));
}
clear_high(d, oprsz, desc);
}
@@ -587,8 +533,8 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = ~(*(vec64 *)(a + i) ^ *(vec64 *)(b + i));
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = ~(*(uint64_t *)(a + i) ^ *(uint64_t *)(b + i));
}
clear_high(d, oprsz, desc);
}
@@ -596,11 +542,10 @@
void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) & vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & b;
}
clear_high(d, oprsz, desc);
}
@@ -608,11 +553,10 @@
void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ b;
}
clear_high(d, oprsz, desc);
}
@@ -620,11 +564,10 @@
void HELPER(gvec_ors)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) | vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | b;
}
clear_high(d, oprsz, desc);
}
@@ -635,8 +578,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) << shift;
}
clear_high(d, oprsz, desc);
}
@@ -647,8 +590,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) << shift;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) << shift;
}
clear_high(d, oprsz, desc);
}
@@ -659,8 +602,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) << shift;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) << shift;
}
clear_high(d, oprsz, desc);
}
@@ -671,8 +614,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) << shift;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) << shift;
}
clear_high(d, oprsz, desc);
}
@@ -683,8 +626,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -695,8 +638,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -707,8 +650,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -719,8 +662,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -731,8 +674,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(svec8 *)(d + i) = *(svec8 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(int8_t *)(d + i) = *(int8_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -743,8 +686,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(svec16 *)(d + i) = *(svec16 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(int16_t *)(d + i) = *(int16_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -755,8 +698,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(svec32 *)(d + i) = *(svec32 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(int32_t *)(d + i) = *(int32_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -767,8 +710,8 @@
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(svec64 *)(d + i) = *(svec64 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(int64_t *)(d + i) = *(int64_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -917,39 +860,30 @@
clear_high(d, oprsz, desc);
}
-/* If vectors are enabled, the compiler fills in -1 for true.
- Otherwise, we must take care of this by hand. */
-#ifdef CONFIG_VECTOR16
-# define DO_CMP0(X) X
-#else
-# define DO_CMP0(X) -(X)
-#endif
-
#define DO_CMP1(NAME, TYPE, OP) \
void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
{ \
intptr_t oprsz = simd_oprsz(desc); \
intptr_t i; \
for (i = 0; i < oprsz; i += sizeof(TYPE)) { \
- *(TYPE *)(d + i) = DO_CMP0(*(TYPE *)(a + i) OP *(TYPE *)(b + i)); \
+ *(TYPE *)(d + i) = -(*(TYPE *)(a + i) OP *(TYPE *)(b + i)); \
} \
clear_high(d, oprsz, desc); \
}
#define DO_CMP2(SZ) \
- DO_CMP1(gvec_eq##SZ, vec##SZ, ==) \
- DO_CMP1(gvec_ne##SZ, vec##SZ, !=) \
- DO_CMP1(gvec_lt##SZ, svec##SZ, <) \
- DO_CMP1(gvec_le##SZ, svec##SZ, <=) \
- DO_CMP1(gvec_ltu##SZ, vec##SZ, <) \
- DO_CMP1(gvec_leu##SZ, vec##SZ, <=)
+ DO_CMP1(gvec_eq##SZ, uint##SZ##_t, ==) \
+ DO_CMP1(gvec_ne##SZ, uint##SZ##_t, !=) \
+ DO_CMP1(gvec_lt##SZ, int##SZ##_t, <) \
+ DO_CMP1(gvec_le##SZ, int##SZ##_t, <=) \
+ DO_CMP1(gvec_ltu##SZ, uint##SZ##_t, <) \
+ DO_CMP1(gvec_leu##SZ, uint##SZ##_t, <=)
DO_CMP2(8)
DO_CMP2(16)
DO_CMP2(32)
DO_CMP2(64)
-#undef DO_CMP0
#undef DO_CMP1
#undef DO_CMP2
@@ -1450,11 +1384,11 @@
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- vec64 aa = *(vec64 *)(a + i);
- vec64 bb = *(vec64 *)(b + i);
- vec64 cc = *(vec64 *)(c + i);
- *(vec64 *)(d + i) = (bb & aa) | (cc & ~aa);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ uint64_t aa = *(uint64_t *)(a + i);
+ uint64_t bb = *(uint64_t *)(b + i);
+ uint64_t cc = *(uint64_t *)(c + i);
+ *(uint64_t *)(d + i) = (bb & aa) | (cc & ~aa);
}
clear_high(d, oprsz, desc);
}
diff --git a/block/io.c b/block/io.c
index 7e4cb74..aba67f6 100644
--- a/block/io.c
+++ b/block/io.c
@@ -1399,7 +1399,7 @@
if (!(flags & BDRV_REQ_PREFETCH)) {
qemu_iovec_from_buf(qiov, qiov_offset + progress,
bounce_buffer + skip_bytes,
- pnum - skip_bytes);
+ MIN(pnum - skip_bytes, bytes - progress));
}
} else if (!(flags & BDRV_REQ_PREFETCH)) {
/* Read directly into the destination */
diff --git a/block/linux-aio.c b/block/linux-aio.c
index 91204a2..3c0527c 100644
--- a/block/linux-aio.c
+++ b/block/linux-aio.c
@@ -121,7 +121,7 @@
unsigned incompat_features;
unsigned header_length; /* size of aio_ring */
- struct io_event io_events[0];
+ struct io_event io_events[];
};
/**
diff --git a/block/monitor/block-hmp-cmds.c b/block/monitor/block-hmp-cmds.c
index c3a6368..4c8c375 100644
--- a/block/monitor/block-hmp-cmds.c
+++ b/block/monitor/block-hmp-cmds.c
@@ -838,10 +838,8 @@
void hmp_info_block_jobs(Monitor *mon, const QDict *qdict)
{
BlockJobInfoList *list;
- Error *err = NULL;
- list = qmp_query_block_jobs(&err);
- assert(!err);
+ list = qmp_query_block_jobs(&error_abort);
if (!list) {
monitor_printf(mon, "No active jobs\n");
diff --git a/block/vmdk.c b/block/vmdk.c
index 20e909d..8466051 100644
--- a/block/vmdk.c
+++ b/block/vmdk.c
@@ -187,7 +187,7 @@
typedef struct VmdkGrainMarker {
uint64_t lba;
uint32_t size;
- uint8_t data[0];
+ uint8_t data[];
} QEMU_PACKED VmdkGrainMarker;
enum {
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index 09e8aed..f8bb1e5 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -95,7 +95,7 @@
struct sigqueue *first_free; /* first free siginfo queue entry */
int signal_pending; /* non zero if a signal may be pending */
- uint8_t stack[0];
+ uint8_t stack[];
} __attribute__((aligned(16))) TaskState;
void init_task_state(TaskState *ts);
diff --git a/configure b/configure
index eb49bb6..206d22c 100755
--- a/configure
+++ b/configure
@@ -303,6 +303,7 @@
debug_info="yes"
stack_protector=""
use_containers="yes"
+gdb_bin=$(command -v "gdb")
if test -e "$source_path/.git"
then
@@ -405,6 +406,7 @@
DSOSUF=".so"
LDFLAGS_SHARED="-shared"
modules="no"
+module_upgrades="no"
prefix="/usr/local"
mandir="\${prefix}/share/man"
datadir="\${prefix}/share"
@@ -899,7 +901,7 @@
linux="yes"
linux_user="yes"
kvm="yes"
- QEMU_INCLUDES="-I\$(SRC_PATH)/linux-headers -I$PWD/linux-headers $QEMU_INCLUDES"
+ QEMU_INCLUDES="-isystem \$(SRC_PATH)/linux-headers -isystem $PWD/linux-headers $QEMU_INCLUDES"
supported_os="yes"
libudev="yes"
;;
@@ -1032,6 +1034,10 @@
--disable-modules)
modules="no"
;;
+ --disable-module-upgrades) module_upgrades="no"
+ ;;
+ --enable-module-upgrades) module_upgrades="yes"
+ ;;
--cpu=*)
;;
--target-list=*) target_list="$optarg"
@@ -1421,6 +1427,11 @@
;;
--enable-avx2) avx2_opt="yes"
;;
+ --disable-avx512f) avx512f_opt="no"
+ ;;
+ --enable-avx512f) avx512f_opt="yes"
+ ;;
+
--enable-glusterfs) glusterfs="yes"
;;
--disable-virtio-blk-data-plane|--enable-virtio-blk-data-plane)
@@ -1588,6 +1599,8 @@
;;
--disable-fuzzing) fuzzing=no
;;
+ --gdb=*) gdb_bin="$optarg"
+ ;;
*)
echo "ERROR: unknown option $opt"
echo "Try '$0 --help' for more information"
@@ -1773,6 +1786,7 @@
--enable-plugins
enable plugins via shared library loading
--disable-containers don't use containers for cross-building
+ --gdb=GDB-path gdb to use for gdbstub tests [$gdb_bin]
Optional features, enabled with --enable-FEATURE and
disabled with --disable-FEATURE, default is enabled if available:
@@ -1786,6 +1800,7 @@
guest-agent-msi build guest agent Windows MSI installation package
pie Position Independent Executables
modules modules support (non-Windows)
+ module-upgrades try to load modules from alternate paths for upgrades
debug-tcg TCG debugging (default is disabled)
debug-info debugging information
sparse sparse checker
@@ -1857,6 +1872,7 @@
tcmalloc tcmalloc support
jemalloc jemalloc support
avx2 AVX2 optimization support
+ avx512f AVX512F optimization support
replication replication support
opengl opengl support
virglrenderer virgl rendering support
@@ -2049,6 +2065,11 @@
error_exit "Modules are not available for Windows"
fi
+# module_upgrades is only reasonable if modules are enabled
+if test "$modules" = "no" && test "$module_upgrades" = "yes" ; then
+ error_exit "Can't enable module-upgrades as Modules are not enabled"
+fi
+
# Static linking is not possible with modules or PIE
if test "$static" = "yes" ; then
if test "$modules" = "yes" ; then
@@ -3350,7 +3371,9 @@
int main(void) { sasl_server_init(NULL, "qemu"); return 0; }
EOF
# Assuming Cyrus-SASL installed in /usr prefix
- vnc_sasl_cflags=""
+ # QEMU defines struct iovec in "qemu/osdep.h",
+ # we don't want libsasl to redefine it in <sasl/sasl.h>.
+ vnc_sasl_cflags="-DSTRUCT_IOVEC_DEFINED"
vnc_sasl_libs="-lsasl2"
if compile_prog "$vnc_sasl_cflags" "$vnc_sasl_libs" ; then
vnc_sasl=yes
@@ -5574,6 +5597,36 @@
fi
fi
+##########################################
+# avx512f optimization requirement check
+#
+# There is no point enabling this if cpuid.h is not usable,
+# since we won't be able to select the new routines.
+# by default, it is turned off.
+# if user explicitly want to enable it, check environment
+
+if test "$cpuid_h" = "yes" && test "$avx512f_opt" = "yes"; then
+ cat > $TMPC << EOF
+#pragma GCC push_options
+#pragma GCC target("avx512f")
+#include <cpuid.h>
+#include <immintrin.h>
+static int bar(void *a) {
+ __m512i x = *(__m512i *)a;
+ return _mm512_test_epi64_mask(x, x);
+}
+int main(int argc, char *argv[])
+{
+ return bar(argv[0]);
+}
+EOF
+ if ! compile_object "" ; then
+ avx512f_opt="no"
+ fi
+else
+ avx512f_opt="no"
+fi
+
########################################
# check if __[u]int128_t is usable.
@@ -5712,58 +5765,6 @@
fi
########################################
-# See if 16-byte vector operations are supported.
-# Even without a vector unit the compiler may expand these.
-# There is a bug in old GCC for PPC that crashes here.
-# Unfortunately it's the system compiler for Centos 7.
-
-cat > $TMPC << EOF
-typedef unsigned char U1 __attribute__((vector_size(16)));
-typedef unsigned short U2 __attribute__((vector_size(16)));
-typedef unsigned int U4 __attribute__((vector_size(16)));
-typedef unsigned long long U8 __attribute__((vector_size(16)));
-typedef signed char S1 __attribute__((vector_size(16)));
-typedef signed short S2 __attribute__((vector_size(16)));
-typedef signed int S4 __attribute__((vector_size(16)));
-typedef signed long long S8 __attribute__((vector_size(16)));
-static U1 a1, b1;
-static U2 a2, b2;
-static U4 a4, b4;
-static U8 a8, b8;
-static S1 c1;
-static S2 c2;
-static S4 c4;
-static S8 c8;
-static int i;
-void helper(void *d, void *a, int shift, int i);
-void helper(void *d, void *a, int shift, int i)
-{
- *(U1 *)(d + i) = *(U1 *)(a + i) << shift;
- *(U2 *)(d + i) = *(U2 *)(a + i) << shift;
- *(U4 *)(d + i) = *(U4 *)(a + i) << shift;
- *(U8 *)(d + i) = *(U8 *)(a + i) << shift;
-}
-int main(void)
-{
- a1 += b1; a2 += b2; a4 += b4; a8 += b8;
- a1 -= b1; a2 -= b2; a4 -= b4; a8 -= b8;
- a1 *= b1; a2 *= b2; a4 *= b4; a8 *= b8;
- a1 &= b1; a2 &= b2; a4 &= b4; a8 &= b8;
- a1 |= b1; a2 |= b2; a4 |= b4; a8 |= b8;
- a1 ^= b1; a2 ^= b2; a4 ^= b4; a8 ^= b8;
- a1 <<= i; a2 <<= i; a4 <<= i; a8 <<= i;
- a1 >>= i; a2 >>= i; a4 >>= i; a8 >>= i;
- c1 >>= i; c2 >>= i; c4 >>= i; c8 >>= i;
- return 0;
-}
-EOF
-
-vector16=no
-if compile_prog "" "" ; then
- vector16=yes
-fi
-
-########################################
# See if __attribute__((alias)) is supported.
# This false for Xcode 9, but has been remedied for Xcode 10.
# Unfortunately, travis uses Xcode 9 by default.
@@ -6590,6 +6591,7 @@
echo "smbd $smbd"
fi
echo "module support $modules"
+echo "alt path mod load $module_upgrades"
echo "host CPU $cpu"
echo "host big endian $bigendian"
echo "target list $target_list"
@@ -6717,6 +6719,7 @@
echo "tcmalloc support $tcmalloc"
echo "jemalloc support $jemalloc"
echo "avx2 optimization $avx2_opt"
+echo "avx512f optimization $avx512f_opt"
echo "replication support $replication"
echo "VxHS block device $vxhs"
echo "bochs support $bochs"
@@ -6734,6 +6737,7 @@
echo "default devices $default_devices"
echo "plugin support $plugins"
echo "fuzzing support $fuzzing"
+echo "gdb $gdb_bin"
if test "$supported_cpu" = "no"; then
echo
@@ -6943,6 +6947,9 @@
echo "CONFIG_STAMP=_$( (echo $qemu_version; echo $pkgversion; cat $0) | $shacmd - | cut -f1 -d\ )" >> $config_host_mak
echo "CONFIG_MODULES=y" >> $config_host_mak
fi
+if test "$module_upgrades" = "yes"; then
+ echo "CONFIG_MODULE_UPGRADES=y" >> $config_host_mak
+fi
if test "$have_x11" = "yes" && test "$need_x11" = "yes"; then
echo "CONFIG_X11=y" >> $config_host_mak
echo "X11_CFLAGS=$x11_cflags" >> $config_host_mak
@@ -7268,6 +7275,10 @@
echo "CONFIG_AVX2_OPT=y" >> $config_host_mak
fi
+if test "$avx512f_opt" = "yes" ; then
+ echo "CONFIG_AVX512F_OPT=y" >> $config_host_mak
+fi
+
if test "$lzo" = "yes" ; then
echo "CONFIG_LZO=y" >> $config_host_mak
fi
@@ -7383,10 +7394,6 @@
echo "CONFIG_ATOMIC64=y" >> $config_host_mak
fi
-if test "$vector16" = "yes" ; then
- echo "CONFIG_VECTOR16=y" >> $config_host_mak
-fi
-
if test "$attralias" = "yes" ; then
echo "CONFIG_ATTRIBUTE_ALIAS=y" >> $config_host_mak
fi
@@ -7608,6 +7615,10 @@
fi
fi
+if test -n "$gdb_bin" ; then
+ echo "HAVE_GDB_BIN=$gdb_bin" >> $config_host_mak
+fi
+
if test "$tcg_interpreter" = "yes"; then
QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/tci $QEMU_INCLUDES"
elif test "$ARCH" = "sparc64" ; then
diff --git a/contrib/libvhost-user/libvhost-user.h b/contrib/libvhost-user/libvhost-user.h
index 6fc8000..f30394f 100644
--- a/contrib/libvhost-user/libvhost-user.h
+++ b/contrib/libvhost-user/libvhost-user.h
@@ -286,7 +286,7 @@
uint16_t used_idx;
/* Used to track the state of each descriptor in descriptor table */
- VuDescStateSplit desc[0];
+ VuDescStateSplit desc[];
} VuVirtqInflight;
typedef struct VuVirtqInflightDesc {
diff --git a/contrib/vhost-user-gpu/Makefile.objs b/contrib/vhost-user-gpu/Makefile.objs
index 6170c91..0929609 100644
--- a/contrib/vhost-user-gpu/Makefile.objs
+++ b/contrib/vhost-user-gpu/Makefile.objs
@@ -1,7 +1,7 @@
-vhost-user-gpu-obj-y = main.o virgl.o vugbm.o
+vhost-user-gpu-obj-y = vhost-user-gpu.o virgl.o vugbm.o
-main.o-cflags := $(PIXMAN_CFLAGS) $(GBM_CFLAGS)
-main.o-libs := $(PIXMAN_LIBS)
+vhost-user-gpu.o-cflags := $(PIXMAN_CFLAGS) $(GBM_CFLAGS)
+vhost-user-gpu.o-libs := $(PIXMAN_LIBS)
virgl.o-cflags := $(VIRGL_CFLAGS) $(GBM_CFLAGS)
virgl.o-libs := $(VIRGL_LIBS)
diff --git a/contrib/vhost-user-gpu/main.c b/contrib/vhost-user-gpu/vhost-user-gpu.c
similarity index 100%
rename from contrib/vhost-user-gpu/main.c
rename to contrib/vhost-user-gpu/vhost-user-gpu.c
diff --git a/cpus.c b/cpus.c
index b4f8b84..ef441bd 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1026,9 +1026,9 @@
int ret = 0;
if (runstate_is_running()) {
+ runstate_set(state);
cpu_disable_ticks();
pause_all_vcpus();
- runstate_set(state);
vm_state_notify(0, state);
if (send_stop) {
qapi_event_send_stop();
@@ -1899,6 +1899,10 @@
{
CPUState *cpu;
+ if (!runstate_is_running()) {
+ return;
+ }
+
qemu_clock_enable(QEMU_CLOCK_VIRTUAL, true);
CPU_FOREACH(cpu) {
cpu_resume(cpu);
diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst
index 4016523..3b1b660 100644
--- a/docs/interop/vhost-user.rst
+++ b/docs/interop/vhost-user.rst
@@ -568,7 +568,7 @@
uint16_t used_idx;
/* Used to track the state of each descriptor in descriptor table */
- DescStateSplit desc[0];
+ DescStateSplit desc[];
} QueueRegionSplit;
To track inflight I/O, the queue region should be processed as follows:
@@ -690,7 +690,7 @@
uint8_t padding[7];
/* Used to track the state of each descriptor fetched from descriptor ring */
- DescStatePacked desc[0];
+ DescStatePacked desc[];
} QueueRegionPacked;
To track inflight I/O, the queue region should be processed as follows:
diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc
index cbad930..9a23278 100644
--- a/docs/system/cpu-models-x86.rst.inc
+++ b/docs/system/cpu-models-x86.rst.inc
@@ -49,10 +49,15 @@
compatibility is required, use the newest CPU model that is compatible
across all desired hosts.
-``Skylake-Server``, ``Skylake-Server-IBRS``
+``Cascadelake-Server``, ``Cascadelake-Server-noTSX``
+ Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6
+ or 7 only. (The Cascade Lake Xeon processor with *stepping 5 is
+ vulnerable to MDS variants*.)
+
+``Skylake-Server``, ``Skylake-Server-IBRS``, ``Skylake-Server-IBRS-noTSX``
Intel Xeon Processor (Skylake, 2016)
-``Skylake-Client``, ``Skylake-Client-IBRS``
+``Skylake-Client``, ``Skylake-Client-IBRS``, ``Skylake-Client-noTSX-IBRS}``
Intel Core Processor (Skylake, 2015)
``Broadwell``, ``Broadwell-IBRS``, ``Broadwell-noTSX``, ``Broadwell-noTSX-IBRS``
@@ -148,6 +153,54 @@
Requires the host CPU microcode to support this feature before it
can be used for guest CPUs.
+``mds-no``
+ Recommended to inform the guest OS that the host is *not* vulnerable
+ to any of the MDS variants ([MFBDS] CVE-2018-12130, [MLPDS]
+ CVE-2018-12127, [MSBDS] CVE-2018-12126).
+
+ This is an MSR (Model-Specific Register) feature rather than a CPUID feature,
+ so it will not appear in the Linux ``/proc/cpuinfo`` in the host or
+ guest. Instead, the host kernel uses it to populate the MDS
+ vulnerability file in ``sysfs``.
+
+ So it should only be enabled for VMs if the host reports @code{Not
+ affected} in the ``/sys/devices/system/cpu/vulnerabilities/mds`` file.
+
+``taa-no``
+ Recommended to inform that the guest that the host is ``not``
+ vulnerable to CVE-2019-11135, TSX Asynchronous Abort (TAA).
+
+ This too is an MSR feature, so it does not show up in the Linux
+ ``/proc/cpuinfo`` in the host or guest.
+
+ It should only be enabled for VMs if the host reports ``Not affected``
+ in the ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort``
+ file.
+
+``tsx-ctrl``
+ Recommended to inform the guest that it can disable the Intel TSX
+ (Transactional Synchronization Extensions) feature; or, if the
+ processor is vulnerable, use the Intel VERW instruction (a
+ processor-level instruction that performs checks on memory access) as
+ a mitigation for the TAA vulnerability. (For details, refer to
+ Intel's `deep dive into MDS
+ <https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling>`_.)
+
+ Expose this to the guest OS if and only if: (a) the host has TSX
+ enabled; *and* (b) the guest has ``rtm`` CPU flag enabled.
+
+ By disabling TSX, KVM-based guests can avoid paying the price of
+ mitigating TSX-based attacks.
+
+ Note that ``tsx-ctrl`` too is an MSR feature, so it does not show
+ up in the Linux ``/proc/cpuinfo`` in the host or guest.
+
+ To validate that Intel TSX is indeed disabled for the guest, there are
+ two ways: (a) check for the *absence* of ``rtm`` in the guest's
+ ``/proc/cpuinfo``; or (b) the
+ ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` file in
+ the guest should report ``Mitigation: TSX disabled``.
+
Preferred CPU models for AMD x86 hosts
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index bfc693e..c633fe2 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -329,6 +329,13 @@
``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
+``compat`` property of server class POWER CPUs (since 5.0)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The ``compat`` property used to set backwards compatibility modes for
+the processor has been deprecated. The ``max-cpu-compat`` property of
+the ``pseries`` machine type should be used instead.
+
System emulator devices
-----------------------
diff --git a/exec.c b/exec.c
index 0cc500d..de9d949 100644
--- a/exec.c
+++ b/exec.c
@@ -1315,7 +1315,7 @@
unsigned client)
{
DirtyMemoryBlocks *blocks;
- unsigned long end, page;
+ unsigned long end, page, start_page;
bool dirty = false;
RAMBlock *ramblock;
uint64_t mr_offset, mr_size;
@@ -1325,7 +1325,8 @@
}
end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
- page = start >> TARGET_PAGE_BITS;
+ start_page = start >> TARGET_PAGE_BITS;
+ page = start_page;
WITH_RCU_READ_LOCK_GUARD() {
blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
@@ -1345,8 +1346,8 @@
page += num;
}
- mr_offset = (ram_addr_t)(page << TARGET_PAGE_BITS) - ramblock->offset;
- mr_size = (end - page) << TARGET_PAGE_BITS;
+ mr_offset = (ram_addr_t)(start_page << TARGET_PAGE_BITS) - ramblock->offset;
+ mr_size = (end - start_page) << TARGET_PAGE_BITS;
memory_region_clear_dirty_bitmap(ramblock->mr, mr_offset, mr_size);
}
diff --git a/gdbstub.c b/gdbstub.c
index 22a2d63..013fb1a 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -319,8 +319,8 @@
typedef struct GDBRegisterState {
int base_reg;
int num_regs;
- gdb_reg_cb get_reg;
- gdb_reg_cb set_reg;
+ gdb_get_reg_cb get_reg;
+ gdb_set_reg_cb set_reg;
const char *xml;
struct GDBRegisterState *next;
} GDBRegisterState;
@@ -342,6 +342,7 @@
RS_CHKSUM2,
};
typedef struct GDBState {
+ bool init; /* have we been initialised? */
CPUState *c_cpu; /* current CPU for step/continue ops */
CPUState *g_cpu; /* current CPU for other ops */
CPUState *query_cpu; /* for q{f|s}ThreadInfo */
@@ -350,8 +351,7 @@
int line_buf_index;
int line_sum; /* running checksum */
int line_csum; /* checksum at the end of the packet */
- uint8_t last_packet[MAX_PACKET_LENGTH + 4];
- int last_packet_len;
+ GByteArray *last_packet;
int signal;
#ifdef CONFIG_USER_ONLY
int fd;
@@ -365,6 +365,8 @@
int process_num;
char syscall_buf[256];
gdb_syscall_complete_cb current_syscall_cb;
+ GString *str_buf;
+ GByteArray *mem_buf;
} GDBState;
/* By default use no IRQs and no timers while single stepping so as to
@@ -372,7 +374,26 @@
*/
static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
-static GDBState *gdbserver_state;
+static GDBState gdbserver_state;
+
+static void init_gdbserver_state(void)
+{
+ g_assert(!gdbserver_state.init);
+ memset(&gdbserver_state, 0, sizeof(GDBState));
+ gdbserver_state.init = true;
+ gdbserver_state.str_buf = g_string_new(NULL);
+ gdbserver_state.mem_buf = g_byte_array_sized_new(MAX_PACKET_LENGTH);
+ gdbserver_state.last_packet = g_byte_array_sized_new(MAX_PACKET_LENGTH + 4);
+}
+
+#ifndef CONFIG_USER_ONLY
+static void reset_gdbserver_state(void)
+{
+ g_free(gdbserver_state.processes);
+ gdbserver_state.processes = NULL;
+ gdbserver_state.process_num = 0;
+}
+#endif
bool gdb_has_xml;
@@ -380,21 +401,21 @@
/* XXX: This is not thread safe. Do we care? */
static int gdbserver_fd = -1;
-static int get_char(GDBState *s)
+static int get_char(void)
{
uint8_t ch;
int ret;
for(;;) {
- ret = qemu_recv(s->fd, &ch, 1, 0);
+ ret = qemu_recv(gdbserver_state.fd, &ch, 1, 0);
if (ret < 0) {
if (errno == ECONNRESET)
- s->fd = -1;
+ gdbserver_state.fd = -1;
if (errno != EINTR)
return -1;
} else if (ret == 0) {
- close(s->fd);
- s->fd = -1;
+ close(gdbserver_state.fd);
+ gdbserver_state.fd = -1;
return -1;
} else {
break;
@@ -425,18 +446,18 @@
/* -semihosting-config target=auto */
/* On the first call check if gdb is connected and remember. */
if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
- gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
- : GDB_SYS_DISABLED);
+ gdb_syscall_mode = gdbserver_state.init ?
+ GDB_SYS_ENABLED : GDB_SYS_DISABLED;
}
return gdb_syscall_mode == GDB_SYS_ENABLED;
}
/* Resume execution. */
-static inline void gdb_continue(GDBState *s)
+static inline void gdb_continue(void)
{
#ifdef CONFIG_USER_ONLY
- s->running_state = 1;
+ gdbserver_state.running_state = 1;
trace_gdbstub_op_continue();
#else
if (!runstate_needs_reset()) {
@@ -450,7 +471,7 @@
* Resume execution, per CPU actions. For user-mode emulation it's
* equivalent to gdb_continue.
*/
-static int gdb_continue_partial(GDBState *s, char *newstates)
+static int gdb_continue_partial(char *newstates)
{
CPUState *cpu;
int res = 0;
@@ -465,7 +486,7 @@
cpu_single_step(cpu, sstep_flags);
}
}
- s->running_state = 1;
+ gdbserver_state.running_state = 1;
#else
int flag = 0;
@@ -503,13 +524,13 @@
return res;
}
-static void put_buffer(GDBState *s, const uint8_t *buf, int len)
+static void put_buffer(const uint8_t *buf, int len)
{
#ifdef CONFIG_USER_ONLY
int ret;
while (len > 0) {
- ret = send(s->fd, buf, len, 0);
+ ret = send(gdbserver_state.fd, buf, len, 0);
if (ret < 0) {
if (errno != EINTR)
return;
@@ -521,7 +542,7 @@
#else
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, buf, len);
+ qemu_chr_fe_write_all(&gdbserver_state.chr, buf, len);
#endif
}
@@ -546,25 +567,24 @@
}
/* writes 2*len+1 bytes in buf */
-static void memtohex(char *buf, const uint8_t *mem, int len)
+static void memtohex(GString *buf, const uint8_t *mem, int len)
{
int i, c;
- char *q;
- q = buf;
for(i = 0; i < len; i++) {
c = mem[i];
- *q++ = tohex(c >> 4);
- *q++ = tohex(c & 0xf);
+ g_string_append_c(buf, tohex(c >> 4));
+ g_string_append_c(buf, tohex(c & 0xf));
}
- *q = '\0';
+ g_string_append_c(buf, '\0');
}
-static void hextomem(uint8_t *mem, const char *buf, int len)
+static void hextomem(GByteArray *mem, const char *buf, int len)
{
int i;
for(i = 0; i < len; i++) {
- mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
+ guint8 byte = fromhex(buf[0]) << 4 | fromhex(buf[1]);
+ g_byte_array_append(mem, &byte, 1);
buf += 2;
}
}
@@ -603,33 +623,35 @@
}
/* return -1 if error, 0 if OK */
-static int put_packet_binary(GDBState *s, const char *buf, int len, bool dump)
+static int put_packet_binary(const char *buf, int len, bool dump)
{
int csum, i;
- uint8_t *p;
+ uint8_t footer[3];
if (dump && trace_event_get_state_backends(TRACE_GDBSTUB_IO_BINARYREPLY)) {
hexdump(buf, len, trace_gdbstub_io_binaryreply);
}
for(;;) {
- p = s->last_packet;
- *(p++) = '$';
- memcpy(p, buf, len);
- p += len;
+ g_byte_array_set_size(gdbserver_state.last_packet, 0);
+ g_byte_array_append(gdbserver_state.last_packet,
+ (const uint8_t *) "$", 1);
+ g_byte_array_append(gdbserver_state.last_packet,
+ (const uint8_t *) buf, len);
csum = 0;
for(i = 0; i < len; i++) {
csum += buf[i];
}
- *(p++) = '#';
- *(p++) = tohex((csum >> 4) & 0xf);
- *(p++) = tohex((csum) & 0xf);
+ footer[0] = '#';
+ footer[1] = tohex((csum >> 4) & 0xf);
+ footer[2] = tohex((csum) & 0xf);
+ g_byte_array_append(gdbserver_state.last_packet, footer, 3);
- s->last_packet_len = p - s->last_packet;
- put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
+ put_buffer(gdbserver_state.last_packet->data,
+ gdbserver_state.last_packet->len);
#ifdef CONFIG_USER_ONLY
- i = get_char(s);
+ i = get_char();
if (i < 0)
return -1;
if (i == '+')
@@ -642,65 +664,69 @@
}
/* return -1 if error, 0 if OK */
-static int put_packet(GDBState *s, const char *buf)
+static int put_packet(const char *buf)
{
trace_gdbstub_io_reply(buf);
- return put_packet_binary(s, buf, strlen(buf), false);
+ return put_packet_binary(buf, strlen(buf), false);
+}
+
+static void put_strbuf(void)
+{
+ put_packet(gdbserver_state.str_buf->str);
}
/* Encode data using the encoding for 'x' packets. */
-static int memtox(char *buf, const char *mem, int len)
+static void memtox(GString *buf, const char *mem, int len)
{
- char *p = buf;
char c;
while (len--) {
c = *(mem++);
switch (c) {
case '#': case '$': case '*': case '}':
- *(p++) = '}';
- *(p++) = c ^ 0x20;
+ g_string_append_c(buf, '}');
+ g_string_append_c(buf, c ^ 0x20);
break;
default:
- *(p++) = c;
+ g_string_append_c(buf, c);
break;
}
}
- return p - buf;
}
-static uint32_t gdb_get_cpu_pid(const GDBState *s, CPUState *cpu)
+static uint32_t gdb_get_cpu_pid(CPUState *cpu)
{
/* TODO: In user mode, we should use the task state PID */
if (cpu->cluster_index == UNASSIGNED_CLUSTER_INDEX) {
/* Return the default process' PID */
- return s->processes[s->process_num - 1].pid;
+ int index = gdbserver_state.process_num - 1;
+ return gdbserver_state.processes[index].pid;
}
return cpu->cluster_index + 1;
}
-static GDBProcess *gdb_get_process(const GDBState *s, uint32_t pid)
+static GDBProcess *gdb_get_process(uint32_t pid)
{
int i;
if (!pid) {
/* 0 means any process, we take the first one */
- return &s->processes[0];
+ return &gdbserver_state.processes[0];
}
- for (i = 0; i < s->process_num; i++) {
- if (s->processes[i].pid == pid) {
- return &s->processes[i];
+ for (i = 0; i < gdbserver_state.process_num; i++) {
+ if (gdbserver_state.processes[i].pid == pid) {
+ return &gdbserver_state.processes[i];
}
}
return NULL;
}
-static GDBProcess *gdb_get_cpu_process(const GDBState *s, CPUState *cpu)
+static GDBProcess *gdb_get_cpu_process(CPUState *cpu)
{
- return gdb_get_process(s, gdb_get_cpu_pid(s, cpu));
+ return gdb_get_process(gdb_get_cpu_pid(cpu));
}
static CPUState *find_cpu(uint32_t thread_id)
@@ -716,13 +742,12 @@
return NULL;
}
-static CPUState *get_first_cpu_in_process(const GDBState *s,
- GDBProcess *process)
+static CPUState *get_first_cpu_in_process(GDBProcess *process)
{
CPUState *cpu;
CPU_FOREACH(cpu) {
- if (gdb_get_cpu_pid(s, cpu) == process->pid) {
+ if (gdb_get_cpu_pid(cpu) == process->pid) {
return cpu;
}
}
@@ -730,13 +755,13 @@
return NULL;
}
-static CPUState *gdb_next_cpu_in_process(const GDBState *s, CPUState *cpu)
+static CPUState *gdb_next_cpu_in_process(CPUState *cpu)
{
- uint32_t pid = gdb_get_cpu_pid(s, cpu);
+ uint32_t pid = gdb_get_cpu_pid(cpu);
cpu = CPU_NEXT(cpu);
while (cpu) {
- if (gdb_get_cpu_pid(s, cpu) == pid) {
+ if (gdb_get_cpu_pid(cpu) == pid) {
break;
}
@@ -747,12 +772,12 @@
}
/* Return the cpu following @cpu, while ignoring unattached processes. */
-static CPUState *gdb_next_attached_cpu(const GDBState *s, CPUState *cpu)
+static CPUState *gdb_next_attached_cpu(CPUState *cpu)
{
cpu = CPU_NEXT(cpu);
while (cpu) {
- if (gdb_get_cpu_process(s, cpu)->attached) {
+ if (gdb_get_cpu_process(cpu)->attached) {
break;
}
@@ -763,29 +788,29 @@
}
/* Return the first attached cpu */
-static CPUState *gdb_first_attached_cpu(const GDBState *s)
+static CPUState *gdb_first_attached_cpu(void)
{
CPUState *cpu = first_cpu;
- GDBProcess *process = gdb_get_cpu_process(s, cpu);
+ GDBProcess *process = gdb_get_cpu_process(cpu);
if (!process->attached) {
- return gdb_next_attached_cpu(s, cpu);
+ return gdb_next_attached_cpu(cpu);
}
return cpu;
}
-static CPUState *gdb_get_cpu(const GDBState *s, uint32_t pid, uint32_t tid)
+static CPUState *gdb_get_cpu(uint32_t pid, uint32_t tid)
{
GDBProcess *process;
CPUState *cpu;
if (!pid && !tid) {
/* 0 means any process/thread, we take the first attached one */
- return gdb_first_attached_cpu(s);
+ return gdb_first_attached_cpu();
} else if (pid && !tid) {
/* any thread in a specific process */
- process = gdb_get_process(s, pid);
+ process = gdb_get_process(pid);
if (process == NULL) {
return NULL;
@@ -795,7 +820,7 @@
return NULL;
}
- return get_first_cpu_in_process(s, process);
+ return get_first_cpu_in_process(process);
} else {
/* a specific thread */
cpu = find_cpu(tid);
@@ -804,7 +829,7 @@
return NULL;
}
- process = gdb_get_cpu_process(s, cpu);
+ process = gdb_get_cpu_process(cpu);
if (pid && process->pid != pid) {
return NULL;
@@ -818,13 +843,13 @@
}
}
-static const char *get_feature_xml(const GDBState *s, const char *p,
- const char **newp, GDBProcess *process)
+static const char *get_feature_xml(const char *p, const char **newp,
+ GDBProcess *process)
{
size_t len;
int i;
const char *name;
- CPUState *cpu = get_first_cpu_in_process(s, process);
+ CPUState *cpu = get_first_cpu_in_process(process);
CPUClass *cc = CPU_GET_CLASS(cpu);
len = 0;
@@ -881,19 +906,19 @@
return name ? xml_builtin[i][1] : NULL;
}
-static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
+static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
CPUArchState *env = cpu->env_ptr;
GDBRegisterState *r;
if (reg < cc->gdb_num_core_regs) {
- return cc->gdb_read_register(cpu, mem_buf, reg);
+ return cc->gdb_read_register(cpu, buf, reg);
}
for (r = cpu->gdb_regs; r; r = r->next) {
if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
- return r->get_reg(env, mem_buf, reg - r->base_reg);
+ return r->get_reg(env, buf, reg - r->base_reg);
}
}
return 0;
@@ -924,7 +949,7 @@
*/
void gdb_register_coprocessor(CPUState *cpu,
- gdb_reg_cb get_reg, gdb_reg_cb set_reg,
+ gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
int num_regs, const char *xml, int g_pos)
{
GDBRegisterState *s;
@@ -984,7 +1009,7 @@
int err = 0;
if (kvm_enabled()) {
- return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
+ return kvm_insert_breakpoint(gdbserver_state.c_cpu, addr, len, type);
}
switch (type) {
@@ -1021,7 +1046,7 @@
int err = 0;
if (kvm_enabled()) {
- return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
+ return kvm_remove_breakpoint(gdbserver_state.c_cpu, addr, len, type);
}
switch (type) {
@@ -1059,13 +1084,13 @@
#endif
}
-static void gdb_process_breakpoint_remove_all(const GDBState *s, GDBProcess *p)
+static void gdb_process_breakpoint_remove_all(GDBProcess *p)
{
- CPUState *cpu = get_first_cpu_in_process(s, p);
+ CPUState *cpu = get_first_cpu_in_process(p);
while (cpu) {
gdb_cpu_breakpoint_remove_all(cpu);
- cpu = gdb_next_cpu_in_process(s, cpu);
+ cpu = gdb_next_cpu_in_process(cpu);
}
}
@@ -1074,7 +1099,7 @@
CPUState *cpu;
if (kvm_enabled()) {
- kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
+ kvm_remove_all_breakpoints(gdbserver_state.c_cpu);
return;
}
@@ -1083,25 +1108,22 @@
}
}
-static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
+static void gdb_set_cpu_pc(target_ulong pc)
{
- CPUState *cpu = s->c_cpu;
+ CPUState *cpu = gdbserver_state.c_cpu;
cpu_synchronize_state(cpu);
cpu_set_pc(cpu, pc);
}
-static char *gdb_fmt_thread_id(const GDBState *s, CPUState *cpu,
- char *buf, size_t buf_size)
+static void gdb_append_thread_id(CPUState *cpu, GString *buf)
{
- if (s->multiprocess) {
- snprintf(buf, buf_size, "p%02x.%02x",
- gdb_get_cpu_pid(s, cpu), cpu_gdb_index(cpu));
+ if (gdbserver_state.multiprocess) {
+ g_string_append_printf(buf, "p%02x.%02x",
+ gdb_get_cpu_pid(cpu), cpu_gdb_index(cpu));
} else {
- snprintf(buf, buf_size, "%02x", cpu_gdb_index(cpu));
+ g_string_append_printf(buf, "%02x", cpu_gdb_index(cpu));
}
-
- return buf;
}
typedef enum GDBThreadIdKind {
@@ -1163,7 +1185,7 @@
* returns -ENOTSUP if a command is unsupported, -EINVAL or -ERANGE if there is
* a format error, 0 on success.
*/
-static int gdb_handle_vcont(GDBState *s, const char *p)
+static int gdb_handle_vcont(const char *p)
{
int res, signal = 0;
char cur_action;
@@ -1238,36 +1260,36 @@
goto out;
case GDB_ALL_PROCESSES:
- cpu = gdb_first_attached_cpu(s);
+ cpu = gdb_first_attached_cpu();
while (cpu) {
if (newstates[cpu->cpu_index] == 1) {
newstates[cpu->cpu_index] = cur_action;
}
- cpu = gdb_next_attached_cpu(s, cpu);
+ cpu = gdb_next_attached_cpu(cpu);
}
break;
case GDB_ALL_THREADS:
- process = gdb_get_process(s, pid);
+ process = gdb_get_process(pid);
if (!process->attached) {
res = -EINVAL;
goto out;
}
- cpu = get_first_cpu_in_process(s, process);
+ cpu = get_first_cpu_in_process(process);
while (cpu) {
if (newstates[cpu->cpu_index] == 1) {
newstates[cpu->cpu_index] = cur_action;
}
- cpu = gdb_next_cpu_in_process(s, cpu);
+ cpu = gdb_next_cpu_in_process(cpu);
}
break;
case GDB_ONE_THREAD:
- cpu = gdb_get_cpu(s, pid, tid);
+ cpu = gdb_get_cpu(pid, tid);
/* invalid CPU/thread specified */
if (!cpu) {
@@ -1282,8 +1304,8 @@
break;
}
}
- s->signal = signal;
- gdb_continue_partial(s, newstates);
+ gdbserver_state.signal = signal;
+ gdb_continue_partial(newstates);
out:
g_free(newstates);
@@ -1392,11 +1414,8 @@
}
typedef struct GdbCmdContext {
- GDBState *s;
GdbCmdVariant *params;
int num_params;
- uint8_t mem_buf[MAX_PACKET_LENGTH];
- char str_buf[MAX_PACKET_LENGTH + 1];
} GdbCmdContext;
typedef void (*GdbCmdHandler)(GdbCmdContext *gdb_ctx, void *user_ctx);
@@ -1436,7 +1455,7 @@
return !strncmp(string, pattern, strlen(pattern));
}
-static int process_string_cmd(GDBState *s, void *user_ctx, const char *data,
+static int process_string_cmd(void *user_ctx, const char *data,
const GdbCmdParseEntry *cmds, int num_cmds)
{
int i, schema_len, max_num_params = 0;
@@ -1473,7 +1492,6 @@
return -1;
}
- gdb_ctx.s = s;
cmd->handler(&gdb_ctx, user_ctx);
return 0;
}
@@ -1481,53 +1499,54 @@
return -1;
}
-static void run_cmd_parser(GDBState *s, const char *data,
- const GdbCmdParseEntry *cmd)
+static void run_cmd_parser(const char *data, const GdbCmdParseEntry *cmd)
{
if (!data) {
return;
}
+ g_string_set_size(gdbserver_state.str_buf, 0);
+ g_byte_array_set_size(gdbserver_state.mem_buf, 0);
+
/* In case there was an error during the command parsing we must
* send a NULL packet to indicate the command is not supported */
- if (process_string_cmd(s, NULL, data, cmd, 1)) {
- put_packet(s, "");
+ if (process_string_cmd(NULL, data, cmd, 1)) {
+ put_packet("");
}
}
static void handle_detach(GdbCmdContext *gdb_ctx, void *user_ctx)
{
GDBProcess *process;
- GDBState *s = gdb_ctx->s;
uint32_t pid = 1;
- if (s->multiprocess) {
+ if (gdbserver_state.multiprocess) {
if (!gdb_ctx->num_params) {
- put_packet(s, "E22");
+ put_packet("E22");
return;
}
pid = gdb_ctx->params[0].val_ul;
}
- process = gdb_get_process(s, pid);
- gdb_process_breakpoint_remove_all(s, process);
+ process = gdb_get_process(pid);
+ gdb_process_breakpoint_remove_all(process);
process->attached = false;
- if (pid == gdb_get_cpu_pid(s, s->c_cpu)) {
- s->c_cpu = gdb_first_attached_cpu(s);
+ if (pid == gdb_get_cpu_pid(gdbserver_state.c_cpu)) {
+ gdbserver_state.c_cpu = gdb_first_attached_cpu();
}
- if (pid == gdb_get_cpu_pid(s, s->g_cpu)) {
- s->g_cpu = gdb_first_attached_cpu(s);
+ if (pid == gdb_get_cpu_pid(gdbserver_state.g_cpu)) {
+ gdbserver_state.g_cpu = gdb_first_attached_cpu();
}
- if (!s->c_cpu) {
+ if (!gdbserver_state.c_cpu) {
/* No more process attached */
gdb_syscall_mode = GDB_SYS_DISABLED;
- gdb_continue(s);
+ gdb_continue();
}
- put_packet(s, "OK");
+ put_packet("OK");
}
static void handle_thread_alive(GdbCmdContext *gdb_ctx, void *user_ctx)
@@ -1535,33 +1554,33 @@
CPUState *cpu;
if (!gdb_ctx->num_params) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
if (gdb_ctx->params[0].thread_id.kind == GDB_READ_THREAD_ERR) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
- cpu = gdb_get_cpu(gdb_ctx->s, gdb_ctx->params[0].thread_id.pid,
+ cpu = gdb_get_cpu(gdb_ctx->params[0].thread_id.pid,
gdb_ctx->params[0].thread_id.tid);
if (!cpu) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
}
static void handle_continue(GdbCmdContext *gdb_ctx, void *user_ctx)
{
if (gdb_ctx->num_params) {
- gdb_set_cpu_pc(gdb_ctx->s, gdb_ctx->params[0].val_ull);
+ gdb_set_cpu_pc(gdb_ctx->params[0].val_ull);
}
- gdb_ctx->s->signal = 0;
- gdb_continue(gdb_ctx->s);
+ gdbserver_state.signal = 0;
+ gdb_continue();
}
static void handle_cont_with_sig(GdbCmdContext *gdb_ctx, void *user_ctx)
@@ -1576,11 +1595,11 @@
signal = gdb_ctx->params[0].val_ul;
}
- gdb_ctx->s->signal = gdb_signal_to_target(signal);
- if (gdb_ctx->s->signal == -1) {
- gdb_ctx->s->signal = 0;
+ gdbserver_state.signal = gdb_signal_to_target(signal);
+ if (gdbserver_state.signal == -1) {
+ gdbserver_state.signal = 0;
}
- gdb_continue(gdb_ctx->s);
+ gdb_continue();
}
static void handle_set_thread(GdbCmdContext *gdb_ctx, void *user_ctx)
@@ -1588,24 +1607,24 @@
CPUState *cpu;
if (gdb_ctx->num_params != 2) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
if (gdb_ctx->params[1].thread_id.kind == GDB_READ_THREAD_ERR) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
if (gdb_ctx->params[1].thread_id.kind != GDB_ONE_THREAD) {
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
return;
}
- cpu = gdb_get_cpu(gdb_ctx->s, gdb_ctx->params[1].thread_id.pid,
+ cpu = gdb_get_cpu(gdb_ctx->params[1].thread_id.pid,
gdb_ctx->params[1].thread_id.tid);
if (!cpu) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
@@ -1615,15 +1634,15 @@
*/
switch (gdb_ctx->params[0].opcode) {
case 'c':
- gdb_ctx->s->c_cpu = cpu;
- put_packet(gdb_ctx->s, "OK");
+ gdbserver_state.c_cpu = cpu;
+ put_packet("OK");
break;
case 'g':
- gdb_ctx->s->g_cpu = cpu;
- put_packet(gdb_ctx->s, "OK");
+ gdbserver_state.g_cpu = cpu;
+ put_packet("OK");
break;
default:
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
break;
}
}
@@ -1633,7 +1652,7 @@
int res;
if (gdb_ctx->num_params != 3) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
@@ -1641,14 +1660,14 @@
gdb_ctx->params[1].val_ull,
gdb_ctx->params[2].val_ull);
if (res >= 0) {
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
return;
} else if (res == -ENOSYS) {
- put_packet(gdb_ctx->s, "");
+ put_packet("");
return;
}
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
}
static void handle_remove_bp(GdbCmdContext *gdb_ctx, void *user_ctx)
@@ -1656,7 +1675,7 @@
int res;
if (gdb_ctx->num_params != 3) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
@@ -1664,14 +1683,14 @@
gdb_ctx->params[1].val_ull,
gdb_ctx->params[2].val_ull);
if (res >= 0) {
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
return;
} else if (res == -ENOSYS) {
- put_packet(gdb_ctx->s, "");
+ put_packet("");
return;
}
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
}
/*
@@ -1690,20 +1709,20 @@
int reg_size;
if (!gdb_has_xml) {
- put_packet(gdb_ctx->s, "");
+ put_packet("");
return;
}
if (gdb_ctx->num_params != 2) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
reg_size = strlen(gdb_ctx->params[1].data) / 2;
- hextomem(gdb_ctx->mem_buf, gdb_ctx->params[1].data, reg_size);
- gdb_write_register(gdb_ctx->s->g_cpu, gdb_ctx->mem_buf,
+ hextomem(gdbserver_state.mem_buf, gdb_ctx->params[1].data, reg_size);
+ gdb_write_register(gdbserver_state.g_cpu, gdbserver_state.mem_buf->data,
gdb_ctx->params[0].val_ull);
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
}
static void handle_get_reg(GdbCmdContext *gdb_ctx, void *user_ctx)
@@ -1711,73 +1730,79 @@
int reg_size;
if (!gdb_has_xml) {
- put_packet(gdb_ctx->s, "");
+ put_packet("");
return;
}
if (!gdb_ctx->num_params) {
- put_packet(gdb_ctx->s, "E14");
+ put_packet("E14");
return;
}
- reg_size = gdb_read_register(gdb_ctx->s->g_cpu, gdb_ctx->mem_buf,
+ reg_size = gdb_read_register(gdbserver_state.g_cpu,
+ gdbserver_state.mem_buf,
gdb_ctx->params[0].val_ull);
if (!reg_size) {
- put_packet(gdb_ctx->s, "E14");
+ put_packet("E14");
return;
+ } else {
+ g_byte_array_set_size(gdbserver_state.mem_buf, reg_size);
}
- memtohex(gdb_ctx->str_buf, gdb_ctx->mem_buf, reg_size);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, reg_size);
+ put_strbuf();
}
static void handle_write_mem(GdbCmdContext *gdb_ctx, void *user_ctx)
{
if (gdb_ctx->num_params != 3) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
/* hextomem() reads 2*len bytes */
if (gdb_ctx->params[1].val_ull > strlen(gdb_ctx->params[2].data) / 2) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
- hextomem(gdb_ctx->mem_buf, gdb_ctx->params[2].data,
+ hextomem(gdbserver_state.mem_buf, gdb_ctx->params[2].data,
gdb_ctx->params[1].val_ull);
- if (target_memory_rw_debug(gdb_ctx->s->g_cpu, gdb_ctx->params[0].val_ull,
- gdb_ctx->mem_buf,
- gdb_ctx->params[1].val_ull, true)) {
- put_packet(gdb_ctx->s, "E14");
+ if (target_memory_rw_debug(gdbserver_state.g_cpu, gdb_ctx->params[0].val_ull,
+ gdbserver_state.mem_buf->data,
+ gdbserver_state.mem_buf->len, true)) {
+ put_packet("E14");
return;
}
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
}
static void handle_read_mem(GdbCmdContext *gdb_ctx, void *user_ctx)
{
if (gdb_ctx->num_params != 2) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
/* memtohex() doubles the required space */
if (gdb_ctx->params[1].val_ull > MAX_PACKET_LENGTH / 2) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
- if (target_memory_rw_debug(gdb_ctx->s->g_cpu, gdb_ctx->params[0].val_ull,
- gdb_ctx->mem_buf,
- gdb_ctx->params[1].val_ull, false)) {
- put_packet(gdb_ctx->s, "E14");
+ g_byte_array_set_size(gdbserver_state.mem_buf, gdb_ctx->params[1].val_ull);
+
+ if (target_memory_rw_debug(gdbserver_state.g_cpu, gdb_ctx->params[0].val_ull,
+ gdbserver_state.mem_buf->data,
+ gdbserver_state.mem_buf->len, false)) {
+ put_packet("E14");
return;
}
- memtohex(gdb_ctx->str_buf, gdb_ctx->mem_buf, gdb_ctx->params[1].val_ull);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data,
+ gdbserver_state.mem_buf->len);
+ put_strbuf();
}
static void handle_write_all_regs(GdbCmdContext *gdb_ctx, void *user_ctx)
@@ -1790,37 +1815,40 @@
return;
}
- cpu_synchronize_state(gdb_ctx->s->g_cpu);
- registers = gdb_ctx->mem_buf;
+ cpu_synchronize_state(gdbserver_state.g_cpu);
len = strlen(gdb_ctx->params[0].data) / 2;
- hextomem(registers, gdb_ctx->params[0].data, len);
- for (addr = 0; addr < gdb_ctx->s->g_cpu->gdb_num_g_regs && len > 0;
+ hextomem(gdbserver_state.mem_buf, gdb_ctx->params[0].data, len);
+ registers = gdbserver_state.mem_buf->data;
+ for (addr = 0; addr < gdbserver_state.g_cpu->gdb_num_g_regs && len > 0;
addr++) {
- reg_size = gdb_write_register(gdb_ctx->s->g_cpu, registers, addr);
+ reg_size = gdb_write_register(gdbserver_state.g_cpu, registers, addr);
len -= reg_size;
registers += reg_size;
}
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
}
static void handle_read_all_regs(GdbCmdContext *gdb_ctx, void *user_ctx)
{
target_ulong addr, len;
- cpu_synchronize_state(gdb_ctx->s->g_cpu);
+ cpu_synchronize_state(gdbserver_state.g_cpu);
+ g_byte_array_set_size(gdbserver_state.mem_buf, 0);
len = 0;
- for (addr = 0; addr < gdb_ctx->s->g_cpu->gdb_num_g_regs; addr++) {
- len += gdb_read_register(gdb_ctx->s->g_cpu, gdb_ctx->mem_buf + len,
+ for (addr = 0; addr < gdbserver_state.g_cpu->gdb_num_g_regs; addr++) {
+ len += gdb_read_register(gdbserver_state.g_cpu,
+ gdbserver_state.mem_buf,
addr);
}
+ g_assert(len == gdbserver_state.mem_buf->len);
- memtohex(gdb_ctx->str_buf, gdb_ctx->mem_buf, len);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, len);
+ put_strbuf();
}
static void handle_file_io(GdbCmdContext *gdb_ctx, void *user_ctx)
{
- if (gdb_ctx->num_params >= 1 && gdb_ctx->s->current_syscall_cb) {
+ if (gdb_ctx->num_params >= 1 && gdbserver_state.current_syscall_cb) {
target_ulong ret, err;
ret = (target_ulong)gdb_ctx->params[0].val_ull;
@@ -1829,31 +1857,31 @@
} else {
err = 0;
}
- gdb_ctx->s->current_syscall_cb(gdb_ctx->s->c_cpu, ret, err);
- gdb_ctx->s->current_syscall_cb = NULL;
+ gdbserver_state.current_syscall_cb(gdbserver_state.c_cpu, ret, err);
+ gdbserver_state.current_syscall_cb = NULL;
}
if (gdb_ctx->num_params >= 3 && gdb_ctx->params[2].opcode == (uint8_t)'C') {
- put_packet(gdb_ctx->s, "T02");
+ put_packet("T02");
return;
}
- gdb_continue(gdb_ctx->s);
+ gdb_continue();
}
static void handle_step(GdbCmdContext *gdb_ctx, void *user_ctx)
{
if (gdb_ctx->num_params) {
- gdb_set_cpu_pc(gdb_ctx->s, (target_ulong)gdb_ctx->params[0].val_ull);
+ gdb_set_cpu_pc((target_ulong)gdb_ctx->params[0].val_ull);
}
- cpu_single_step(gdb_ctx->s->c_cpu, sstep_flags);
- gdb_continue(gdb_ctx->s);
+ cpu_single_step(gdbserver_state.c_cpu, sstep_flags);
+ gdb_continue();
}
static void handle_v_cont_query(GdbCmdContext *gdb_ctx, void *user_ctx)
{
- put_packet(gdb_ctx->s, "vCont;c;C;s;S");
+ put_packet("vCont;c;C;s;S");
}
static void handle_v_cont(GdbCmdContext *gdb_ctx, void *user_ctx)
@@ -1864,11 +1892,11 @@
return;
}
- res = gdb_handle_vcont(gdb_ctx->s, gdb_ctx->params[0].data);
+ res = gdb_handle_vcont(gdb_ctx->params[0].data);
if ((res == -EINVAL) || (res == -ERANGE)) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
} else if (res) {
- put_packet(gdb_ctx->s, "");
+ put_packet("");
}
}
@@ -1876,38 +1904,37 @@
{
GDBProcess *process;
CPUState *cpu;
- char thread_id[16];
- pstrcpy(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), "E22");
+ g_string_assign(gdbserver_state.str_buf, "E22");
if (!gdb_ctx->num_params) {
goto cleanup;
}
- process = gdb_get_process(gdb_ctx->s, gdb_ctx->params[0].val_ul);
+ process = gdb_get_process(gdb_ctx->params[0].val_ul);
if (!process) {
goto cleanup;
}
- cpu = get_first_cpu_in_process(gdb_ctx->s, process);
+ cpu = get_first_cpu_in_process(process);
if (!cpu) {
goto cleanup;
}
process->attached = true;
- gdb_ctx->s->g_cpu = cpu;
- gdb_ctx->s->c_cpu = cpu;
+ gdbserver_state.g_cpu = cpu;
+ gdbserver_state.c_cpu = cpu;
- gdb_fmt_thread_id(gdb_ctx->s, cpu, thread_id, sizeof(thread_id));
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), "T%02xthread:%s;",
- GDB_SIGNAL_TRAP, thread_id);
+ g_string_printf(gdbserver_state.str_buf, "T%02xthread:", GDB_SIGNAL_TRAP);
+ gdb_append_thread_id(cpu, gdbserver_state.str_buf);
+ g_string_append_c(gdbserver_state.str_buf, ';');
cleanup:
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ put_strbuf();
}
static void handle_v_kill(GdbCmdContext *gdb_ctx, void *user_ctx)
{
/* Kill the target */
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
error_report("QEMU: Terminated via GDBstub");
exit(0);
}
@@ -1944,19 +1971,18 @@
return;
}
- if (process_string_cmd(gdb_ctx->s, NULL, gdb_ctx->params[0].data,
+ if (process_string_cmd(NULL, gdb_ctx->params[0].data,
gdb_v_commands_table,
ARRAY_SIZE(gdb_v_commands_table))) {
- put_packet(gdb_ctx->s, "");
+ put_packet("");
}
}
static void handle_query_qemu_sstepbits(GdbCmdContext *gdb_ctx, void *user_ctx)
{
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf),
- "ENABLE=%x,NOIRQ=%x,NOTIMER=%x", SSTEP_ENABLE,
- SSTEP_NOIRQ, SSTEP_NOTIMER);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ g_string_printf(gdbserver_state.str_buf, "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
+ SSTEP_ENABLE, SSTEP_NOIRQ, SSTEP_NOTIMER);
+ put_strbuf();
}
static void handle_set_qemu_sstep(GdbCmdContext *gdb_ctx, void *user_ctx)
@@ -1966,68 +1992,63 @@
}
sstep_flags = gdb_ctx->params[0].val_ul;
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
}
static void handle_query_qemu_sstep(GdbCmdContext *gdb_ctx, void *user_ctx)
{
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), "0x%x", sstep_flags);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ g_string_printf(gdbserver_state.str_buf, "0x%x", sstep_flags);
+ put_strbuf();
}
static void handle_query_curr_tid(GdbCmdContext *gdb_ctx, void *user_ctx)
{
CPUState *cpu;
GDBProcess *process;
- char thread_id[16];
/*
* "Current thread" remains vague in the spec, so always return
* the first thread of the current process (gdb returns the
* first thread).
*/
- process = gdb_get_cpu_process(gdb_ctx->s, gdb_ctx->s->g_cpu);
- cpu = get_first_cpu_in_process(gdb_ctx->s, process);
- gdb_fmt_thread_id(gdb_ctx->s, cpu, thread_id, sizeof(thread_id));
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), "QC%s", thread_id);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ process = gdb_get_cpu_process(gdbserver_state.g_cpu);
+ cpu = get_first_cpu_in_process(process);
+ g_string_assign(gdbserver_state.str_buf, "QC");
+ gdb_append_thread_id(cpu, gdbserver_state.str_buf);
+ put_strbuf();
}
static void handle_query_threads(GdbCmdContext *gdb_ctx, void *user_ctx)
{
- char thread_id[16];
-
- if (!gdb_ctx->s->query_cpu) {
- put_packet(gdb_ctx->s, "l");
+ if (!gdbserver_state.query_cpu) {
+ put_packet("l");
return;
}
- gdb_fmt_thread_id(gdb_ctx->s, gdb_ctx->s->query_cpu, thread_id,
- sizeof(thread_id));
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), "m%s", thread_id);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
- gdb_ctx->s->query_cpu =
- gdb_next_attached_cpu(gdb_ctx->s, gdb_ctx->s->query_cpu);
+ g_string_assign(gdbserver_state.str_buf, "m");
+ gdb_append_thread_id(gdbserver_state.query_cpu, gdbserver_state.str_buf);
+ put_strbuf();
+ gdbserver_state.query_cpu = gdb_next_attached_cpu(gdbserver_state.query_cpu);
}
static void handle_query_first_threads(GdbCmdContext *gdb_ctx, void *user_ctx)
{
- gdb_ctx->s->query_cpu = gdb_first_attached_cpu(gdb_ctx->s);
+ gdbserver_state.query_cpu = gdb_first_attached_cpu();
handle_query_threads(gdb_ctx, user_ctx);
}
static void handle_query_thread_extra(GdbCmdContext *gdb_ctx, void *user_ctx)
{
+ g_autoptr(GString) rs = g_string_new(NULL);
CPUState *cpu;
- int len;
if (!gdb_ctx->num_params ||
gdb_ctx->params[0].thread_id.kind == GDB_READ_THREAD_ERR) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
- cpu = gdb_get_cpu(gdb_ctx->s, gdb_ctx->params[0].thread_id.pid,
+ cpu = gdb_get_cpu(gdb_ctx->params[0].thread_id.pid,
gdb_ctx->params[0].thread_id.tid);
if (!cpu) {
return;
@@ -2035,24 +2056,21 @@
cpu_synchronize_state(cpu);
- if (gdb_ctx->s->multiprocess && (gdb_ctx->s->process_num > 1)) {
+ if (gdbserver_state.multiprocess && (gdbserver_state.process_num > 1)) {
/* Print the CPU model and name in multiprocess mode */
ObjectClass *oc = object_get_class(OBJECT(cpu));
const char *cpu_model = object_class_get_name(oc);
- char *cpu_name = object_get_canonical_path_component(OBJECT(cpu));
- len = snprintf((char *)gdb_ctx->mem_buf, sizeof(gdb_ctx->str_buf) / 2,
- "%s %s [%s]", cpu_model, cpu_name,
- cpu->halted ? "halted " : "running");
- g_free(cpu_name);
+ g_autofree char *cpu_name;
+ cpu_name = object_get_canonical_path_component(OBJECT(cpu));
+ g_string_printf(rs, "%s %s [%s]", cpu_model, cpu_name,
+ cpu->halted ? "halted " : "running");
} else {
- /* memtohex() doubles the required space */
- len = snprintf((char *)gdb_ctx->mem_buf, sizeof(gdb_ctx->str_buf) / 2,
- "CPU#%d [%s]", cpu->cpu_index,
+ g_string_printf(rs, "CPU#%d [%s]", cpu->cpu_index,
cpu->halted ? "halted " : "running");
}
- trace_gdbstub_op_extra_info((char *)gdb_ctx->mem_buf);
- memtohex(gdb_ctx->str_buf, gdb_ctx->mem_buf, len);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ trace_gdbstub_op_extra_info(rs->str);
+ memtohex(gdbserver_state.str_buf, (uint8_t *)rs->str, rs->len);
+ put_strbuf();
}
#ifdef CONFIG_USER_ONLY
@@ -2060,37 +2078,40 @@
{
TaskState *ts;
- ts = gdb_ctx->s->c_cpu->opaque;
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf),
- "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
- ";Bss=" TARGET_ABI_FMT_lx,
- ts->info->code_offset,
- ts->info->data_offset,
- ts->info->data_offset);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ ts = gdbserver_state.c_cpu->opaque;
+ g_string_printf(gdbserver_state.str_buf,
+ "Text=" TARGET_ABI_FMT_lx
+ ";Data=" TARGET_ABI_FMT_lx
+ ";Bss=" TARGET_ABI_FMT_lx,
+ ts->info->code_offset,
+ ts->info->data_offset,
+ ts->info->data_offset);
+ put_strbuf();
}
#else
static void handle_query_rcmd(GdbCmdContext *gdb_ctx, void *user_ctx)
{
+ const guint8 zero = 0;
int len;
if (!gdb_ctx->num_params) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
len = strlen(gdb_ctx->params[0].data);
if (len % 2) {
- put_packet(gdb_ctx->s, "E01");
+ put_packet("E01");
return;
}
+ g_assert(gdbserver_state.mem_buf->len == 0);
len = len / 2;
- hextomem(gdb_ctx->mem_buf, gdb_ctx->params[0].data, len);
- gdb_ctx->mem_buf[len++] = 0;
- qemu_chr_be_write(gdb_ctx->s->mon_chr, gdb_ctx->mem_buf, len);
- put_packet(gdb_ctx->s, "OK");
-
+ hextomem(gdbserver_state.mem_buf, gdb_ctx->params[0].data, len);
+ g_byte_array_append(gdbserver_state.mem_buf, &zero, 1);
+ qemu_chr_be_write(gdbserver_state.mon_chr, gdbserver_state.mem_buf->data,
+ gdbserver_state.mem_buf->len);
+ put_packet("OK");
}
#endif
@@ -2098,21 +2119,19 @@
{
CPUClass *cc;
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), "PacketSize=%x",
- MAX_PACKET_LENGTH);
+ g_string_printf(gdbserver_state.str_buf, "PacketSize=%x", MAX_PACKET_LENGTH);
cc = CPU_GET_CLASS(first_cpu);
if (cc->gdb_core_xml_file) {
- pstrcat(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf),
- ";qXfer:features:read+");
+ g_string_append(gdbserver_state.str_buf, ";qXfer:features:read+");
}
if (gdb_ctx->num_params &&
strstr(gdb_ctx->params[0].data, "multiprocess+")) {
- gdb_ctx->s->multiprocess = true;
+ gdbserver_state.multiprocess = true;
}
- pstrcat(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), ";multiprocess+");
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ g_string_append(gdbserver_state.str_buf, ";vContSupported+;multiprocess+");
+ put_strbuf();
}
static void handle_query_xfer_features(GdbCmdContext *gdb_ctx, void *user_ctx)
@@ -2124,22 +2143,22 @@
const char *p;
if (gdb_ctx->num_params < 3) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
- process = gdb_get_cpu_process(gdb_ctx->s, gdb_ctx->s->g_cpu);
- cc = CPU_GET_CLASS(gdb_ctx->s->g_cpu);
+ process = gdb_get_cpu_process(gdbserver_state.g_cpu);
+ cc = CPU_GET_CLASS(gdbserver_state.g_cpu);
if (!cc->gdb_core_xml_file) {
- put_packet(gdb_ctx->s, "");
+ put_packet("");
return;
}
gdb_has_xml = true;
p = gdb_ctx->params[0].data;
- xml = get_feature_xml(gdb_ctx->s, p, &p, process);
+ xml = get_feature_xml(p, &p, process);
if (!xml) {
- put_packet(gdb_ctx->s, "E00");
+ put_packet("E00");
return;
}
@@ -2147,7 +2166,7 @@
len = gdb_ctx->params[2].val_ul;
total_len = strlen(xml);
if (addr > total_len) {
- put_packet(gdb_ctx->s, "E00");
+ put_packet("E00");
return;
}
@@ -2156,42 +2175,43 @@
}
if (len < total_len - addr) {
- gdb_ctx->str_buf[0] = 'm';
- len = memtox(gdb_ctx->str_buf + 1, xml + addr, len);
+ g_string_assign(gdbserver_state.str_buf, "m");
+ memtox(gdbserver_state.str_buf, xml + addr, len);
} else {
- gdb_ctx->str_buf[0] = 'l';
- len = memtox(gdb_ctx->str_buf + 1, xml + addr, total_len - addr);
+ g_string_assign(gdbserver_state.str_buf, "l");
+ memtox(gdbserver_state.str_buf, xml + addr, total_len - addr);
}
- put_packet_binary(gdb_ctx->s, gdb_ctx->str_buf, len + 1, true);
+ put_packet_binary(gdbserver_state.str_buf->str,
+ gdbserver_state.str_buf->len, true);
}
static void handle_query_attached(GdbCmdContext *gdb_ctx, void *user_ctx)
{
- put_packet(gdb_ctx->s, GDB_ATTACHED);
+ put_packet(GDB_ATTACHED);
}
static void handle_query_qemu_supported(GdbCmdContext *gdb_ctx, void *user_ctx)
{
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), "sstepbits;sstep");
+ g_string_printf(gdbserver_state.str_buf, "sstepbits;sstep");
#ifndef CONFIG_USER_ONLY
- pstrcat(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), ";PhyMemMode");
+ g_string_append(gdbserver_state.str_buf, ";PhyMemMode");
#endif
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ put_strbuf();
}
#ifndef CONFIG_USER_ONLY
static void handle_query_qemu_phy_mem_mode(GdbCmdContext *gdb_ctx,
void *user_ctx)
{
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), "%d", phy_memory_mode);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ g_string_printf(gdbserver_state.str_buf, "%d", phy_memory_mode);
+ put_strbuf();
}
static void handle_set_qemu_phy_mem_mode(GdbCmdContext *gdb_ctx, void *user_ctx)
{
if (!gdb_ctx->num_params) {
- put_packet(gdb_ctx->s, "E22");
+ put_packet("E22");
return;
}
@@ -2200,7 +2220,7 @@
} else {
phy_memory_mode = 1;
}
- put_packet(gdb_ctx->s, "OK");
+ put_packet("OK");
}
#endif
@@ -2316,16 +2336,16 @@
return;
}
- if (!process_string_cmd(gdb_ctx->s, NULL, gdb_ctx->params[0].data,
+ if (!process_string_cmd(NULL, gdb_ctx->params[0].data,
gdb_gen_query_set_common_table,
ARRAY_SIZE(gdb_gen_query_set_common_table))) {
return;
}
- if (process_string_cmd(gdb_ctx->s, NULL, gdb_ctx->params[0].data,
+ if (process_string_cmd(NULL, gdb_ctx->params[0].data,
gdb_gen_query_table,
ARRAY_SIZE(gdb_gen_query_table))) {
- put_packet(gdb_ctx->s, "");
+ put_packet("");
}
}
@@ -2335,28 +2355,25 @@
return;
}
- if (!process_string_cmd(gdb_ctx->s, NULL, gdb_ctx->params[0].data,
+ if (!process_string_cmd(NULL, gdb_ctx->params[0].data,
gdb_gen_query_set_common_table,
ARRAY_SIZE(gdb_gen_query_set_common_table))) {
return;
}
- if (process_string_cmd(gdb_ctx->s, NULL, gdb_ctx->params[0].data,
+ if (process_string_cmd(NULL, gdb_ctx->params[0].data,
gdb_gen_set_table,
ARRAY_SIZE(gdb_gen_set_table))) {
- put_packet(gdb_ctx->s, "");
+ put_packet("");
}
}
static void handle_target_halt(GdbCmdContext *gdb_ctx, void *user_ctx)
{
- char thread_id[16];
-
- gdb_fmt_thread_id(gdb_ctx->s, gdb_ctx->s->c_cpu, thread_id,
- sizeof(thread_id));
- snprintf(gdb_ctx->str_buf, sizeof(gdb_ctx->str_buf), "T%02xthread:%s;",
- GDB_SIGNAL_TRAP, thread_id);
- put_packet(gdb_ctx->s, gdb_ctx->str_buf);
+ g_string_printf(gdbserver_state.str_buf, "T%02xthread:", GDB_SIGNAL_TRAP);
+ gdb_append_thread_id(gdbserver_state.c_cpu, gdbserver_state.str_buf);
+ g_string_append_c(gdbserver_state.str_buf, ';');
+ put_strbuf();
/*
* Remove all the breakpoints when this query is issued,
* because gdb is doing an initial connect and the state
@@ -2365,7 +2382,7 @@
gdb_breakpoint_remove_all();
}
-static int gdb_handle_packet(GDBState *s, const char *line_buf)
+static int gdb_handle_packet(const char *line_buf)
{
const GdbCmdParseEntry *cmd_parser = NULL;
@@ -2373,7 +2390,7 @@
switch (line_buf[0]) {
case '!':
- put_packet(s, "OK");
+ put_packet("OK");
break;
case '?':
{
@@ -2588,12 +2605,12 @@
break;
default:
/* put empty packet */
- put_packet(s, "");
+ put_packet("");
break;
}
if (cmd_parser) {
- run_cmd_parser(s, line_buf, cmd_parser);
+ run_cmd_parser(line_buf, cmd_parser);
}
return RS_IDLE;
@@ -2601,7 +2618,7 @@
void gdb_set_stop_cpu(CPUState *cpu)
{
- GDBProcess *p = gdb_get_cpu_process(gdbserver_state, cpu);
+ GDBProcess *p = gdb_get_cpu_process(cpu);
if (!p->attached) {
/*
@@ -2611,26 +2628,25 @@
return;
}
- gdbserver_state->c_cpu = cpu;
- gdbserver_state->g_cpu = cpu;
+ gdbserver_state.c_cpu = cpu;
+ gdbserver_state.g_cpu = cpu;
}
#ifndef CONFIG_USER_ONLY
static void gdb_vm_state_change(void *opaque, int running, RunState state)
{
- GDBState *s = gdbserver_state;
- CPUState *cpu = s->c_cpu;
- char buf[256];
- char thread_id[16];
+ CPUState *cpu = gdbserver_state.c_cpu;
+ g_autoptr(GString) buf = g_string_new(NULL);
+ g_autoptr(GString) tid = g_string_new(NULL);
const char *type;
int ret;
- if (running || s->state == RS_INACTIVE) {
+ if (running || gdbserver_state.state == RS_INACTIVE) {
return;
}
/* Is there a GDB syscall waiting to be sent? */
- if (s->current_syscall_cb) {
- put_packet(s, s->syscall_buf);
+ if (gdbserver_state.current_syscall_cb) {
+ put_packet(gdbserver_state.syscall_buf);
return;
}
@@ -2639,7 +2655,7 @@
return;
}
- gdb_fmt_thread_id(s, cpu, thread_id, sizeof(thread_id));
+ gdb_append_thread_id(cpu, tid);
switch (state) {
case RUN_STATE_DEBUG:
@@ -2657,10 +2673,9 @@
}
trace_gdbstub_hit_watchpoint(type, cpu_gdb_index(cpu),
(target_ulong)cpu->watchpoint_hit->vaddr);
- snprintf(buf, sizeof(buf),
- "T%02xthread:%s;%swatch:" TARGET_FMT_lx ";",
- GDB_SIGNAL_TRAP, thread_id, type,
- (target_ulong)cpu->watchpoint_hit->vaddr);
+ g_string_printf(buf, "T%02xthread:%s;%swatch:" TARGET_FMT_lx ";",
+ GDB_SIGNAL_TRAP, tid->str, type,
+ (target_ulong)cpu->watchpoint_hit->vaddr);
cpu->watchpoint_hit = NULL;
goto send_packet;
} else {
@@ -2701,10 +2716,10 @@
break;
}
gdb_set_stop_cpu(cpu);
- snprintf(buf, sizeof(buf), "T%02xthread:%s;", ret, thread_id);
+ g_string_printf(buf, "T%02xthread:%s;", ret, tid->str);
send_packet:
- put_packet(s, buf);
+ put_packet(buf->str);
/* disable single step if it was enabled */
cpu_single_step(cpu, 0);
@@ -2722,17 +2737,17 @@
char *p_end;
target_ulong addr;
uint64_t i64;
- GDBState *s;
- s = gdbserver_state;
- if (!s)
+ if (!gdbserver_state.init) {
return;
- s->current_syscall_cb = cb;
+ }
+
+ gdbserver_state.current_syscall_cb = cb;
#ifndef CONFIG_USER_ONLY
vm_stop(RUN_STATE_DEBUG);
#endif
- p = s->syscall_buf;
- p_end = &s->syscall_buf[sizeof(s->syscall_buf)];
+ p = &gdbserver_state.syscall_buf[0];
+ p_end = &gdbserver_state.syscall_buf[sizeof(gdbserver_state.syscall_buf)];
*(p++) = 'F';
while (*fmt) {
if (*fmt == '%') {
@@ -2765,14 +2780,14 @@
}
*p = 0;
#ifdef CONFIG_USER_ONLY
- put_packet(s, s->syscall_buf);
+ put_packet(gdbserver_state.syscall_buf);
/* Return control to gdb for it to process the syscall request.
* Since the protocol requires that gdb hands control back to us
* using a "here are the results" F packet, we don't need to check
* gdb_handlesig's return value (which is the signal to deliver if
* execution was resumed via a continue packet).
*/
- gdb_handlesig(s->c_cpu, 0);
+ gdb_handlesig(gdbserver_state.c_cpu, 0);
#else
/* In this case wait to send the syscall packet until notification that
the CPU has stopped. This must be done because if the packet is sent
@@ -2780,7 +2795,7 @@
is still in the running state, which can cause packets to be dropped
and state transition 'T' packets to be sent while the syscall is still
being processed. */
- qemu_cpu_kick(s->c_cpu);
+ qemu_cpu_kick(gdbserver_state.c_cpu);
#endif
}
@@ -2793,25 +2808,27 @@
va_end(va);
}
-static void gdb_read_byte(GDBState *s, uint8_t ch)
+static void gdb_read_byte(uint8_t ch)
{
uint8_t reply;
#ifndef CONFIG_USER_ONLY
- if (s->last_packet_len) {
+ if (gdbserver_state.last_packet->len) {
/* Waiting for a response to the last packet. If we see the start
of a new command then abandon the previous response. */
if (ch == '-') {
trace_gdbstub_err_got_nack();
- put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
+ put_buffer(gdbserver_state.last_packet->data,
+ gdbserver_state.last_packet->len);
} else if (ch == '+') {
trace_gdbstub_io_got_ack();
} else {
trace_gdbstub_io_got_unexpected(ch);
}
- if (ch == '+' || ch == '$')
- s->last_packet_len = 0;
+ if (ch == '+' || ch == '$') {
+ g_byte_array_set_size(gdbserver_state.last_packet, 0);
+ }
if (ch != '$')
return;
}
@@ -2822,13 +2839,13 @@
} else
#endif
{
- switch(s->state) {
+ switch(gdbserver_state.state) {
case RS_IDLE:
if (ch == '$') {
/* start of command packet */
- s->line_buf_index = 0;
- s->line_sum = 0;
- s->state = RS_GETLINE;
+ gdbserver_state.line_buf_index = 0;
+ gdbserver_state.line_sum = 0;
+ gdbserver_state.state = RS_GETLINE;
} else {
trace_gdbstub_err_garbage(ch);
}
@@ -2836,37 +2853,37 @@
case RS_GETLINE:
if (ch == '}') {
/* start escape sequence */
- s->state = RS_GETLINE_ESC;
- s->line_sum += ch;
+ gdbserver_state.state = RS_GETLINE_ESC;
+ gdbserver_state.line_sum += ch;
} else if (ch == '*') {
/* start run length encoding sequence */
- s->state = RS_GETLINE_RLE;
- s->line_sum += ch;
+ gdbserver_state.state = RS_GETLINE_RLE;
+ gdbserver_state.line_sum += ch;
} else if (ch == '#') {
/* end of command, start of checksum*/
- s->state = RS_CHKSUM1;
- } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
+ gdbserver_state.state = RS_CHKSUM1;
+ } else if (gdbserver_state.line_buf_index >= sizeof(gdbserver_state.line_buf) - 1) {
trace_gdbstub_err_overrun();
- s->state = RS_IDLE;
+ gdbserver_state.state = RS_IDLE;
} else {
/* unescaped command character */
- s->line_buf[s->line_buf_index++] = ch;
- s->line_sum += ch;
+ gdbserver_state.line_buf[gdbserver_state.line_buf_index++] = ch;
+ gdbserver_state.line_sum += ch;
}
break;
case RS_GETLINE_ESC:
if (ch == '#') {
/* unexpected end of command in escape sequence */
- s->state = RS_CHKSUM1;
- } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
+ gdbserver_state.state = RS_CHKSUM1;
+ } else if (gdbserver_state.line_buf_index >= sizeof(gdbserver_state.line_buf) - 1) {
/* command buffer overrun */
trace_gdbstub_err_overrun();
- s->state = RS_IDLE;
+ gdbserver_state.state = RS_IDLE;
} else {
/* parse escaped character and leave escape state */
- s->line_buf[s->line_buf_index++] = ch ^ 0x20;
- s->line_sum += ch;
- s->state = RS_GETLINE;
+ gdbserver_state.line_buf[gdbserver_state.line_buf_index++] = ch ^ 0x20;
+ gdbserver_state.line_sum += ch;
+ gdbserver_state.state = RS_GETLINE;
}
break;
case RS_GETLINE_RLE:
@@ -2877,25 +2894,25 @@
if (ch < ' ' || ch == '#' || ch == '$' || ch > 126) {
/* invalid RLE count encoding */
trace_gdbstub_err_invalid_repeat(ch);
- s->state = RS_GETLINE;
+ gdbserver_state.state = RS_GETLINE;
} else {
/* decode repeat length */
int repeat = ch - ' ' + 3;
- if (s->line_buf_index + repeat >= sizeof(s->line_buf) - 1) {
+ if (gdbserver_state.line_buf_index + repeat >= sizeof(gdbserver_state.line_buf) - 1) {
/* that many repeats would overrun the command buffer */
trace_gdbstub_err_overrun();
- s->state = RS_IDLE;
- } else if (s->line_buf_index < 1) {
+ gdbserver_state.state = RS_IDLE;
+ } else if (gdbserver_state.line_buf_index < 1) {
/* got a repeat but we have nothing to repeat */
trace_gdbstub_err_invalid_rle();
- s->state = RS_GETLINE;
+ gdbserver_state.state = RS_GETLINE;
} else {
/* repeat the last character */
- memset(s->line_buf + s->line_buf_index,
- s->line_buf[s->line_buf_index - 1], repeat);
- s->line_buf_index += repeat;
- s->line_sum += ch;
- s->state = RS_GETLINE;
+ memset(gdbserver_state.line_buf + gdbserver_state.line_buf_index,
+ gdbserver_state.line_buf[gdbserver_state.line_buf_index - 1], repeat);
+ gdbserver_state.line_buf_index += repeat;
+ gdbserver_state.line_sum += ch;
+ gdbserver_state.state = RS_GETLINE;
}
}
break;
@@ -2903,33 +2920,33 @@
/* get high hex digit of checksum */
if (!isxdigit(ch)) {
trace_gdbstub_err_checksum_invalid(ch);
- s->state = RS_GETLINE;
+ gdbserver_state.state = RS_GETLINE;
break;
}
- s->line_buf[s->line_buf_index] = '\0';
- s->line_csum = fromhex(ch) << 4;
- s->state = RS_CHKSUM2;
+ gdbserver_state.line_buf[gdbserver_state.line_buf_index] = '\0';
+ gdbserver_state.line_csum = fromhex(ch) << 4;
+ gdbserver_state.state = RS_CHKSUM2;
break;
case RS_CHKSUM2:
/* get low hex digit of checksum */
if (!isxdigit(ch)) {
trace_gdbstub_err_checksum_invalid(ch);
- s->state = RS_GETLINE;
+ gdbserver_state.state = RS_GETLINE;
break;
}
- s->line_csum |= fromhex(ch);
+ gdbserver_state.line_csum |= fromhex(ch);
- if (s->line_csum != (s->line_sum & 0xff)) {
- trace_gdbstub_err_checksum_incorrect(s->line_sum, s->line_csum);
+ if (gdbserver_state.line_csum != (gdbserver_state.line_sum & 0xff)) {
+ trace_gdbstub_err_checksum_incorrect(gdbserver_state.line_sum, gdbserver_state.line_csum);
/* send NAK reply */
reply = '-';
- put_buffer(s, &reply, 1);
- s->state = RS_IDLE;
+ put_buffer(&reply, 1);
+ gdbserver_state.state = RS_IDLE;
} else {
/* send ACK reply */
reply = '+';
- put_buffer(s, &reply, 1);
- s->state = gdb_handle_packet(s, s->line_buf);
+ put_buffer(&reply, 1);
+ gdbserver_state.state = gdb_handle_packet(gdbserver_state.line_buf);
}
break;
default:
@@ -2941,15 +2958,13 @@
/* Tell the remote gdb that the process has exited. */
void gdb_exit(CPUArchState *env, int code)
{
- GDBState *s;
char buf[4];
- s = gdbserver_state;
- if (!s) {
+ if (!gdbserver_state.init) {
return;
}
#ifdef CONFIG_USER_ONLY
- if (gdbserver_fd < 0 || s->fd < 0) {
+ if (gdbserver_fd < 0 || gdbserver_state.fd < 0) {
return;
}
#endif
@@ -2957,10 +2972,10 @@
trace_gdbstub_op_exiting((uint8_t)code);
snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
- put_packet(s, buf);
+ put_packet(buf);
#ifndef CONFIG_USER_ONLY
- qemu_chr_fe_deinit(&s->chr, true);
+ qemu_chr_fe_deinit(&gdbserver_state.chr, true);
#endif
}
@@ -2974,7 +2989,7 @@
GDBProcess *process;
int max_pid = 0;
- if (s->process_num) {
+ if (gdbserver_state.process_num) {
max_pid = s->processes[s->process_num - 1].pid;
}
@@ -2993,12 +3008,10 @@
int
gdb_handlesig(CPUState *cpu, int sig)
{
- GDBState *s;
char buf[256];
int n;
- s = gdbserver_state;
- if (gdbserver_fd < 0 || s->fd < 0) {
+ if (gdbserver_fd < 0 || gdbserver_state.fd < 0) {
return sig;
}
@@ -3008,58 +3021,55 @@
if (sig != 0) {
snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb(sig));
- put_packet(s, buf);
+ put_packet(buf);
}
/* put_packet() might have detected that the peer terminated the
connection. */
- if (s->fd < 0) {
+ if (gdbserver_state.fd < 0) {
return sig;
}
sig = 0;
- s->state = RS_IDLE;
- s->running_state = 0;
- while (s->running_state == 0) {
- n = read(s->fd, buf, 256);
+ gdbserver_state.state = RS_IDLE;
+ gdbserver_state.running_state = 0;
+ while (gdbserver_state.running_state == 0) {
+ n = read(gdbserver_state.fd, buf, 256);
if (n > 0) {
int i;
for (i = 0; i < n; i++) {
- gdb_read_byte(s, buf[i]);
+ gdb_read_byte(buf[i]);
}
} else {
/* XXX: Connection closed. Should probably wait for another
connection before continuing. */
if (n == 0) {
- close(s->fd);
+ close(gdbserver_state.fd);
}
- s->fd = -1;
+ gdbserver_state.fd = -1;
return sig;
}
}
- sig = s->signal;
- s->signal = 0;
+ sig = gdbserver_state.signal;
+ gdbserver_state.signal = 0;
return sig;
}
/* Tell the remote gdb that the process has exited due to SIG. */
void gdb_signalled(CPUArchState *env, int sig)
{
- GDBState *s;
char buf[4];
- s = gdbserver_state;
- if (gdbserver_fd < 0 || s->fd < 0) {
+ if (gdbserver_fd < 0 || gdbserver_state.fd < 0) {
return;
}
snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb(sig));
- put_packet(s, buf);
+ put_packet(buf);
}
static bool gdb_accept(void)
{
- GDBState *s;
struct sockaddr_in sockaddr;
socklen_t len;
int fd;
@@ -3083,15 +3093,13 @@
return false;
}
- s = g_malloc0(sizeof(GDBState));
- create_default_process(s);
- s->processes[0].attached = true;
- s->c_cpu = gdb_first_attached_cpu(s);
- s->g_cpu = s->c_cpu;
- s->fd = fd;
+ init_gdbserver_state();
+ create_default_process(&gdbserver_state);
+ gdbserver_state.processes[0].attached = true;
+ gdbserver_state.c_cpu = gdb_first_attached_cpu();
+ gdbserver_state.g_cpu = gdbserver_state.c_cpu;
+ gdbserver_state.fd = fd;
gdb_has_xml = false;
-
- gdbserver_state = s;
return true;
}
@@ -3144,13 +3152,11 @@
/* Disable gdb stub for child processes. */
void gdbserver_fork(CPUState *cpu)
{
- GDBState *s = gdbserver_state;
-
- if (gdbserver_fd < 0 || s->fd < 0) {
+ if (gdbserver_fd < 0 || gdbserver_state.fd < 0) {
return;
}
- close(s->fd);
- s->fd = -1;
+ close(gdbserver_state.fd);
+ gdbserver_state.fd = -1;
cpu_breakpoint_remove_all(cpu, BP_GDB);
cpu_watchpoint_remove_all(cpu, BP_GDB);
}
@@ -3167,7 +3173,7 @@
int i;
for (i = 0; i < size; i++) {
- gdb_read_byte(gdbserver_state, buf[i]);
+ gdb_read_byte(buf[i]);
}
}
@@ -3183,7 +3189,7 @@
s->processes[i].attached = !i;
}
- s->c_cpu = gdb_first_attached_cpu(s);
+ s->c_cpu = gdb_first_attached_cpu();
s->g_cpu = s->c_cpu;
vm_stop(RUN_STATE_PAUSED);
@@ -3194,32 +3200,11 @@
}
}
-static void gdb_monitor_output(GDBState *s, const char *msg, int len)
-{
- char buf[MAX_PACKET_LENGTH];
-
- buf[0] = 'O';
- if (len > (MAX_PACKET_LENGTH/2) - 1)
- len = (MAX_PACKET_LENGTH/2) - 1;
- memtohex(buf + 1, (uint8_t *)msg, len);
- put_packet(s, buf);
-}
-
static int gdb_monitor_write(Chardev *chr, const uint8_t *buf, int len)
{
- const char *p = (const char *)buf;
- int max_sz;
-
- max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
- for (;;) {
- if (len <= max_sz) {
- gdb_monitor_output(gdbserver_state, p, len);
- break;
- }
- gdb_monitor_output(gdbserver_state, p, max_sz);
- p += max_sz;
- len -= max_sz;
- }
+ g_autoptr(GString) hex_buf = g_string_new("O");
+ memtohex(hex_buf, buf, len);
+ put_packet(hex_buf->str);
return len;
}
@@ -3300,26 +3285,18 @@
{
object_child_foreach(object_get_root(), find_cpu_clusters, s);
- if (s->processes) {
+ if (gdbserver_state.processes) {
/* Sort by PID */
- qsort(s->processes, s->process_num, sizeof(s->processes[0]), pid_order);
+ qsort(gdbserver_state.processes, gdbserver_state.process_num, sizeof(gdbserver_state.processes[0]), pid_order);
}
create_default_process(s);
}
-static void cleanup_processes(GDBState *s)
-{
- g_free(s->processes);
- s->process_num = 0;
- s->processes = NULL;
-}
-
int gdbserver_start(const char *device)
{
trace_gdbstub_op_start(device);
- GDBState *s;
char gdbstub_device_name[128];
Chardev *chr = NULL;
Chardev *mon_chr;
@@ -3357,10 +3334,8 @@
return -1;
}
- s = gdbserver_state;
- if (!s) {
- s = g_malloc0(sizeof(GDBState));
- gdbserver_state = s;
+ if (!gdbserver_state.init) {
+ init_gdbserver_state();
qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
@@ -3369,31 +3344,30 @@
NULL, NULL, &error_abort);
monitor_init_hmp(mon_chr, false, &error_abort);
} else {
- qemu_chr_fe_deinit(&s->chr, true);
- mon_chr = s->mon_chr;
- cleanup_processes(s);
- memset(s, 0, sizeof(GDBState));
- s->mon_chr = mon_chr;
+ qemu_chr_fe_deinit(&gdbserver_state.chr, true);
+ mon_chr = gdbserver_state.mon_chr;
+ reset_gdbserver_state();
}
- create_processes(s);
+ create_processes(&gdbserver_state);
if (chr) {
- qemu_chr_fe_init(&s->chr, chr, &error_abort);
- qemu_chr_fe_set_handlers(&s->chr, gdb_chr_can_receive, gdb_chr_receive,
- gdb_chr_event, NULL, s, NULL, true);
+ qemu_chr_fe_init(&gdbserver_state.chr, chr, &error_abort);
+ qemu_chr_fe_set_handlers(&gdbserver_state.chr, gdb_chr_can_receive,
+ gdb_chr_receive, gdb_chr_event,
+ NULL, &gdbserver_state, NULL, true);
}
- s->state = chr ? RS_IDLE : RS_INACTIVE;
- s->mon_chr = mon_chr;
- s->current_syscall_cb = NULL;
+ gdbserver_state.state = chr ? RS_IDLE : RS_INACTIVE;
+ gdbserver_state.mon_chr = mon_chr;
+ gdbserver_state.current_syscall_cb = NULL;
return 0;
}
void gdbserver_cleanup(void)
{
- if (gdbserver_state) {
- put_packet(gdbserver_state, "W00");
+ if (gdbserver_state.init) {
+ put_packet("W00");
}
}
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 4e74284..336cace 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -357,81 +357,6 @@
s->pm.cpu_hotplug_legacy = value;
}
-static void ich9_pm_get_disable_s3(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ICH9LPCPMRegs *pm = opaque;
- uint8_t value = pm->disable_s3;
-
- visit_type_uint8(v, name, &value, errp);
-}
-
-static void ich9_pm_set_disable_s3(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ICH9LPCPMRegs *pm = opaque;
- Error *local_err = NULL;
- uint8_t value;
-
- visit_type_uint8(v, name, &value, &local_err);
- if (local_err) {
- goto out;
- }
- pm->disable_s3 = value;
-out:
- error_propagate(errp, local_err);
-}
-
-static void ich9_pm_get_disable_s4(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ICH9LPCPMRegs *pm = opaque;
- uint8_t value = pm->disable_s4;
-
- visit_type_uint8(v, name, &value, errp);
-}
-
-static void ich9_pm_set_disable_s4(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ICH9LPCPMRegs *pm = opaque;
- Error *local_err = NULL;
- uint8_t value;
-
- visit_type_uint8(v, name, &value, &local_err);
- if (local_err) {
- goto out;
- }
- pm->disable_s4 = value;
-out:
- error_propagate(errp, local_err);
-}
-
-static void ich9_pm_get_s4_val(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ICH9LPCPMRegs *pm = opaque;
- uint8_t value = pm->s4_val;
-
- visit_type_uint8(v, name, &value, errp);
-}
-
-static void ich9_pm_set_s4_val(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ICH9LPCPMRegs *pm = opaque;
- Error *local_err = NULL;
- uint8_t value;
-
- visit_type_uint8(v, name, &value, &local_err);
- if (local_err) {
- goto out;
- }
- pm->s4_val = value;
-out:
- error_propagate(errp, local_err);
-}
-
static bool ich9_pm_get_enable_tco(Object *obj, Error **errp)
{
ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
@@ -454,12 +379,12 @@
pm->s4_val = 2;
object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
- &pm->pm_io_base, errp);
+ &pm->pm_io_base, OBJ_PROP_FLAG_READ, errp);
object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
ich9_pm_get_gpe0_blk,
NULL, NULL, pm, NULL);
object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
- &gpe0_len, errp);
+ &gpe0_len, OBJ_PROP_FLAG_READ, errp);
object_property_add_bool(obj, "memory-hotplug-support",
ich9_pm_get_memory_hotplug_support,
ich9_pm_set_memory_hotplug_support,
@@ -468,18 +393,14 @@
ich9_pm_get_cpu_hotplug_legacy,
ich9_pm_set_cpu_hotplug_legacy,
NULL);
- object_property_add(obj, ACPI_PM_PROP_S3_DISABLED, "uint8",
- ich9_pm_get_disable_s3,
- ich9_pm_set_disable_s3,
- NULL, pm, NULL);
- object_property_add(obj, ACPI_PM_PROP_S4_DISABLED, "uint8",
- ich9_pm_get_disable_s4,
- ich9_pm_set_disable_s4,
- NULL, pm, NULL);
- object_property_add(obj, ACPI_PM_PROP_S4_VAL, "uint8",
- ich9_pm_get_s4_val,
- ich9_pm_set_s4_val,
- NULL, pm, NULL);
+ object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S3_DISABLED,
+ &pm->disable_s3, OBJ_PROP_FLAG_READWRITE,
+ NULL);
+ object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_DISABLED,
+ &pm->disable_s4, OBJ_PROP_FLAG_READWRITE,
+ NULL);
+ object_property_add_uint8_ptr(obj, ACPI_PM_PROP_S4_VAL,
+ &pm->s4_val, OBJ_PROP_FLAG_READWRITE, NULL);
object_property_add_bool(obj, ACPI_PM_PROP_TCO_ENABLED,
ich9_pm_get_enable_tco,
ich9_pm_set_enable_tco,
diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
index 5219dd0..eb6a37b 100644
--- a/hw/acpi/nvdimm.c
+++ b/hw/acpi/nvdimm.c
@@ -485,7 +485,7 @@
/* the size of buffer filled by QEMU. */
uint32_t len;
uint32_t func_ret_status; /* return status code. */
- uint8_t out_buf[0]; /* the data got via Get Namesapce Label function. */
+ uint8_t out_buf[]; /* the data got via Get Namesapce Label function. */
} QEMU_PACKED;
typedef struct NvdimmFuncGetLabelDataOut NvdimmFuncGetLabelDataOut;
QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataOut) > NVDIMM_DSM_MEMORY_SIZE);
@@ -493,7 +493,7 @@
struct NvdimmFuncSetLabelDataIn {
uint32_t offset; /* the offset in the namespace label data area. */
uint32_t length; /* the size of data is to be written via the function. */
- uint8_t in_buf[0]; /* the data written to label data area. */
+ uint8_t in_buf[]; /* the data written to label data area. */
} QEMU_PACKED;
typedef struct NvdimmFuncSetLabelDataIn NvdimmFuncSetLabelDataIn;
QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncSetLabelDataIn) +
@@ -510,7 +510,7 @@
/* the size of buffer filled by QEMU. */
uint32_t len;
uint32_t func_ret_status; /* return status code. */
- uint8_t fit[0]; /* the FIT data. */
+ uint8_t fit[]; /* the FIT data. */
} QEMU_PACKED;
typedef struct NvdimmFuncReadFITOut NvdimmFuncReadFITOut;
QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncReadFITOut) > NVDIMM_DSM_MEMORY_SIZE);
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 8413348..4dcef37 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -80,7 +80,8 @@
*bus_bsel = (*bsel_alloc)++;
object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
- bus_bsel, &error_abort);
+ bus_bsel, OBJ_PROP_FLAG_READ,
+ &error_abort);
}
return bsel_alloc;
@@ -373,9 +374,9 @@
memory_region_add_subregion(address_space_io, s->io_base, &s->io);
object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
- &error_abort);
+ OBJ_PROP_FLAG_READ, &error_abort);
object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
- &error_abort);
+ OBJ_PROP_FLAG_READ, &error_abort);
}
const VMStateDescription vmstate_acpi_pcihp_pci_status = {
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index b84dbba..964d6f5 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -444,17 +444,17 @@
static const uint16_t sci_int = 9;
object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
- &acpi_enable_cmd, NULL);
+ &acpi_enable_cmd, OBJ_PROP_FLAG_READ, NULL);
object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
- &acpi_disable_cmd, NULL);
+ &acpi_disable_cmd, OBJ_PROP_FLAG_READ, NULL);
object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
- &gpe0_blk, NULL);
+ &gpe0_blk, OBJ_PROP_FLAG_READ, NULL);
object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
- &gpe0_blk_len, NULL);
+ &gpe0_blk_len, OBJ_PROP_FLAG_READ, NULL);
object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
- &sci_int, NULL);
+ &sci_int, OBJ_PROP_FLAG_READ, NULL);
object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
- &s->io_base, NULL);
+ &s->io_base, OBJ_PROP_FLAG_READ, NULL);
}
static void piix4_pm_realize(PCIDevice *dev, Error **errp)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e5a876c..188419d 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -373,6 +373,7 @@
select IMX
select IMX_FEC
select IMX_I2C
+ select IMX_USBPHY
select SDHCI
config ASPEED_SOC
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 59a27bd..1f7253e 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -305,23 +305,21 @@
/*** Memory ***/
/* Chip-ID and OMR */
- memory_region_init_io(&s->chipid_mem, NULL, &exynos4210_chipid_and_omr_ops,
- NULL, "exynos4210.chipid", sizeof(chipid_and_omr));
+ memory_region_init_io(&s->chipid_mem, OBJECT(socdev),
+ &exynos4210_chipid_and_omr_ops, NULL,
+ "exynos4210.chipid", sizeof(chipid_and_omr));
memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
&s->chipid_mem);
/* Internal ROM */
- memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom",
+ memory_region_init_rom(&s->irom_mem, OBJECT(socdev), "exynos4210.irom",
EXYNOS4210_IROM_SIZE, &error_fatal);
- memory_region_set_readonly(&s->irom_mem, true);
memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
&s->irom_mem);
/* mirror of iROM */
- memory_region_init_alias(&s->irom_alias_mem, NULL, "exynos4210.irom_alias",
- &s->irom_mem,
- 0,
+ memory_region_init_alias(&s->irom_alias_mem, OBJECT(socdev),
+ "exynos4210.irom_alias", &s->irom_mem, 0,
EXYNOS4210_IROM_SIZE);
- memory_region_set_readonly(&s->irom_alias_mem, true);
memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
&s->irom_alias_mem);
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index a3f829f..6f1a82c 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -303,16 +303,16 @@
}
/* initialize 2 x 16 KB ROM */
- memory_region_init_rom(&s->rom[0], NULL,
- "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
+ memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0",
+ FSL_IMX25_ROM0_SIZE, &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
&s->rom[0]);
- memory_region_init_rom(&s->rom[1], NULL,
- "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
+ memory_region_init_rom(&s->rom[1], OBJECT(dev), "imx25.rom1",
+ FSL_IMX25_ROM1_SIZE, &err);
if (err) {
error_propagate(errp, err);
return;
@@ -331,7 +331,7 @@
&s->iram);
/* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
- memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
+ memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx25.iram_alias",
&s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
&s->iram_alias);
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
index 55e90d1..8472d2e 100644
--- a/hw/arm/fsl-imx31.c
+++ b/hw/arm/fsl-imx31.c
@@ -206,7 +206,7 @@
}
/* On a real system, the first 16k is a `secure boot rom' */
- memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
+ memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom",
FSL_IMX31_SECURE_ROM_SIZE, &err);
if (err) {
error_propagate(errp, err);
@@ -216,7 +216,7 @@
&s->secure_rom);
/* There is also a 16k ROM */
- memory_region_init_rom(&s->rom, NULL, "imx31.rom",
+ memory_region_init_rom(&s->rom, OBJECT(dev), "imx31.rom",
FSL_IMX31_ROM_SIZE, &err);
if (err) {
error_propagate(errp, err);
@@ -236,7 +236,7 @@
&s->iram);
/* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
- memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
+ memory_region_init_alias(&s->iram_alias, OBJECT(dev), "imx31.iram_alias",
&s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
&s->iram_alias);
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index ecc6285..13f1bf2 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -22,6 +22,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/fsl-imx6.h"
+#include "hw/usb/imx-usb-phy.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "sysemu/sysemu.h"
@@ -86,6 +87,17 @@
TYPE_IMX_USDHC);
}
+ for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
+ snprintf(name, NAME_SIZE, "usbphy%d", i);
+ sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
+ TYPE_IMX_USBPHY);
+ }
+ for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
+ snprintf(name, NAME_SIZE, "usb%d", i);
+ sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
+ TYPE_CHIPIDEA);
+ }
+
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
snprintf(name, NAME_SIZE, "spi%d", i + 1);
sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
@@ -349,6 +361,30 @@
esdhc_table[i].irq));
}
+ /* USB */
+ for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
+ object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+ FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
+ }
+ for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
+ static const int FSL_IMX6_USBn_IRQ[] = {
+ FSL_IMX6_USB_OTG_IRQ,
+ FSL_IMX6_USB_HOST1_IRQ,
+ FSL_IMX6_USB_HOST2_IRQ,
+ FSL_IMX6_USB_HOST3_IRQ,
+ };
+
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+ FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore),
+ FSL_IMX6_USBn_IRQ[i]));
+ }
+
/* Initialize all ECSPI */
for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
static const struct {
@@ -405,7 +441,7 @@
}
/* ROM memory */
- memory_region_init_rom(&s->rom, NULL, "imx6.rom",
+ memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
FSL_IMX6_ROM_SIZE, &err);
if (err) {
error_propagate(errp, err);
@@ -415,7 +451,7 @@
&s->rom);
/* CAAM memory */
- memory_region_init_rom(&s->caam, NULL, "imx6.caam",
+ memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
FSL_IMX6_CAAM_MEM_SIZE, &err);
if (err) {
error_propagate(errp, err);
@@ -435,7 +471,7 @@
&s->ocram);
/* internal OCRAM (256 KB) is aliased over 1 MB */
- memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias",
+ memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
&s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
&s->ocram_alias);
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index c405b68..56dfd7c 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -20,6 +20,7 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6ul.h"
#include "hw/misc/unimp.h"
+#include "hw/usb/imx-usb-phy.h"
#include "hw/boards.h"
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
@@ -133,6 +134,18 @@
TYPE_IMX_ENET);
}
+ /* USB */
+ for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+ snprintf(name, NAME_SIZE, "usbphy%d", i);
+ sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
+ TYPE_IMX_USBPHY);
+ }
+ for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+ snprintf(name, NAME_SIZE, "usb%d", i);
+ sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
+ TYPE_CHIPIDEA);
+ }
+
/*
* SDHCI
*/
@@ -456,6 +469,28 @@
FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
}
+ /* USB */
+ for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+ object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+ FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
+ }
+
+ for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+ static const int FSL_IMX6UL_USBn_IRQ[] = {
+ FSL_IMX6UL_USB1_IRQ,
+ FSL_IMX6UL_USB2_IRQ,
+ };
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+ FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ FSL_IMX6UL_USBn_IRQ[i]));
+ }
+
/*
* USDHC
*/
@@ -517,6 +552,20 @@
create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
/*
+ * PWM
+ */
+ create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
+ create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
+ create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
+ create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
+
+ /*
+ * CAN
+ */
+ create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
+ create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
+
+ /*
* APHB_DMA
*/
create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR,
@@ -543,7 +592,7 @@
/*
* ROM memory
*/
- memory_region_init_rom(&s->rom, NULL, "imx6ul.rom",
+ memory_region_init_rom(&s->rom, OBJECT(dev), "imx6ul.rom",
FSL_IMX6UL_ROM_SIZE, &error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR,
&s->rom);
@@ -551,7 +600,7 @@
/*
* CAAM memory
*/
- memory_region_init_rom(&s->caam, NULL, "imx6ul.caam",
+ memory_region_init_rom(&s->caam, OBJECT(dev), "imx6ul.caam",
FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort);
memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR,
&s->caam);
@@ -568,8 +617,9 @@
/*
* internal OCRAM (128 KB) is aliased over 512 KB
*/
- memory_region_init_alias(&s->ocram_alias, NULL, "imx6ul.ocram_alias",
- &s->ocram, 0, FSL_IMX6UL_OCRAM_ALIAS_SIZE);
+ memory_region_init_alias(&s->ocram_alias, OBJECT(dev),
+ "imx6ul.ocram_alias", &s->ocram, 0,
+ FSL_IMX6UL_OCRAM_ALIAS_SIZE);
memory_region_add_subregion(get_system_memory(),
FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
}
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index 1042017..6bc6436 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -124,9 +124,8 @@
/* Setup CPU & memory */
mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
machine->cpu_type);
- memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
+ memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
&error_fatal);
- memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);
/* There are two 32MiB flash devices on the board */
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index 8f84692..588d643 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -96,7 +96,7 @@
MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
- memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
+ memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
&error_fatal);
/*
* On power-on, the eNVM region 0x60000000 is automatically
@@ -104,8 +104,8 @@
* start address (0x0). We do not support remapping other eNVM,
* eSRAM and DDR regions by guest(via Sysreg) currently.
*/
- memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
- nvm, 0, s->envm_size);
+ memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm, 0,
+ s->envm_size);
memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
memory_region_add_subregion(system_memory, 0, nvm_alias);
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 4817a76..57eff63 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -165,7 +165,7 @@
}
/* STUB Peripherals */
- memory_region_init_io(&s->clock, NULL, &clock_ops, NULL,
+ memory_region_init_io(&s->clock, OBJECT(dev_soc), &clock_ops, NULL,
"nrf51_soc.clock", 0x1000);
memory_region_add_subregion_overlap(&s->container,
NRF51_IOMEM_BASE, &s->clock, -1);
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index de5ff44..57829b3 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -131,9 +131,8 @@
mpu = omap310_mpu_init(machine->ram, machine->cpu_type);
/* External Flash (EMIFS) */
- memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
+ memory_region_init_rom(flash, NULL, "omap_sx1.flash0-0", flash_size,
&error_fatal);
- memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val,
@@ -167,9 +166,8 @@
if ((version == 1) &&
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
- memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0",
+ memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0",
flash1_size, &error_fatal);
- memory_region_set_readonly(flash_1, true);
memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 99554bd..97ca105 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -213,9 +213,8 @@
mpu = omap310_mpu_init(machine->ram, machine->cpu_type);
/* External Flash (EMIFS) */
- memory_region_init_ram(flash, NULL, "palmte.flash", flash_size,
+ memory_region_init_rom(flash, NULL, "palmte.flash", flash_size,
&error_fatal);
- memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space_mem, OMAP_CS0_BASE, flash);
memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val, "palmte-cs0",
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 56a3620..336c9ba 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -2290,9 +2290,6 @@
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
}
- sysbus_create_simple("sysbus-ohci", 0x4c000000,
- qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
-
s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index cbfa693..c28d9b5 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -929,8 +929,7 @@
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
- memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
- memory_region_set_readonly(rom, true);
+ memory_region_init_rom(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
memory_region_add_subregion(address_space_mem, 0, rom);
/* Setup peripherals */
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 221a786..d136ba1 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1300,9 +1300,8 @@
sram_size = ((board->dc0 >> 18) + 1) * 1024;
/* Flash programming is done via the SCU, so pretend it is ROM. */
- memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size,
+ memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
&error_fatal);
- memory_region_set_readonly(flash, true);
memory_region_add_subregion(system_memory, 0, flash);
memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 627fd44..118c342 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -93,13 +93,10 @@
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
- memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
- &error_fatal);
- memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
- flash, 0, FLASH_SIZE);
-
- memory_region_set_readonly(flash, true);
- memory_region_set_readonly(flash_alias, true);
+ memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash",
+ FLASH_SIZE, &error_fatal);
+ memory_region_init_alias(flash_alias, OBJECT(dev_soc),
+ "STM32F205.flash.alias", flash, 0, FLASH_SIZE);
memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
memory_region_add_subregion(system_memory, 0, flash_alias);
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index 9bcad97..4f10ce6 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -95,17 +95,15 @@
Error *err = NULL;
int i;
- memory_region_init_ram(&s->flash, NULL, "STM32F405.flash", FLASH_SIZE,
- &err);
+ memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
+ FLASH_SIZE, &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
- memory_region_init_alias(&s->flash_alias, NULL, "STM32F405.flash.alias",
- &s->flash, 0, FLASH_SIZE);
-
- memory_region_set_readonly(&s->flash, true);
- memory_region_set_readonly(&s->flash_alias, true);
+ memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
+ "STM32F405.flash.alias", &s->flash, 0,
+ FLASH_SIZE);
memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
memory_region_add_subregion(system_memory, 0, &s->flash_alias);
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 4d95a1f..5dee2d7 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -226,8 +226,7 @@
mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
- memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
- memory_region_set_readonly(rom, true);
+ memory_region_init_rom(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
memory_region_add_subregion(address_space_mem, 0, rom);
tmio = tc6393xb_init(address_space_mem, 0x10000000,
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index cab0160..49f1c8d 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -318,9 +318,9 @@
ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
- memory_region_init_alias(&s->ddr_ram_high, NULL,
- "ddr-ram-high", s->ddr_ram,
- ddr_low_size, ddr_high_size);
+ memory_region_init_alias(&s->ddr_ram_high, OBJECT(dev),
+ "ddr-ram-high", s->ddr_ram, ddr_low_size,
+ ddr_high_size);
memory_region_add_subregion(get_system_memory(),
XLNX_ZYNQMP_HIGH_RAM_START,
&s->ddr_ram_high);
@@ -330,9 +330,8 @@
ddr_low_size = ram_size;
}
- memory_region_init_alias(&s->ddr_ram_low, NULL,
- "ddr-ram-low", s->ddr_ram,
- 0, ddr_low_size);
+ memory_region_init_alias(&s->ddr_ram_low, OBJECT(dev), "ddr-ram-low",
+ s->ddr_ram, 0, ddr_low_size);
memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
/* Create the four OCM banks */
diff --git a/hw/audio/fmopl.c b/hw/audio/fmopl.c
index 173a752..356d4df 100644
--- a/hw/audio/fmopl.c
+++ b/hw/audio/fmopl.c
@@ -186,7 +186,7 @@
/* envelope output curve table */
/* attack + decay + OFF */
-static int32_t ENV_CURVE[2*EG_ENT+1];
+static int32_t *ENV_CURVE;
/* multiple table */
#define ML 2
@@ -1090,6 +1090,7 @@
OPL->clock = clock;
OPL->rate = rate;
OPL->max_ch = max_ch;
+ ENV_CURVE = g_new(int32_t, 2 * EG_ENT + 1);
/* init grobal tables */
OPL_initialize(OPL);
/* reset chip */
@@ -1127,6 +1128,7 @@
#endif
OPL_UnLockTable();
free(OPL);
+ g_free(ENV_CURVE);
}
/* ---------- Option handlers ---------- */
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
index 1bcc3e5..e8d18b7 100644
--- a/hw/audio/intel-hda.c
+++ b/hw/audio/intel-hda.c
@@ -181,7 +181,9 @@
IntelHDAStream st[8];
/* state */
+ MemoryRegion container;
MemoryRegion mmio;
+ MemoryRegion alias;
uint32_t rirb_count;
int64_t wall_base_ns;
@@ -670,12 +672,6 @@
.offset = offsetof(IntelHDAState, wall_clk),
.rhandler = intel_hda_get_wall_clk,
},
- [ ICH6_REG_WALLCLK + 0x2000 ] = {
- .name = "WALLCLK(alias)",
- .size = 4,
- .offset = offsetof(IntelHDAState, wall_clk),
- .rhandler = intel_hda_get_wall_clk,
- },
/* dma engine */
[ ICH6_REG_CORBLBASE ] = {
@@ -837,12 +833,6 @@
.size = 4, \
.offset = offsetof(IntelHDAState, st[_i].lpib), \
}, \
- [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
- .stream = _i, \
- .name = _t stringify(_i) " LPIB(alias)", \
- .size = 4, \
- .offset = offsetof(IntelHDAState, st[_i].lpib), \
- }, \
[ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
.stream = _i, \
.name = _t stringify(_i) " CBL", \
@@ -1125,9 +1115,15 @@
error_free(err);
}
+ memory_region_init(&d->container, OBJECT(d),
+ "intel-hda-container", 0x4000);
memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
- "intel-hda", 0x4000);
- pci_register_bar(&d->pci, 0, 0, &d->mmio);
+ "intel-hda", 0x2000);
+ memory_region_add_subregion(&d->container, 0x0000, &d->mmio);
+ memory_region_init_alias(&d->alias, OBJECT(d), "intel-hda-alias",
+ &d->mmio, 0, 0x2000);
+ memory_region_add_subregion(&d->container, 0x2000, &d->alias);
+ pci_register_bar(&d->pci, 0, 0, &d->container);
hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
intel_hda_response, intel_hda_xfer);
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 61f2fb8..8227088 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -32,17 +32,7 @@
#include "qemu/module.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
-
-#ifndef M25P80_ERR_DEBUG
-#define M25P80_ERR_DEBUG 0
-#endif
-
-#define DB_PRINT_L(level, ...) do { \
- if (M25P80_ERR_DEBUG > (level)) { \
- fprintf(stderr, ": %s: ", __func__); \
- fprintf(stderr, ## __VA_ARGS__); \
- } \
-} while (0)
+#include "trace.h"
/* Fields for FlashPartInfo->flags */
@@ -574,7 +564,8 @@
abort();
}
- DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
+ trace_m25p80_flash_erase(s, offset, len);
+
if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
" device\n", len);
@@ -607,8 +598,7 @@
}
if ((prev ^ data) & data) {
- DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8
- " -> %" PRIx8 "\n", addr, prev, data);
+ trace_m25p80_programming_zero_to_one(s, addr, prev, data);
}
if (s->pi->flags & EEPROM) {
@@ -662,6 +652,9 @@
s->state = STATE_IDLE;
+ trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
+ s->cur_addr);
+
switch (s->cmd_in_progress) {
case DPP:
case QPP:
@@ -825,7 +818,7 @@
break;
}
- DB_PRINT_L(0, "Reset done.\n");
+ trace_m25p80_reset_done(s);
}
static void decode_fast_read_cmd(Flash *s)
@@ -941,9 +934,10 @@
static void decode_new_cmd(Flash *s, uint32_t value)
{
- s->cmd_in_progress = value;
int i;
- DB_PRINT_L(0, "decoded new command:%x\n", value);
+
+ s->cmd_in_progress = value;
+ trace_m25p80_command_decoded(s, value);
if (value != RESET_MEMORY) {
s->reset_enable = false;
@@ -1042,12 +1036,15 @@
break;
case JEDEC_READ:
- DB_PRINT_L(0, "populated jedec code\n");
+ trace_m25p80_populated_jedec(s);
for (i = 0; i < s->pi->id_len; i++) {
s->data[i] = s->pi->id[i];
}
+ for (; i < SPI_NOR_MAX_ID_LEN; i++) {
+ s->data[i] = 0;
+ }
- s->len = s->pi->id_len;
+ s->len = SPI_NOR_MAX_ID_LEN;
s->pos = 0;
s->state = STATE_READING_DATA;
break;
@@ -1063,7 +1060,7 @@
case BULK_ERASE_60:
case BULK_ERASE:
if (s->write_enable) {
- DB_PRINT_L(0, "chip erase\n");
+ trace_m25p80_chip_erase(s);
flash_erase(s, 0, BULK_ERASE);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
@@ -1164,6 +1161,11 @@
s->quad_enable = false;
break;
default:
+ s->pos = 0;
+ s->len = 1;
+ s->state = STATE_READING_DATA;
+ s->data_read_loop = true;
+ s->data[0] = 0;
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
break;
}
@@ -1184,7 +1186,7 @@
s->data_read_loop = false;
}
- DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
+ trace_m25p80_select(s, select ? "de" : "");
return 0;
}
@@ -1194,19 +1196,20 @@
Flash *s = M25P80(ss);
uint32_t r = 0;
+ trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
+ s->cur_addr, (uint8_t)tx);
+
switch (s->state) {
case STATE_PAGE_PROGRAM:
- DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
- s->cur_addr, (uint8_t)tx);
+ trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
flash_write8(s, s->cur_addr, (uint8_t)tx);
s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
break;
case STATE_READ:
r = s->storage[s->cur_addr];
- DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
- (uint8_t)r);
+ trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
break;
@@ -1244,6 +1247,7 @@
}
r = s->data[s->pos];
+ trace_m25p80_read_data(s, s->pos, (uint8_t)r);
s->pos++;
if (s->pos == s->len) {
s->pos = 0;
@@ -1281,7 +1285,7 @@
return;
}
- DB_PRINT_L(0, "Binding to IF_MTD drive\n");
+ trace_m25p80_binding(s);
s->storage = blk_blockalign(s->blk, s->size);
if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
@@ -1289,7 +1293,7 @@
return;
}
} else {
- DB_PRINT_L(0, "No BDRV - binding to RAM\n");
+ trace_m25p80_binding_no_bdrv(s);
s->storage = blk_blockalign(NULL, s->size);
memset(s->storage, 0xFF, s->size);
}
diff --git a/hw/block/trace-events b/hw/block/trace-events
index c03e80c..f78939f 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -134,3 +134,19 @@
xen_block_blockdev_del(const char *node_name) "%s"
xen_block_device_create(unsigned int number) "%u"
xen_block_device_destroy(unsigned int number) "%u"
+
+# m25p80.c
+m25p80_flash_erase(void *s, int offset, uint32_t len) "[%p] offset = 0x%"PRIx32", len = %u"
+m25p80_programming_zero_to_one(void *s, uint32_t addr, uint8_t prev, uint8_t data) "[%p] programming zero to one! addr=0x%"PRIx32" 0x%"PRIx8" -> 0x%"PRIx8
+m25p80_reset_done(void *s) "[%p] Reset done."
+m25p80_command_decoded(void *s, uint32_t cmd) "[%p] new command:0x%"PRIx32
+m25p80_complete_collecting(void *s, uint32_t cmd, int n, uint8_t ear, uint32_t cur_addr) "[%p] decode cmd: 0x%"PRIx32" len %d ear 0x%"PRIx8" addr 0x%"PRIx32
+m25p80_populated_jedec(void *s) "[%p] populated jedec code"
+m25p80_chip_erase(void *s) "[%p] chip erase"
+m25p80_select(void *s, const char *what) "[%p] %sselect"
+m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_addr=0x%"PRIx32" data=0x%"PRIx8
+m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
+m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
+m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
+m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
+m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
diff --git a/hw/block/xen-block.c b/hw/block/xen-block.c
index 3885464..07bb32e 100644
--- a/hw/block/xen-block.c
+++ b/hw/block/xen-block.c
@@ -998,29 +998,27 @@
XenBlockVdev *vdev = &blockdev->props.vdev;
XenBlockDrive *drive = blockdev->drive;
XenBlockIOThread *iothread = blockdev->iothread;
+ Error *local_err = NULL;
trace_xen_block_device_destroy(vdev->number);
object_unparent(OBJECT(xendev));
if (iothread) {
- Error *local_err = NULL;
-
xen_block_iothread_destroy(iothread, &local_err);
if (local_err) {
error_propagate_prepend(errp, local_err,
- "failed to destroy iothread: ");
+ "failed to destroy iothread: ");
return;
}
}
if (drive) {
- Error *local_err = NULL;
-
xen_block_drive_destroy(drive, &local_err);
if (local_err) {
error_propagate_prepend(errp, local_err,
- "failed to destroy drive: ");
+ "failed to destroy drive: ");
+ return;
}
}
}
diff --git a/hw/char/sclpconsole-lm.c b/hw/char/sclpconsole-lm.c
index c420dc0..2b5f37b 100644
--- a/hw/char/sclpconsole-lm.c
+++ b/hw/char/sclpconsole-lm.c
@@ -31,7 +31,7 @@
typedef struct OprtnsCommand {
EventBufferHeader header;
MDMSU message_unit;
- char data[0];
+ char data[];
} QEMU_PACKED OprtnsCommand;
/* max size for line-mode data in 4K SCCB page */
diff --git a/hw/char/sclpconsole.c b/hw/char/sclpconsole.c
index 1fa124d..5c76649 100644
--- a/hw/char/sclpconsole.c
+++ b/hw/char/sclpconsole.c
@@ -25,7 +25,7 @@
typedef struct ASCIIConsoleData {
EventBufferHeader ebh;
- char data[0];
+ char data[];
} QEMU_PACKED ASCIIConsoleData;
/* max size for ASCII data in 4K SCCB page */
diff --git a/hw/char/serial.c b/hw/char/serial.c
index 9298881..2ab8b69 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -997,7 +997,7 @@
return;
}
- memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
+ memory_region_init_io(&s->io, OBJECT(dev), &serial_io_ops, s, "serial", 8);
sysbus_init_mmio(SYS_BUS_DEVICE(sio), &s->io);
sysbus_init_irq(SYS_BUS_DEVICE(sio), &s->irq);
}
@@ -1106,8 +1106,9 @@
return;
}
- memory_region_init_io(&s->io, NULL, &serial_mm_ops[smm->endianness], smm,
- "serial", 8 << smm->regshift);
+ memory_region_init_io(&s->io, OBJECT(dev),
+ &serial_mm_ops[smm->endianness], smm, "serial",
+ 8 << smm->regshift);
sysbus_init_mmio(SYS_BUS_DEVICE(smm), &s->io);
sysbus_init_irq(SYS_BUS_DEVICE(smm), &smm->serial.irq);
}
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index fe65ca6..3b2363f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -177,7 +177,7 @@
}
-static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg)
+static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
return 0;
}
diff --git a/hw/core/loader.c b/hw/core/loader.c
index d1b78f6..eeef6da 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -1119,19 +1119,26 @@
{
Rom *rom;
- /*
- * We don't need to fill in the RAM with ROM data because we'll fill
- * the data in during the next incoming migration in all cases. Note
- * that some of those RAMs can actually be modified by the guest on ARM
- * so this is probably the only right thing to do here.
- */
- if (runstate_check(RUN_STATE_INMIGRATE))
- return;
-
QTAILQ_FOREACH(rom, &roms, next) {
if (rom->fw_file) {
continue;
}
+ /*
+ * We don't need to fill in the RAM with ROM data because we'll fill
+ * the data in during the next incoming migration in all cases. Note
+ * that some of those RAMs can actually be modified by the guest.
+ */
+ if (runstate_check(RUN_STATE_INMIGRATE)) {
+ if (rom->data && rom->isrom) {
+ /*
+ * Free it so that a rom_reset after migration doesn't
+ * overwrite a potentially modified 'rom'.
+ */
+ rom_free_data(rom);
+ }
+ continue;
+ }
+
if (rom->data == NULL) {
continue;
}
diff --git a/hw/core/platform-bus.c b/hw/core/platform-bus.c
index 22c5f76..d494e5c 100644
--- a/hw/core/platform-bus.c
+++ b/hw/core/platform-bus.c
@@ -187,7 +187,8 @@
d = SYS_BUS_DEVICE(dev);
pbus = PLATFORM_BUS_DEVICE(dev);
- memory_region_init(&pbus->mmio, NULL, "platform bus", pbus->mmio_size);
+ memory_region_init(&pbus->mmio, OBJECT(dev), "platform bus",
+ pbus->mmio_size);
sysbus_init_mmio(d, &pbus->mmio);
pbus->used_irqs = bitmap_new(pbus->num_irqs);
diff --git a/hw/display/cg3.c b/hw/display/cg3.c
index 4fb67c6..a1ede10 100644
--- a/hw/display/cg3.c
+++ b/hw/display/cg3.c
@@ -287,9 +287,8 @@
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
CG3State *s = CG3(obj);
- memory_region_init_ram_nomigrate(&s->rom, obj, "cg3.prom", FCODE_MAX_ROM_SIZE,
- &error_fatal);
- memory_region_set_readonly(&s->rom, true);
+ memory_region_init_rom_nomigrate(&s->rom, obj, "cg3.prom",
+ FCODE_MAX_ROM_SIZE, &error_fatal);
sysbus_init_mmio(sbd, &s->rom);
memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg",
diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c
index 55185c9..adcba96 100644
--- a/hw/display/g364fb.c
+++ b/hw/display/g364fb.c
@@ -477,7 +477,8 @@
s->con = graphic_console_init(dev, 0, &g364fb_ops, s);
- memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
+ memory_region_init_io(&s->mem_ctrl, OBJECT(dev), &g364fb_ctrl_ops, s,
+ "ctrl", 0x180000);
memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram",
s->vram_size, s->vram);
vmstate_register_ram(&s->mem_vram, dev);
diff --git a/hw/display/macfb.c b/hw/display/macfb.c
index 8bff16d..b68faff 100644
--- a/hw/display/macfb.c
+++ b/hw/display/macfb.c
@@ -362,8 +362,8 @@
return;
}
- memory_region_init_io(&s->mem_ctrl, NULL, &macfb_ctrl_ops, s, "macfb-ctrl",
- 0x1000);
+ memory_region_init_io(&s->mem_ctrl, OBJECT(dev), &macfb_ctrl_ops, s,
+ "macfb-ctrl", 0x1000);
memory_region_init_ram_nomigrate(&s->mem_vram, OBJECT(s), "macfb-vram",
MACFB_VRAM_SIZE, errp);
diff --git a/hw/display/tcx.c b/hw/display/tcx.c
index ca458f9..76de16e 100644
--- a/hw/display/tcx.c
+++ b/hw/display/tcx.c
@@ -755,9 +755,8 @@
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
TCXState *s = TCX(obj);
- memory_region_init_ram_nomigrate(&s->rom, obj, "tcx.prom", FCODE_MAX_ROM_SIZE,
- &error_fatal);
- memory_region_set_readonly(&s->rom, true);
+ memory_region_init_rom_nomigrate(&s->rom, obj, "tcx.prom",
+ FCODE_MAX_ROM_SIZE, &error_fatal);
sysbus_init_mmio(sbd, &s->rom);
/* 2/STIP : Stippler */
diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c
index bad8deb..ef15c06 100644
--- a/hw/dma/i8257.c
+++ b/hw/dma/i8257.c
@@ -553,7 +553,7 @@
I8257State *d = I8257(dev);
int i;
- memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
+ memory_region_init_io(&d->channel_io, OBJECT(dev), &channel_io_ops, d,
"dma-chan", 8 << d->dshift);
memory_region_add_subregion(isa_address_space_io(isa),
d->base, &d->channel_io);
diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c
index 21e2c36..7434d27 100644
--- a/hw/dma/rc4030.c
+++ b/hw/dma/rc4030.c
@@ -679,9 +679,9 @@
s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
rc4030_periodic_timer, s);
- memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s,
+ memory_region_init_io(&s->iomem_chipset, o, &rc4030_ops, s,
"rc4030.chipset", 0x300);
- memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s,
+ memory_region_init_io(&s->iomem_jazzio, o, &jazzio_ops, s,
"rc4030.jazzio", 0x00001000);
memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr),
diff --git a/hw/dma/soc_dma.c b/hw/dma/soc_dma.c
index c3e4158..3a43005 100644
--- a/hw/dma/soc_dma.c
+++ b/hw/dma/soc_dma.c
@@ -80,7 +80,7 @@
} *memmap;
int memmap_size;
- struct soc_dma_ch_s ch[0];
+ struct soc_dma_ch_s ch[];
};
static void soc_dma_ch_schedule(struct soc_dma_ch_s *ch, int delay_bytes)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 204b684..df7ad25 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3094,6 +3094,12 @@
uint16_t mask, source_id;
uint8_t bus, bus_max, bus_min;
+ if (index >= iommu->intr_size) {
+ error_report_once("%s: index too large: ind=0x%x",
+ __func__, index);
+ return -VTD_FR_IR_INDEX_OVER;
+ }
+
addr = iommu->intr_root + index * sizeof(*entry);
if (dma_memory_read(&address_space_memory, addr, entry,
sizeof(*entry))) {
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 7f38e6b..0824652 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -328,7 +328,7 @@
uint64_t next;
uint32_t type;
uint32_t len;
- uint8_t data[0];
+ uint8_t data[];
} __attribute__((packed));
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 20c8155..6608d72 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -677,8 +677,8 @@
uint64_t timas[2 * 2];
/* Interrupt number ranges for the IPIs */
uint32_t lisn_ranges[] = {
- cpu_to_be32(0),
- cpu_to_be32(nr_servers),
+ cpu_to_be32(SPAPR_IRQ_IPI),
+ cpu_to_be32(SPAPR_IRQ_IPI + nr_servers),
};
/*
* EQ size - the sizes of pages supported by the system 4K, 64K,
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index cb79616..fbc3165 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -625,36 +625,21 @@
.endianness = DEVICE_LITTLE_ENDIAN
};
-static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
- uint32_t value = lpc->sci_gsi;
-
- visit_type_uint32(v, name, &value, errp);
-}
-
-static void ich9_lpc_add_properties(ICH9LPCState *lpc)
-{
- static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
- static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
-
- object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32",
- ich9_lpc_get_sci_int,
- NULL, NULL, NULL, NULL);
- object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
- &acpi_enable_cmd, NULL);
- object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
- &acpi_disable_cmd, NULL);
-
- ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL);
-}
-
static void ich9_lpc_initfn(Object *obj)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
- ich9_lpc_add_properties(lpc);
+ static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
+ static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
+
+ object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT,
+ &lpc->sci_gsi, OBJ_PROP_FLAG_READ, NULL);
+ object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
+ &acpi_enable_cmd, OBJ_PROP_FLAG_READ, NULL);
+ object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
+ &acpi_disable_cmd, OBJ_PROP_FLAG_READ, NULL);
+
+ ich9_pm_add_properties(obj, &lpc->pm, NULL);
}
static void ich9_lpc_realize(PCIDevice *d, Error **errp)
diff --git a/hw/m68k/bootinfo.h b/hw/m68k/bootinfo.h
index 5f8ded2..c954270 100644
--- a/hw/m68k/bootinfo.h
+++ b/hw/m68k/bootinfo.h
@@ -14,7 +14,7 @@
struct bi_record {
uint16_t tag; /* tag ID */
uint16_t size; /* size of record */
- uint32_t data[0]; /* data */
+ uint32_t data[]; /* data */
};
/* machine independent tags */
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index c5699f6..81749e7 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -399,13 +399,12 @@
uint8_t *ptr;
/* allocate and load BIOS */
rom = g_malloc(sizeof(*rom));
- memory_region_init_ram(rom, NULL, "m68k_mac.rom", MACROM_SIZE,
+ memory_region_init_rom(rom, NULL, "m68k_mac.rom", MACROM_SIZE,
&error_abort);
if (bios_name == NULL) {
bios_name = MACROM_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
- memory_region_set_readonly(rom, true);
memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
/* Load MacROM binary */
diff --git a/hw/misc/edu.c b/hw/misc/edu.c
index d5e2bdb..ff10f5b 100644
--- a/hw/misc/edu.c
+++ b/hw/misc/edu.c
@@ -396,21 +396,14 @@
msi_uninit(pdev);
}
-static void edu_obj_uint64(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- uint64_t *val = opaque;
-
- visit_type_uint64(v, name, val, errp);
-}
-
static void edu_instance_init(Object *obj)
{
EduState *edu = EDU(obj);
edu->dma_mask = (1UL << 28) - 1;
- object_property_add(obj, "dma_mask", "uint64", edu_obj_uint64,
- edu_obj_uint64, NULL, &edu->dma_mask, NULL);
+ object_property_add_uint64_ptr(obj, "dma_mask",
+ &edu->dma_mask, OBJ_PROP_FLAG_READWRITE,
+ NULL);
}
static void edu_class_init(ObjectClass *class, void *data)
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 1a0fad7..a8dc9b3 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -832,7 +832,6 @@
IVShmemState *s = IVSHMEM_COMMON(dev);
Error *err = NULL;
uint8_t *pci_conf;
- Error *local_err = NULL;
/* IRQFD requires MSI */
if (ivshmem_has_feature(s, IVSHMEM_IOEVENTFD) &&
@@ -899,9 +898,9 @@
if (!ivshmem_is_master(s)) {
error_setg(&s->migration_blocker,
"Migration is disabled when using feature 'peer mode' in device 'ivshmem'");
- migrate_add_blocker(s->migration_blocker, &local_err);
- if (local_err) {
- error_propagate(errp, local_err);
+ migrate_add_blocker(s->migration_blocker, &err);
+ if (err) {
+ error_propagate(errp, err);
error_free(s->migration_blocker);
return;
}
diff --git a/hw/misc/omap_l4.c b/hw/misc/omap_l4.c
index 61b6df5..54aeaec 100644
--- a/hw/misc/omap_l4.c
+++ b/hw/misc/omap_l4.c
@@ -24,7 +24,7 @@
MemoryRegion *address_space;
hwaddr base;
int ta_num;
- struct omap_target_agent_s ta[0];
+ struct omap_target_agent_s ta[];
};
struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 81fc13e..1563c11 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -986,13 +986,12 @@
s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
- memory_region_init_ram(&s->prom, OBJECT(dev),
- "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
+ memory_region_init_rom(&s->prom, OBJECT(dev), "dp8393x-prom",
+ SONIC_PROM_SIZE, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
- memory_region_set_readonly(&s->prom, true);
prom = memory_region_get_ram_ptr(&s->prom);
checksum = 0;
for (i = 0; i < 6; i++) {
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 6a124a1..5c145a8 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -855,13 +855,15 @@
break;
case ENET_TGSR:
/* implement clear timer flag */
- value = value & 0x0000000f;
+ s->regs[index] &= ~(value & 0x0000000f); /* all bits W1C */
break;
case ENET_TCSR0:
case ENET_TCSR1:
case ENET_TCSR2:
case ENET_TCSR3:
- value = value & 0x000000fd;
+ s->regs[index] &= ~(value & 0x00000080); /* W1C bits */
+ s->regs[index] &= ~0x0000007d; /* writable fields */
+ s->regs[index] |= (value & 0x0000007d);
break;
case ENET_TCCR0:
case ENET_TCCR1:
diff --git a/hw/nvram/eeprom93xx.c b/hw/nvram/eeprom93xx.c
index 07f0954..ca6f591 100644
--- a/hw/nvram/eeprom93xx.c
+++ b/hw/nvram/eeprom93xx.c
@@ -86,7 +86,7 @@
uint8_t addrbits;
uint16_t size;
uint16_t data;
- uint16_t contents[0];
+ uint16_t contents[];
};
/* Code for saving and restoring of EEPROM state. */
diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c
index 1aff72b..1a02e9a 100644
--- a/hw/pci-host/prep.c
+++ b/hw/pci-host/prep.c
@@ -325,9 +325,8 @@
d->config[0x0D] = 0x10; // latency_timer
d->config[0x34] = 0x00; // capabilities_pointer
- memory_region_init_ram_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
- &error_fatal);
- memory_region_set_readonly(&s->bios, true);
+ memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
+ &error_fatal);
memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
&s->bios);
if (s->bios_name) {
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 993f467..2bbc90b 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -166,14 +166,6 @@
visit_type_uint64(v, name, &value, errp);
}
-static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
-
- visit_type_uint64(v, name, &e->size, errp);
-}
-
/*
* NOTE: setting defaults for the mch.* fields in this table
* doesn't work, because mch is a separate QOM object that is
@@ -214,6 +206,7 @@
{
Q35PCIHost *s = Q35_HOST_DEVICE(obj);
PCIHostState *phb = PCI_HOST_BRIDGE(obj);
+ PCIExpressHost *pehb = PCIE_HOST_BRIDGE(obj);
memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
"pci-conf-idx", 4);
@@ -243,9 +236,8 @@
q35_host_get_pci_hole64_end,
NULL, NULL, NULL, NULL);
- object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64",
- q35_host_get_mmcfg_size,
- NULL, NULL, NULL, NULL);
+ object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE,
+ &pehb->size, OBJ_PROP_FLAG_READ, NULL);
object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
(Object **) &s->mch.ram_memory,
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index b8189bf..b2ec372 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -155,13 +155,12 @@
memory_region_add_subregion(get_system_memory(), 0, machine->ram);
/* allocate and load BIOS */
- memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
+ memory_region_init_rom(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
&error_fatal);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
- memory_region_set_readonly(bios, true);
memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 440c406..faaa165 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -129,13 +129,12 @@
memory_region_add_subregion(sysmem, 0, machine->ram);
/* allocate and load BIOS */
- memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
+ memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
&error_fatal);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
- memory_region_set_readonly(bios, true);
memory_region_add_subregion(sysmem, PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index f150dec..b5ffa48 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -829,7 +829,7 @@
bool hostboot_mode = !!pnv->fw_load_addr;
/* let isa_bus_new() create its own bridge on SysBus otherwise
- * devices speficied on the command line won't find the bus and
+ * devices specified on the command line won't find the bus and
* will fail to create.
*/
isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index de93c40..e6bffb9 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -199,7 +199,7 @@
#endif
{
bios = g_new(MemoryRegion, 1);
- memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE,
+ memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
&error_fatal);
if (bios_name == NULL)
@@ -223,7 +223,6 @@
/* Avoid an uninitialized variable warning */
bios_size = -1;
}
- memory_region_set_readonly(bios, true);
}
/* Register FPGA */
ref405ep_fpga_init(sysmem, 0xF0300000);
@@ -471,7 +470,7 @@
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
bios = g_new(MemoryRegion, 1);
- memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
+ memory_region_init_rom(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
&error_fatal);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
@@ -489,7 +488,6 @@
error_report("Could not load PowerPC BIOS '%s'", bios_name);
exit(1);
}
- memory_region_set_readonly(bios, true);
}
/* Register Linux flash */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index cc10798..9a2bd50 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -103,7 +103,7 @@
#define FW_OVERHEAD 0x2800000
#define KERNEL_LOAD_ADDR FW_MAX_SIZE
-#define MIN_RMA_SLOF 128UL
+#define MIN_RMA_SLOF (128 * MiB)
#define PHANDLE_INTC 0x00001111
@@ -217,10 +217,9 @@
sizeof(associativity));
}
-/* Populate the "ibm,pa-features" property */
-static void spapr_populate_pa_features(SpaprMachineState *spapr,
- PowerPCCPU *cpu,
- void *fdt, int offset)
+static void spapr_dt_pa_features(SpaprMachineState *spapr,
+ PowerPCCPU *cpu,
+ void *fdt, int offset)
{
uint8_t pa_features_206[] = { 6, 0,
0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
@@ -315,8 +314,8 @@
g_string_append_len(s, s1, strlen(s1) + 1);
}
-static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
- hwaddr size)
+static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start,
+ hwaddr size)
{
uint32_t associativity[] = {
cpu_to_be32(0x4), /* length */
@@ -341,9 +340,294 @@
return off;
}
-static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
+static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
+{
+ MemoryDeviceInfoList *info;
+
+ for (info = list; info; info = info->next) {
+ MemoryDeviceInfo *value = info->value;
+
+ if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
+ PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
+
+ if (addr >= pcdimm_info->addr &&
+ addr < (pcdimm_info->addr + pcdimm_info->size)) {
+ return pcdimm_info->node;
+ }
+ }
+ }
+
+ return -1;
+}
+
+struct sPAPRDrconfCellV2 {
+ uint32_t seq_lmbs;
+ uint64_t base_addr;
+ uint32_t drc_index;
+ uint32_t aa_index;
+ uint32_t flags;
+} QEMU_PACKED;
+
+typedef struct DrconfCellQueue {
+ struct sPAPRDrconfCellV2 cell;
+ QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
+} DrconfCellQueue;
+
+static DrconfCellQueue *
+spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
+ uint32_t drc_index, uint32_t aa_index,
+ uint32_t flags)
+{
+ DrconfCellQueue *elem;
+
+ elem = g_malloc0(sizeof(*elem));
+ elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
+ elem->cell.base_addr = cpu_to_be64(base_addr);
+ elem->cell.drc_index = cpu_to_be32(drc_index);
+ elem->cell.aa_index = cpu_to_be32(aa_index);
+ elem->cell.flags = cpu_to_be32(flags);
+
+ return elem;
+}
+
+static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt,
+ int offset, MemoryDeviceInfoList *dimms)
{
MachineState *machine = MACHINE(spapr);
+ uint8_t *int_buf, *cur_index;
+ int ret;
+ uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
+ uint64_t addr, cur_addr, size;
+ uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
+ uint64_t mem_end = machine->device_memory->base +
+ memory_region_size(&machine->device_memory->mr);
+ uint32_t node, buf_len, nr_entries = 0;
+ SpaprDrc *drc;
+ DrconfCellQueue *elem, *next;
+ MemoryDeviceInfoList *info;
+ QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
+ = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
+
+ /* Entry to cover RAM and the gap area */
+ elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
+ SPAPR_LMB_FLAGS_RESERVED |
+ SPAPR_LMB_FLAGS_DRC_INVALID);
+ QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
+ nr_entries++;
+
+ cur_addr = machine->device_memory->base;
+ for (info = dimms; info; info = info->next) {
+ PCDIMMDeviceInfo *di = info->value->u.dimm.data;
+
+ addr = di->addr;
+ size = di->size;
+ node = di->node;
+
+ /*
+ * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
+ * area is marked hotpluggable in the next iteration for the bigger
+ * chunk including the NVDIMM occupied area.
+ */
+ if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM)
+ continue;
+
+ /* Entry for hot-pluggable area */
+ if (cur_addr < addr) {
+ drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
+ g_assert(drc);
+ elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
+ cur_addr, spapr_drc_index(drc), -1, 0);
+ QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
+ nr_entries++;
+ }
+
+ /* Entry for DIMM */
+ drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
+ g_assert(drc);
+ elem = spapr_get_drconf_cell(size / lmb_size, addr,
+ spapr_drc_index(drc), node,
+ SPAPR_LMB_FLAGS_ASSIGNED);
+ QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
+ nr_entries++;
+ cur_addr = addr + size;
+ }
+
+ /* Entry for remaining hotpluggable area */
+ if (cur_addr < mem_end) {
+ drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
+ g_assert(drc);
+ elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
+ cur_addr, spapr_drc_index(drc), -1, 0);
+ QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
+ nr_entries++;
+ }
+
+ buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
+ int_buf = cur_index = g_malloc0(buf_len);
+ *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
+ cur_index += sizeof(nr_entries);
+
+ QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
+ memcpy(cur_index, &elem->cell, sizeof(elem->cell));
+ cur_index += sizeof(elem->cell);
+ QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
+ g_free(elem);
+ }
+
+ ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
+ g_free(int_buf);
+ if (ret < 0) {
+ return -1;
+ }
+ return 0;
+}
+
+static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt,
+ int offset, MemoryDeviceInfoList *dimms)
+{
+ MachineState *machine = MACHINE(spapr);
+ int i, ret;
+ uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
+ uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
+ uint32_t nr_lmbs = (machine->device_memory->base +
+ memory_region_size(&machine->device_memory->mr)) /
+ lmb_size;
+ uint32_t *int_buf, *cur_index, buf_len;
+
+ /*
+ * Allocate enough buffer size to fit in ibm,dynamic-memory
+ */
+ buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
+ cur_index = int_buf = g_malloc0(buf_len);
+ int_buf[0] = cpu_to_be32(nr_lmbs);
+ cur_index++;
+ for (i = 0; i < nr_lmbs; i++) {
+ uint64_t addr = i * lmb_size;
+ uint32_t *dynamic_memory = cur_index;
+
+ if (i >= device_lmb_start) {
+ SpaprDrc *drc;
+
+ drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
+ g_assert(drc);
+
+ dynamic_memory[0] = cpu_to_be32(addr >> 32);
+ dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
+ dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
+ dynamic_memory[3] = cpu_to_be32(0); /* reserved */
+ dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
+ if (memory_region_present(get_system_memory(), addr)) {
+ dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
+ } else {
+ dynamic_memory[5] = cpu_to_be32(0);
+ }
+ } else {
+ /*
+ * LMB information for RMA, boot time RAM and gap b/n RAM and
+ * device memory region -- all these are marked as reserved
+ * and as having no valid DRC.
+ */
+ dynamic_memory[0] = cpu_to_be32(addr >> 32);
+ dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
+ dynamic_memory[2] = cpu_to_be32(0);
+ dynamic_memory[3] = cpu_to_be32(0); /* reserved */
+ dynamic_memory[4] = cpu_to_be32(-1);
+ dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
+ SPAPR_LMB_FLAGS_DRC_INVALID);
+ }
+
+ cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
+ }
+ ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
+ g_free(int_buf);
+ if (ret < 0) {
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * Adds ibm,dynamic-reconfiguration-memory node.
+ * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
+ * of this device tree node.
+ */
+static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr,
+ void *fdt)
+{
+ MachineState *machine = MACHINE(spapr);
+ int nb_numa_nodes = machine->numa_state->num_nodes;
+ int ret, i, offset;
+ uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
+ uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
+ uint32_t *int_buf, *cur_index, buf_len;
+ int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
+ MemoryDeviceInfoList *dimms = NULL;
+
+ /*
+ * Don't create the node if there is no device memory
+ */
+ if (machine->ram_size == machine->maxram_size) {
+ return 0;
+ }
+
+ offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
+
+ ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
+ sizeof(prop_lmb_size));
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
+ dimms = qmp_memory_device_list();
+ if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
+ ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms);
+ } else {
+ ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms);
+ }
+ qapi_free_MemoryDeviceInfoList(dimms);
+
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* ibm,associativity-lookup-arrays */
+ buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
+ cur_index = int_buf = g_malloc0(buf_len);
+ int_buf[0] = cpu_to_be32(nr_nodes);
+ int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
+ cur_index += 2;
+ for (i = 0; i < nr_nodes; i++) {
+ uint32_t associativity[] = {
+ cpu_to_be32(0x0),
+ cpu_to_be32(0x0),
+ cpu_to_be32(0x0),
+ cpu_to_be32(i)
+ };
+ memcpy(cur_index, associativity, sizeof(associativity));
+ cur_index += 4;
+ }
+ ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
+ (cur_index - int_buf) * sizeof(uint32_t));
+ g_free(int_buf);
+
+ return ret;
+}
+
+static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt)
+{
+ MachineState *machine = MACHINE(spapr);
+ SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
hwaddr mem_start, node_size;
int i, nb_nodes = machine->numa_state->num_nodes;
NodeInfo *nodes = machine->numa_state->nodes;
@@ -363,7 +647,7 @@
if (!mem_start) {
/* spapr_machine_init() checks for rma_size <= node0_size
* already */
- spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
+ spapr_dt_memory_node(fdt, i, 0, spapr->rma_size);
mem_start += spapr->rma_size;
node_size -= spapr->rma_size;
}
@@ -375,17 +659,28 @@
sizetmp = 1ULL << ctzl(mem_start);
}
- spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
+ spapr_dt_memory_node(fdt, i, mem_start, sizetmp);
node_size -= sizetmp;
mem_start += sizetmp;
}
}
+ /* Generate ibm,dynamic-reconfiguration-memory node if required */
+ if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) {
+ int ret;
+
+ g_assert(smc->dr_lmb_enabled);
+ ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt);
+ if (ret) {
+ return ret;
+ }
+ }
+
return 0;
}
-static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
- SpaprMachineState *spapr)
+static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
+ SpaprMachineState *spapr)
{
MachineState *ms = MACHINE(spapr);
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -485,7 +780,7 @@
page_sizes_prop, page_sizes_prop_size)));
}
- spapr_populate_pa_features(spapr, cpu, fdt, offset);
+ spapr_dt_pa_features(spapr, cpu, fdt, offset);
_FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
cs->cpu_index / vcpus_per_socket)));
@@ -519,7 +814,7 @@
pcc->lrg_decr_bits)));
}
-static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr)
+static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr)
{
CPUState **rev;
CPUState *cs;
@@ -563,13 +858,13 @@
offset = fdt_add_subnode(fdt, cpus_offset, nodename);
g_free(nodename);
_FDT(offset);
- spapr_populate_cpu_dt(cs, fdt, offset, spapr);
+ spapr_dt_cpu(cs, fdt, offset, spapr);
}
g_free(rev);
}
-static int spapr_rng_populate_dt(void *fdt)
+static int spapr_dt_rng(void *fdt)
{
int node;
int ret;
@@ -592,317 +887,6 @@
return ret ? -1 : 0;
}
-static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
-{
- MemoryDeviceInfoList *info;
-
- for (info = list; info; info = info->next) {
- MemoryDeviceInfo *value = info->value;
-
- if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
- PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
-
- if (addr >= pcdimm_info->addr &&
- addr < (pcdimm_info->addr + pcdimm_info->size)) {
- return pcdimm_info->node;
- }
- }
- }
-
- return -1;
-}
-
-struct sPAPRDrconfCellV2 {
- uint32_t seq_lmbs;
- uint64_t base_addr;
- uint32_t drc_index;
- uint32_t aa_index;
- uint32_t flags;
-} QEMU_PACKED;
-
-typedef struct DrconfCellQueue {
- struct sPAPRDrconfCellV2 cell;
- QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
-} DrconfCellQueue;
-
-static DrconfCellQueue *
-spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
- uint32_t drc_index, uint32_t aa_index,
- uint32_t flags)
-{
- DrconfCellQueue *elem;
-
- elem = g_malloc0(sizeof(*elem));
- elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
- elem->cell.base_addr = cpu_to_be64(base_addr);
- elem->cell.drc_index = cpu_to_be32(drc_index);
- elem->cell.aa_index = cpu_to_be32(aa_index);
- elem->cell.flags = cpu_to_be32(flags);
-
- return elem;
-}
-
-/* ibm,dynamic-memory-v2 */
-static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt,
- int offset, MemoryDeviceInfoList *dimms)
-{
- MachineState *machine = MACHINE(spapr);
- uint8_t *int_buf, *cur_index;
- int ret;
- uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
- uint64_t addr, cur_addr, size;
- uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
- uint64_t mem_end = machine->device_memory->base +
- memory_region_size(&machine->device_memory->mr);
- uint32_t node, buf_len, nr_entries = 0;
- SpaprDrc *drc;
- DrconfCellQueue *elem, *next;
- MemoryDeviceInfoList *info;
- QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
- = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
-
- /* Entry to cover RAM and the gap area */
- elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
- SPAPR_LMB_FLAGS_RESERVED |
- SPAPR_LMB_FLAGS_DRC_INVALID);
- QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
- nr_entries++;
-
- cur_addr = machine->device_memory->base;
- for (info = dimms; info; info = info->next) {
- PCDIMMDeviceInfo *di = info->value->u.dimm.data;
-
- addr = di->addr;
- size = di->size;
- node = di->node;
-
- /*
- * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
- * area is marked hotpluggable in the next iteration for the bigger
- * chunk including the NVDIMM occupied area.
- */
- if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM)
- continue;
-
- /* Entry for hot-pluggable area */
- if (cur_addr < addr) {
- drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
- g_assert(drc);
- elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
- cur_addr, spapr_drc_index(drc), -1, 0);
- QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
- nr_entries++;
- }
-
- /* Entry for DIMM */
- drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
- g_assert(drc);
- elem = spapr_get_drconf_cell(size / lmb_size, addr,
- spapr_drc_index(drc), node,
- SPAPR_LMB_FLAGS_ASSIGNED);
- QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
- nr_entries++;
- cur_addr = addr + size;
- }
-
- /* Entry for remaining hotpluggable area */
- if (cur_addr < mem_end) {
- drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
- g_assert(drc);
- elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
- cur_addr, spapr_drc_index(drc), -1, 0);
- QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
- nr_entries++;
- }
-
- buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
- int_buf = cur_index = g_malloc0(buf_len);
- *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
- cur_index += sizeof(nr_entries);
-
- QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
- memcpy(cur_index, &elem->cell, sizeof(elem->cell));
- cur_index += sizeof(elem->cell);
- QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
- g_free(elem);
- }
-
- ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
- g_free(int_buf);
- if (ret < 0) {
- return -1;
- }
- return 0;
-}
-
-/* ibm,dynamic-memory */
-static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt,
- int offset, MemoryDeviceInfoList *dimms)
-{
- MachineState *machine = MACHINE(spapr);
- int i, ret;
- uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
- uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
- uint32_t nr_lmbs = (machine->device_memory->base +
- memory_region_size(&machine->device_memory->mr)) /
- lmb_size;
- uint32_t *int_buf, *cur_index, buf_len;
-
- /*
- * Allocate enough buffer size to fit in ibm,dynamic-memory
- */
- buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
- cur_index = int_buf = g_malloc0(buf_len);
- int_buf[0] = cpu_to_be32(nr_lmbs);
- cur_index++;
- for (i = 0; i < nr_lmbs; i++) {
- uint64_t addr = i * lmb_size;
- uint32_t *dynamic_memory = cur_index;
-
- if (i >= device_lmb_start) {
- SpaprDrc *drc;
-
- drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
- g_assert(drc);
-
- dynamic_memory[0] = cpu_to_be32(addr >> 32);
- dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
- dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
- dynamic_memory[3] = cpu_to_be32(0); /* reserved */
- dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
- if (memory_region_present(get_system_memory(), addr)) {
- dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
- } else {
- dynamic_memory[5] = cpu_to_be32(0);
- }
- } else {
- /*
- * LMB information for RMA, boot time RAM and gap b/n RAM and
- * device memory region -- all these are marked as reserved
- * and as having no valid DRC.
- */
- dynamic_memory[0] = cpu_to_be32(addr >> 32);
- dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
- dynamic_memory[2] = cpu_to_be32(0);
- dynamic_memory[3] = cpu_to_be32(0); /* reserved */
- dynamic_memory[4] = cpu_to_be32(-1);
- dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
- SPAPR_LMB_FLAGS_DRC_INVALID);
- }
-
- cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
- }
- ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
- g_free(int_buf);
- if (ret < 0) {
- return -1;
- }
- return 0;
-}
-
-/*
- * Adds ibm,dynamic-reconfiguration-memory node.
- * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
- * of this device tree node.
- */
-static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt)
-{
- MachineState *machine = MACHINE(spapr);
- int nb_numa_nodes = machine->numa_state->num_nodes;
- int ret, i, offset;
- uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
- uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
- uint32_t *int_buf, *cur_index, buf_len;
- int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
- MemoryDeviceInfoList *dimms = NULL;
-
- /*
- * Don't create the node if there is no device memory
- */
- if (machine->ram_size == machine->maxram_size) {
- return 0;
- }
-
- offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
-
- ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
- sizeof(prop_lmb_size));
- if (ret < 0) {
- return ret;
- }
-
- ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
- if (ret < 0) {
- return ret;
- }
-
- ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
- if (ret < 0) {
- return ret;
- }
-
- /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
- dimms = qmp_memory_device_list();
- if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
- ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
- } else {
- ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
- }
- qapi_free_MemoryDeviceInfoList(dimms);
-
- if (ret < 0) {
- return ret;
- }
-
- /* ibm,associativity-lookup-arrays */
- buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
- cur_index = int_buf = g_malloc0(buf_len);
- int_buf[0] = cpu_to_be32(nr_nodes);
- int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
- cur_index += 2;
- for (i = 0; i < nr_nodes; i++) {
- uint32_t associativity[] = {
- cpu_to_be32(0x0),
- cpu_to_be32(0x0),
- cpu_to_be32(0x0),
- cpu_to_be32(i)
- };
- memcpy(cur_index, associativity, sizeof(associativity));
- cur_index += 4;
- }
- ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
- (cur_index - int_buf) * sizeof(uint32_t));
- g_free(int_buf);
-
- return ret;
-}
-
-static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt,
- SpaprOptionVector *ov5_updates)
-{
- SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
- int ret = 0, offset;
-
- /* Generate ibm,dynamic-reconfiguration-memory node if required */
- if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
- g_assert(smc->dr_lmb_enabled);
- ret = spapr_populate_drconf_memory(spapr, fdt);
- if (ret) {
- return ret;
- }
- }
-
- offset = fdt_path_offset(fdt, "/chosen");
- if (offset < 0) {
- offset = fdt_add_subnode(fdt, 0, "chosen");
- if (offset < 0) {
- return offset;
- }
- }
- return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
- "ibm,architecture-vec-5");
-}
-
static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
{
MachineState *ms = MACHINE(spapr);
@@ -967,6 +951,29 @@
_FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
maxdomains, sizeof(maxdomains)));
+ /*
+ * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
+ * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
+ *
+ * The system reset requirements are driven by existing Linux and PowerVM
+ * implementation which (contrary to PAPR) saves r3 in the error log
+ * structure like machine check, so Linux expects to find the saved r3
+ * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
+ * does not look at the error value).
+ *
+ * System reset interrupts are not subject to interlock like machine
+ * check, so this memory area could be corrupted if the sreset is
+ * interrupted by a machine check (or vice versa) if it was shared. To
+ * prevent this, system reset uses per-CPU areas for the sreset save
+ * area. A system reset that interrupts a system reset handler could
+ * still overwrite this area, but Linux doesn't try to recover in that
+ * case anyway.
+ *
+ * The extra 8 bytes is required because Linux's FWNMI error log check
+ * is off-by-one.
+ */
+ _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX +
+ ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t)));
_FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
RTAS_ERROR_LOG_MAX));
_FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
@@ -1040,81 +1047,91 @@
val, sizeof(val)));
}
-static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
+static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
{
MachineState *machine = MACHINE(spapr);
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
int chosen;
- const char *boot_device = machine->boot_order;
- char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
- size_t cb = 0;
- char *bootlist = get_boot_devices_list(&cb);
_FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
- if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
- _FDT(fdt_setprop_string(fdt, chosen, "bootargs",
- machine->kernel_cmdline));
- }
- if (spapr->initrd_size) {
- _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
- spapr->initrd_base));
- _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
- spapr->initrd_base + spapr->initrd_size));
- }
+ if (reset) {
+ const char *boot_device = machine->boot_order;
+ char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
+ size_t cb = 0;
+ char *bootlist = get_boot_devices_list(&cb);
- if (spapr->kernel_size) {
- uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr),
- cpu_to_be64(spapr->kernel_size) };
-
- _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
- &kprop, sizeof(kprop)));
- if (spapr->kernel_le) {
- _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
+ if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
+ _FDT(fdt_setprop_string(fdt, chosen, "bootargs",
+ machine->kernel_cmdline));
}
- }
- if (boot_menu) {
- _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
- }
- _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
- _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
- _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
- if (cb && bootlist) {
- int i;
+ if (spapr->initrd_size) {
+ _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
+ spapr->initrd_base));
+ _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
+ spapr->initrd_base + spapr->initrd_size));
+ }
- for (i = 0; i < cb; i++) {
- if (bootlist[i] == '\n') {
- bootlist[i] = ' ';
+ if (spapr->kernel_size) {
+ uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr),
+ cpu_to_be64(spapr->kernel_size) };
+
+ _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
+ &kprop, sizeof(kprop)));
+ if (spapr->kernel_le) {
+ _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
}
}
- _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
- }
+ if (boot_menu) {
+ _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
+ }
+ _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
+ _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
+ _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
- if (boot_device && strlen(boot_device)) {
- _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
- }
+ if (cb && bootlist) {
+ int i;
- if (!spapr->has_graphics && stdout_path) {
+ for (i = 0; i < cb; i++) {
+ if (bootlist[i] == '\n') {
+ bootlist[i] = ' ';
+ }
+ }
+ _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
+ }
+
+ if (boot_device && strlen(boot_device)) {
+ _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
+ }
+
+ if (!spapr->has_graphics && stdout_path) {
+ /*
+ * "linux,stdout-path" and "stdout" properties are
+ * deprecated by linux kernel. New platforms should only
+ * use the "stdout-path" property. Set the new property
+ * and continue using older property to remain compatible
+ * with the existing firmware.
+ */
+ _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
+ _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
+ }
+
/*
- * "linux,stdout-path" and "stdout" properties are deprecated by linux
- * kernel. New platforms should only use the "stdout-path" property. Set
- * the new property and continue using older property to remain
- * compatible with the existing firmware.
+ * We can deal with BAR reallocation just fine, advertise it
+ * to the guest
*/
- _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
- _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
+ if (smc->linux_pci_probe) {
+ _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
+ }
+
+ spapr_dt_ov5_platform_support(spapr, fdt, chosen);
+
+ g_free(stdout_path);
+ g_free(bootlist);
}
- /* We can deal with BAR reallocation just fine, advertise it to the guest */
- if (smc->linux_pci_probe) {
- _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
- }
-
- spapr_dt_ov5_platform_support(spapr, fdt, chosen);
-
- g_free(stdout_path);
- g_free(bootlist);
+ _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5"));
}
static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
@@ -1192,7 +1209,7 @@
/* /interrupt controller */
spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC);
- ret = spapr_populate_memory(spapr, fdt);
+ ret = spapr_dt_memory(spapr, fdt);
if (ret < 0) {
error_report("couldn't setup memory nodes in fdt");
exit(1);
@@ -1202,7 +1219,7 @@
spapr_dt_vdevice(spapr->vio_bus, fdt);
if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
- ret = spapr_rng_populate_dt(fdt);
+ ret = spapr_dt_rng(fdt);
if (ret < 0) {
error_report("could not set up rng device in the fdt");
exit(1);
@@ -1217,8 +1234,7 @@
}
}
- /* cpus */
- spapr_populate_cpus_dt_node(fdt, spapr);
+ spapr_dt_cpus(fdt, spapr);
if (smc->dr_lmb_enabled) {
_FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
@@ -1240,9 +1256,7 @@
spapr_dt_rtas(spapr, fdt);
/* /chosen */
- if (reset) {
- spapr_dt_chosen(spapr, fdt);
- }
+ spapr_dt_chosen(spapr, fdt, reset);
/* /hypervisor */
if (kvm_enabled()) {
@@ -1261,13 +1275,6 @@
}
}
- /* ibm,client-architecture-support updates */
- ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
- if (ret < 0) {
- error_report("couldn't setup CAS properties fdt");
- exit(1);
- }
-
if (smc->dr_phb_enabled) {
ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
if (ret < 0) {
@@ -1569,7 +1576,7 @@
spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
}
-void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr)
+void spapr_setup_hpt(SpaprMachineState *spapr)
{
int hpt_shift;
@@ -1585,9 +1592,16 @@
}
spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
- if (spapr->vrma_adjust) {
- spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
- spapr->htab_shift);
+ if (kvm_enabled()) {
+ hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift);
+
+ /* Check our RMA fits in the possible VRMA */
+ if (vrma_limit < spapr->rma_size) {
+ error_report("Unable to create %" HWADDR_PRIu
+ "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB",
+ spapr->rma_size / MiB, vrma_limit / MiB);
+ exit(EXIT_FAILURE);
+ }
}
}
@@ -1627,7 +1641,7 @@
spapr->patb_entry = PATE1_GR;
spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
} else {
- spapr_setup_hpt_and_vrma(spapr);
+ spapr_setup_hpt(spapr);
}
qemu_devices_reset();
@@ -1691,16 +1705,17 @@
spapr->fdt_blob = fdt;
/* Set up the entry state */
- spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
+ spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0);
first_ppc_cpu->env.gpr[5] = 0;
spapr->cas_reboot = false;
- spapr->mc_status = -1;
- spapr->guest_machine_check_addr = -1;
+ spapr->fwnmi_system_reset_addr = -1;
+ spapr->fwnmi_machine_check_addr = -1;
+ spapr->fwnmi_machine_check_interlock = -1;
/* Signal all vCPUs waiting on this condition */
- qemu_cond_broadcast(&spapr->mc_delivery_cond);
+ qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond);
migrate_del_blocker(spapr->fwnmi_migration_blocker);
}
@@ -1989,7 +2004,7 @@
{
SpaprMachineState *spapr = (SpaprMachineState *)opaque;
- return spapr->guest_machine_check_addr != -1;
+ return spapr->fwnmi_machine_check_addr != -1;
}
static int spapr_fwnmi_pre_save(void *opaque)
@@ -2000,7 +2015,7 @@
* Check if machine check handling is in progress and print a
* warning message.
*/
- if (spapr->mc_status != -1) {
+ if (spapr->fwnmi_machine_check_interlock != -1) {
warn_report("A machine check is being handled during migration. The"
"handler may run and log hardware error on the destination");
}
@@ -2008,15 +2023,16 @@
return 0;
}
-static const VMStateDescription vmstate_spapr_machine_check = {
- .name = "spapr_machine_check",
+static const VMStateDescription vmstate_spapr_fwnmi = {
+ .name = "spapr_fwnmi",
.version_id = 1,
.minimum_version_id = 1,
.needed = spapr_fwnmi_needed,
.pre_save = spapr_fwnmi_pre_save,
.fields = (VMStateField[]) {
- VMSTATE_UINT64(guest_machine_check_addr, SpaprMachineState),
- VMSTATE_INT32(mc_status, SpaprMachineState),
+ VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState),
+ VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState),
+ VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState),
VMSTATE_END_OF_LIST()
},
};
@@ -2055,7 +2071,7 @@
&vmstate_spapr_cap_large_decr,
&vmstate_spapr_cap_ccf_assist,
&vmstate_spapr_cap_fwnmi,
- &vmstate_spapr_machine_check,
+ &vmstate_spapr_fwnmi,
NULL
}
};
@@ -2641,6 +2657,42 @@
return PCI_HOST_BRIDGE(dev);
}
+static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp)
+{
+ MachineState *machine = MACHINE(spapr);
+ SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
+ hwaddr rma_size = machine->ram_size;
+ hwaddr node0_size = spapr_node0_size(machine);
+
+ /* RMA has to fit in the first NUMA node */
+ rma_size = MIN(rma_size, node0_size);
+
+ /*
+ * VRMA access is via a special 1TiB SLB mapping, so the RMA can
+ * never exceed that
+ */
+ rma_size = MIN(rma_size, 1 * TiB);
+
+ /*
+ * Clamp the RMA size based on machine type. This is for
+ * migration compatibility with older qemu versions, which limited
+ * the RMA size for complicated and mostly bad reasons.
+ */
+ if (smc->rma_limit) {
+ rma_size = MIN(rma_size, smc->rma_limit);
+ }
+
+ if (rma_size < MIN_RMA_SLOF) {
+ error_setg(errp,
+ "pSeries SLOF firmware requires >= %" HWADDR_PRIx
+ "ldMiB guest RMA (Real Mode Area memory)",
+ MIN_RMA_SLOF / MiB);
+ return 0;
+ }
+
+ return rma_size;
+}
+
/* pSeries LPAR / sPAPR hardware init */
static void spapr_machine_init(MachineState *machine)
{
@@ -2652,7 +2704,6 @@
PCIHostState *phb;
int i;
MemoryRegion *sysmem = get_system_memory();
- hwaddr node0_size = spapr_node0_size(machine);
long load_limit, fw_size;
char *filename;
Error *resize_hpt_err = NULL;
@@ -2692,34 +2743,7 @@
exit(1);
}
- spapr->rma_size = node0_size;
-
- /* With KVM, we don't actually know whether KVM supports an
- * unbounded RMA (PR KVM) or is limited by the hash table size
- * (HV KVM using VRMA), so we always assume the latter
- *
- * In that case, we also limit the initial allocations for RTAS
- * etc... to 256M since we have no way to know what the VRMA size
- * is going to be as it depends on the size of the hash table
- * which isn't determined yet.
- */
- if (kvm_enabled()) {
- spapr->vrma_adjust = 1;
- spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
- }
-
- /* Actually we don't support unbounded RMA anymore since we added
- * proper emulation of HV mode. The max we can get is 16G which
- * also happens to be what we configure for PAPR mode so make sure
- * we don't do anything bigger than that
- */
- spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
-
- if (spapr->rma_size > node0_size) {
- error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
- spapr->rma_size);
- exit(1);
- }
+ spapr->rma_size = spapr_rma_size(spapr, &error_fatal);
/* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
@@ -2869,7 +2893,7 @@
spapr_create_lmb_dr_connectors(spapr);
}
- if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_ON) {
+ if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) {
/* Create the error string for live migration blocker */
error_setg(&spapr->fwnmi_migration_blocker,
"A machine check is being handled during migration. The handler"
@@ -2956,13 +2980,6 @@
}
}
- if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
- error_report(
- "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
- MIN_RMA_SLOF);
- exit(1);
- }
-
if (kernel_filename) {
uint64_t lowaddr = 0;
@@ -3045,7 +3062,7 @@
kvmppc_spapr_enable_inkernel_multitce();
}
- qemu_cond_init(&spapr->mc_delivery_cond);
+ qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond);
}
static int spapr_kvm_type(MachineState *machine, const char *vm_type)
@@ -3223,30 +3240,6 @@
}
}
-static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- visit_type_uint32(v, name, (uint32_t *)opaque, errp);
-}
-
-static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- visit_type_uint32(v, name, (uint32_t *)opaque, errp);
-}
-
-static void spapr_get_kernel_addr(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- visit_type_uint64(v, name, (uint64_t *)opaque, errp);
-}
-
-static void spapr_set_kernel_addr(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- visit_type_uint64(v, name, (uint64_t *)opaque, errp);
-}
-
static char *spapr_get_ic_mode(Object *obj, Error **errp)
{
SpaprMachineState *spapr = SPAPR_MACHINE(obj);
@@ -3344,17 +3337,19 @@
object_property_set_description(obj, "resize-hpt",
"Resizing of the Hash Page Table (enabled, disabled, required)",
NULL);
- object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
- spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
+ object_property_add_uint32_ptr(obj, "vsmt",
+ &spapr->vsmt, OBJ_PROP_FLAG_READWRITE,
+ &error_abort);
object_property_set_description(obj, "vsmt",
"Virtual SMT: KVM behaves as if this were"
" the host's SMT mode", &error_abort);
+
object_property_add_bool(obj, "vfio-no-msix-emulation",
spapr_get_msix_emulation, NULL, NULL);
- object_property_add(obj, "kernel-addr", "uint64", spapr_get_kernel_addr,
- spapr_set_kernel_addr, NULL, &spapr->kernel_addr,
- &error_abort);
+ object_property_add_uint64_ptr(obj, "kernel-addr",
+ &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE,
+ &error_abort);
object_property_set_description(obj, "kernel-addr",
stringify(KERNEL_LOAD_ADDR)
" for -kernel is the default",
@@ -3389,8 +3384,28 @@
void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
+ SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
+
cpu_synchronize_state(cs);
- ppc_cpu_do_system_reset(cs);
+ /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
+ if (spapr->fwnmi_system_reset_addr != -1) {
+ uint64_t rtas_addr, addr;
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ /* get rtas addr from fdt */
+ rtas_addr = spapr_get_rtas_addr();
+ if (!rtas_addr) {
+ qemu_system_guest_panicked(NULL);
+ return;
+ }
+
+ addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2;
+ stq_be_phys(&address_space_memory, addr, env->gpr[3]);
+ stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0);
+ env->gpr[3] = addr;
+ }
+ ppc_cpu_do_system_reset(cs, spapr->fwnmi_system_reset_addr);
}
static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
@@ -3411,8 +3426,8 @@
addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE;
node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP,
&error_abort);
- *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr,
- SPAPR_MEMORY_BLOCK_SIZE);
+ *fdt_start_offset = spapr_dt_memory_node(fdt, node, addr,
+ SPAPR_MEMORY_BLOCK_SIZE);
return 0;
}
@@ -3813,7 +3828,7 @@
offset = fdt_add_subnode(fdt, 0, nodename);
g_free(nodename);
- spapr_populate_cpu_dt(cs, fdt, offset, spapr);
+ spapr_dt_cpu(cs, fdt, offset, spapr);
*fdt_start_offset = offset;
return 0;
@@ -4526,7 +4541,7 @@
smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
- smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_ON;
+ smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
spapr_caps_add_properties(smc, &error_abort);
smc->irq = &spapr_irq_dual;
smc->dr_phb_enabled = true;
@@ -4604,7 +4619,8 @@
spapr_machine_5_0_class_options(mc);
compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
- smc->default_caps.caps[SPAPR_CAP_FWNMI_MCE] = SPAPR_CAP_OFF;
+ smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF;
+ smc->rma_limit = 16 * GiB;
mc->nvdimm_supported = false;
}
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 8b27d3a..679ae79 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -509,17 +509,14 @@
}
}
-static void cap_fwnmi_mce_apply(SpaprMachineState *spapr, uint8_t val,
+static void cap_fwnmi_apply(SpaprMachineState *spapr, uint8_t val,
Error **errp)
{
if (!val) {
return; /* Disabled by default */
}
- if (tcg_enabled()) {
- warn_report("Firmware Assisted Non-Maskable Interrupts(FWNMI) not "
- "supported in TCG");
- } else if (kvm_enabled()) {
+ if (kvm_enabled()) {
if (kvmppc_set_fwnmi() < 0) {
error_setg(errp, "Firmware Assisted Non-Maskable Interrupts(FWNMI) "
"not supported by KVM");
@@ -626,14 +623,14 @@
.type = "bool",
.apply = cap_ccf_assist_apply,
},
- [SPAPR_CAP_FWNMI_MCE] = {
- .name = "fwnmi-mce",
- .description = "Handle fwnmi machine check exceptions",
- .index = SPAPR_CAP_FWNMI_MCE,
+ [SPAPR_CAP_FWNMI] = {
+ .name = "fwnmi",
+ .description = "Implements PAPR FWNMI option",
+ .index = SPAPR_CAP_FWNMI,
.get = spapr_cap_get_bool,
.set = spapr_cap_set_bool,
.type = "bool",
- .apply = cap_fwnmi_mce_apply,
+ .apply = cap_fwnmi_apply,
},
};
@@ -774,7 +771,7 @@
SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV);
SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER);
SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
-SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI_MCE);
+SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI);
void spapr_caps_init(SpaprMachineState *spapr)
{
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index d09125d..ac1c109 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -50,22 +50,14 @@
* the settings below ensure proper operations with TCG in absence of
* a real hypervisor.
*
- * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
- * real mode accesses, which thankfully defaults to 0 and isn't
- * accessible in guest mode.
- *
* Disable Power-saving mode Exit Cause exceptions for the CPU, so
* we don't get spurious wakups before an RTAS start-cpu call.
* For the same reason, set PSSCR_EC.
*/
- lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
+ lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
lpcr |= LPCR_LPES0 | LPCR_LPES1;
env->spr[SPR_PSSCR] |= PSSCR_EC;
- /* Set RMLS to the max (ie, 16G) */
- lpcr &= ~LPCR_RMLS;
- lpcr |= 1ull << LPCR_RMLS_SHIFT;
-
ppc_store_lpcr(cpu, lpcr);
/* Set a full AMOR so guest can use the AMR as it sees fit */
@@ -84,13 +76,17 @@
spapr_irq_cpu_intc_reset(spapr, cpu);
}
-void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
+void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
+ target_ulong r1, target_ulong r3,
+ target_ulong r4)
{
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
env->nip = nip;
+ env->gpr[1] = r1;
env->gpr[3] = r3;
+ env->gpr[4] = r4;
kvmppc_set_reg_ppc_online(cpu, 1);
CPU(cpu)->halted = 0;
/* Enable Power-saving mode Exit Cause exceptions */
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index e373d34..47e6bb1 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -583,7 +583,8 @@
SpaprDrc *drc = SPAPR_DR_CONNECTOR(obj);
SpaprDrcClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
- object_property_add_uint32_ptr(obj, "id", &drc->id, NULL);
+ object_property_add_uint32_ptr(obj, "id", &drc->id, OBJ_PROP_FLAG_READ,
+ NULL);
object_property_add(obj, "index", "uint32", prop_get_index,
NULL, NULL, NULL, NULL);
object_property_add(obj, "fdt", "struct", prop_get_fdt,
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index 8b32b7e..323fcef 100644
--- a/hw/ppc/spapr_events.c
+++ b/hw/ppc/spapr_events.c
@@ -786,28 +786,12 @@
{
SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
CPUState *cs = CPU(cpu);
- uint64_t rtas_addr;
CPUPPCState *env = &cpu->env;
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- target_ulong msr = 0;
+ uint64_t rtas_addr;
struct rtas_error_log log;
struct mc_extended_log *ext_elog;
uint32_t summary;
- /*
- * Properly set bits in MSR before we invoke the handler.
- * SRR0/1, DAR and DSISR are properly set by KVM
- */
- if (!(*pcc->interrupts_big_endian)(cpu)) {
- msr |= (1ULL << MSR_LE);
- }
-
- if (env->msr & (1ULL << MSR_SF)) {
- msr |= (1ULL << MSR_SF);
- }
-
- msr |= (1ULL << MSR_ME);
-
ext_elog = g_malloc0(sizeof(*ext_elog));
summary = spapr_mce_get_elog_type(cpu, recovered, ext_elog);
@@ -823,8 +807,7 @@
/* get rtas addr from fdt */
rtas_addr = spapr_get_rtas_addr();
if (!rtas_addr) {
- /* Unable to fetch rtas_addr. Hence reset the guest */
- ppc_cpu_do_system_reset(cs);
+ qemu_system_guest_panicked(NULL);
g_free(ext_elog);
return;
}
@@ -836,12 +819,11 @@
cpu_physical_memory_write(rtas_addr + RTAS_ERROR_LOG_OFFSET +
sizeof(env->gpr[3]) + sizeof(log), ext_elog,
sizeof(*ext_elog));
+ g_free(ext_elog);
env->gpr[3] = rtas_addr + RTAS_ERROR_LOG_OFFSET;
- env->msr = msr;
- env->nip = spapr->guest_machine_check_addr;
- g_free(ext_elog);
+ ppc_cpu_do_fwnmi_machine_check(cs, spapr->fwnmi_machine_check_addr);
}
void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered)
@@ -851,7 +833,7 @@
int ret;
Error *local_err = NULL;
- if (spapr->guest_machine_check_addr == -1) {
+ if (spapr->fwnmi_machine_check_addr == -1) {
/*
* This implies that we have hit a machine check either when the
* guest has not registered FWNMI (i.e., "ibm,nmi-register" not
@@ -863,19 +845,19 @@
return;
}
- while (spapr->mc_status != -1) {
+ while (spapr->fwnmi_machine_check_interlock != -1) {
/*
* Check whether the same CPU got machine check error
* while still handling the mc error (i.e., before
* that CPU called "ibm,nmi-interlock")
*/
- if (spapr->mc_status == cpu->vcpu_id) {
+ if (spapr->fwnmi_machine_check_interlock == cpu->vcpu_id) {
qemu_system_guest_panicked(NULL);
return;
}
- qemu_cond_wait_iothread(&spapr->mc_delivery_cond);
+ qemu_cond_wait_iothread(&spapr->fwnmi_machine_check_interlock_cond);
/* Meanwhile if the system is reset, then just return */
- if (spapr->guest_machine_check_addr == -1) {
+ if (spapr->fwnmi_machine_check_addr == -1) {
return;
}
}
@@ -891,7 +873,7 @@
warn_report("Received a fwnmi while migration was in progress");
}
- spapr->mc_status = cpu->vcpu_id;
+ spapr->fwnmi_machine_check_interlock = cpu->vcpu_id;
spapr_mce_dispatch_elog(cpu, recovered);
}
@@ -983,6 +965,19 @@
}
}
+void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr)
+{
+ SpaprEventLogEntry *entry = NULL, *next_entry;
+
+ QTAILQ_FOREACH_SAFE(entry, &spapr->pending_events, next, next_entry) {
+ if (spapr_event_log_entry_type(entry) == RTAS_LOG_TYPE_HOTPLUG) {
+ QTAILQ_REMOVE(&spapr->pending_events, entry, next);
+ g_free(entry->extended_log);
+ g_free(entry);
+ }
+ }
+}
+
void spapr_events_init(SpaprMachineState *spapr)
{
int epow_irq = SPAPR_IRQ_EPOW;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 934eb12..40c86e9 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1458,7 +1458,7 @@
spapr_free_hpt(spapr);
} else if (!(patbe_new & PATE1_GR)) {
/* RADIX->HASH || NOTHING->HASH : Allocate HPT */
- spapr_setup_hpt_and_vrma(spapr);
+ spapr_setup_hpt(spapr);
}
return;
}
@@ -1640,7 +1640,7 @@
return best_compat;
}
-static bool spapr_transient_dev_before_cas(void)
+static void spapr_handle_transient_dev_before_cas(SpaprMachineState *spapr)
{
Object *drc_container;
ObjectProperty *prop;
@@ -1658,10 +1658,11 @@
prop->name, NULL));
if (spapr_drc_transient(drc)) {
- return true;
+ spapr_drc_reset(drc);
}
}
- return false;
+
+ spapr_clear_pending_hotplug_events(spapr);
}
static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
@@ -1834,9 +1835,7 @@
spapr_irq_update_active_intc(spapr);
- if (spapr_transient_dev_before_cas()) {
- spapr->cas_reboot = true;
- }
+ spapr_handle_transient_dev_before_cas(spapr);
if (!spapr->cas_reboot) {
void *fdt;
@@ -1846,7 +1845,7 @@
* (because the guest isn't going to use radix) then set it up here. */
if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
/* legacy hash or new hash: */
- spapr_setup_hpt_and_vrma(spapr);
+ spapr_setup_hpt(spapr);
}
if (fdt_bufsize < sizeof(hdr)) {
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
index 74eeb8b..25be808 100644
--- a/hw/ppc/spapr_nvdimm.c
+++ b/hw/ppc/spapr_nvdimm.c
@@ -35,6 +35,7 @@
{
char *uuidstr = NULL;
QemuUUID uuid;
+ int ret;
if (size % SPAPR_MINIMUM_SCM_BLOCK_SIZE) {
error_setg(errp, "NVDIMM memory size excluding the label area"
@@ -43,8 +44,10 @@
return;
}
- uuidstr = object_property_get_str(OBJECT(nvdimm), NVDIMM_UUID_PROP, NULL);
- qemu_uuid_parse(uuidstr, &uuid);
+ uuidstr = object_property_get_str(OBJECT(nvdimm), NVDIMM_UUID_PROP,
+ &error_abort);
+ ret = qemu_uuid_parse(uuidstr, &uuid);
+ g_assert(!ret);
g_free(uuidstr);
if (qemu_uuid_is_null(&uuid)) {
diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_ovec.c
index 0ff6d1a..dd003f1 100644
--- a/hw/ppc/spapr_ovec.c
+++ b/hw/ppc/spapr_ovec.c
@@ -200,8 +200,8 @@
return ov;
}
-int spapr_ovec_populate_dt(void *fdt, int fdt_offset,
- SpaprOptionVector *ov, const char *name)
+int spapr_dt_ovec(void *fdt, int fdt_offset,
+ SpaprOptionVector *ov, const char *name)
{
uint8_t vec[OV_MAXBYTES + 1];
uint16_t vec_len;
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 656fdd2..9fb8c86 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -190,7 +190,7 @@
*/
newcpu->env.tb_env->tb_offset = callcpu->env.tb_env->tb_offset;
- spapr_cpu_set_entry_state(newcpu, start, r3);
+ spapr_cpu_set_entry_state(newcpu, start, 0, r3, 0);
qemu_cpu_kick(CPU(newcpu));
@@ -414,8 +414,9 @@
uint32_t nret, target_ulong rets)
{
hwaddr rtas_addr;
+ target_ulong sreset_addr, mce_addr;
- if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_OFF) {
+ if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) {
rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED);
return;
}
@@ -426,7 +427,19 @@
return;
}
- spapr->guest_machine_check_addr = rtas_ld(args, 1);
+ sreset_addr = rtas_ld(args, 0);
+ mce_addr = rtas_ld(args, 1);
+
+ /* PAPR requires these are in the first 32M of memory and within RMA */
+ if (sreset_addr >= 32 * MiB || sreset_addr >= spapr->rma_size ||
+ mce_addr >= 32 * MiB || mce_addr >= spapr->rma_size) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ spapr->fwnmi_system_reset_addr = sreset_addr;
+ spapr->fwnmi_machine_check_addr = mce_addr;
+
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}
@@ -436,29 +449,39 @@
target_ulong args,
uint32_t nret, target_ulong rets)
{
- if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI_MCE) == SPAPR_CAP_OFF) {
+ if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) {
rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED);
return;
}
- if (spapr->guest_machine_check_addr == -1) {
+ if (spapr->fwnmi_machine_check_addr == -1) {
/* NMI register not called */
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
- if (spapr->mc_status != cpu->vcpu_id) {
- /* The vCPU that hit the NMI should invoke "ibm,nmi-interlock" */
- rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ if (spapr->fwnmi_machine_check_interlock != cpu->vcpu_id) {
+ /*
+ * The vCPU that hit the NMI should invoke "ibm,nmi-interlock"
+ * This should be PARAM_ERROR, but Linux calls "ibm,nmi-interlock"
+ * for system reset interrupts, despite them not being interlocked.
+ * PowerVM silently ignores this and returns success here. Returning
+ * failure causes Linux to print the error "FWNMI: nmi-interlock
+ * failed: -3", although no other apparent ill effects, this is a
+ * regression for the user when enabling FWNMI. So for now, match
+ * PowerVM. When most Linux clients are fixed, this could be
+ * changed.
+ */
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
return;
}
/*
* vCPU issuing "ibm,nmi-interlock" is done with NMI handling,
- * hence unset mc_status.
+ * hence unset fwnmi_machine_check_interlock.
*/
- spapr->mc_status = -1;
- qemu_cond_signal(&spapr->mc_delivery_cond);
+ spapr->fwnmi_machine_check_interlock = -1;
+ qemu_cond_signal(&spapr->fwnmi_machine_check_interlock_cond);
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
migrate_del_blocker(spapr->fwnmi_migration_blocker);
}
diff --git a/hw/rdma/vmw/pvrdma_qp_ops.c b/hw/rdma/vmw/pvrdma_qp_ops.c
index bd6db85..8050287 100644
--- a/hw/rdma/vmw/pvrdma_qp_ops.c
+++ b/hw/rdma/vmw/pvrdma_qp_ops.c
@@ -34,13 +34,13 @@
/* Send Queue WQE */
typedef struct PvrdmaSqWqe {
struct pvrdma_sq_wqe_hdr hdr;
- struct pvrdma_sge sge[0];
+ struct pvrdma_sge sge[];
} PvrdmaSqWqe;
/* Recv Queue WQE */
typedef struct PvrdmaRqWqe {
struct pvrdma_rq_wqe_hdr hdr;
- struct pvrdma_sge sge[0];
+ struct pvrdma_sge sge[];
} PvrdmaRqWqe;
/*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index a254cad..646553a 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -145,8 +145,8 @@
&error_abort);
/* Mask ROM */
- memory_region_init_rom(&s->mask_rom, NULL, "riscv.sifive.e.mrom",
- memmap[SIFIVE_E_MROM].size, &error_fatal);
+ memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
+ memmap[SIFIVE_E_MROM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
memmap[SIFIVE_E_MROM].base, &s->mask_rom);
@@ -208,9 +208,8 @@
memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
/* Flash memory */
- memory_region_init_ram(&s->xip_mem, NULL, "riscv.sifive.e.xip",
- memmap[SIFIVE_E_XIP].size, &error_fatal);
- memory_region_set_readonly(&s->xip_mem, true);
+ memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
+ memmap[SIFIVE_E_XIP].size, &error_fatal);
memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
&s->xip_mem);
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4409ea1..56351c4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -501,7 +501,7 @@
&error_abort);
/* boot rom */
- memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
+ memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
memmap[SIFIVE_U_MROM].size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
mask_rom);
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
index 50cf95b..64f928f 100644
--- a/hw/s390x/virtio-ccw.c
+++ b/hw/s390x/virtio-ccw.c
@@ -193,7 +193,7 @@
typedef struct VirtioRevInfo {
uint16_t revision;
uint16_t length;
- uint8_t data[0];
+ uint8_t data[];
} QEMU_PACKED VirtioRevInfo;
/* Specify where the virtqueues for the subchannel are in guest memory. */
diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c
index 7d584e7..923488b 100644
--- a/hw/scsi/spapr_vscsi.c
+++ b/hw/scsi/spapr_vscsi.c
@@ -55,6 +55,8 @@
#define VSCSI_MAX_SECTORS 4096
#define VSCSI_REQ_LIMIT 24
+/* Maximum size of a IU payload */
+#define SRP_MAX_IU_DATA_LEN (SRP_MAX_IU_LEN - sizeof(union srp_iu))
#define SRP_RSP_SENSE_DATA_LEN 18
#define SRP_REPORT_LUNS_WLUN 0xc10100000000000ULL
@@ -66,7 +68,7 @@
typedef struct vscsi_req {
vscsi_crq crq;
- union viosrp_iu iu;
+ uint8_t viosrp_iu_buf[SRP_MAX_IU_LEN];
/* SCSI request tracking */
SCSIRequest *sreq;
@@ -97,6 +99,11 @@
vscsi_req reqs[VSCSI_REQ_LIMIT];
} VSCSIState;
+static union viosrp_iu *req_iu(vscsi_req *req)
+{
+ return (union viosrp_iu *)req->viosrp_iu_buf;
+}
+
static struct vscsi_req *vscsi_get_req(VSCSIState *s)
{
vscsi_req *req;
@@ -121,7 +128,7 @@
for (i = 0; i < VSCSI_REQ_LIMIT; i++) {
req = &s->reqs[i];
- if (req->iu.srp.cmd.tag == srp_tag) {
+ if (req_iu(req)->srp.cmd.tag == srp_tag) {
return req;
}
}
@@ -176,9 +183,11 @@
{
long rc, rc1;
+ assert(length <= SRP_MAX_IU_LEN);
+
/* First copy the SRP */
rc = spapr_vio_dma_write(&s->vdev, req->crq.s.IU_data_ptr,
- &req->iu, length);
+ &req->viosrp_iu_buf, length);
if (rc) {
fprintf(stderr, "vscsi_send_iu: DMA write failure !\n");
}
@@ -188,7 +197,7 @@
req->crq.s.reserved = 0x00;
req->crq.s.timeout = cpu_to_be16(0x0000);
req->crq.s.IU_length = cpu_to_be16(length);
- req->crq.s.IU_data_ptr = req->iu.srp.rsp.tag; /* right byte order */
+ req->crq.s.IU_data_ptr = req_iu(req)->srp.rsp.tag; /* right byte order */
if (rc == 0) {
req->crq.s.status = VIOSRP_OK;
@@ -224,7 +233,7 @@
static int vscsi_send_rsp(VSCSIState *s, vscsi_req *req,
uint8_t status, int32_t res_in, int32_t res_out)
{
- union viosrp_iu *iu = &req->iu;
+ union viosrp_iu *iu = req_iu(req);
uint64_t tag = iu->srp.rsp.tag;
int total_len = sizeof(iu->srp.rsp);
uint8_t sol_not = iu->srp.cmd.sol_not;
@@ -261,10 +270,12 @@
if (status) {
iu->srp.rsp.sol_not = (sol_not & 0x04) >> 2;
if (req->senselen) {
- req->iu.srp.rsp.flags |= SRP_RSP_FLAG_SNSVALID;
- req->iu.srp.rsp.sense_data_len = cpu_to_be32(req->senselen);
- memcpy(req->iu.srp.rsp.data, req->sense, req->senselen);
- total_len += req->senselen;
+ int sense_data_len = MIN(req->senselen, SRP_MAX_IU_DATA_LEN);
+
+ iu->srp.rsp.flags |= SRP_RSP_FLAG_SNSVALID;
+ iu->srp.rsp.sense_data_len = cpu_to_be32(sense_data_len);
+ memcpy(iu->srp.rsp.data, req->sense, sense_data_len);
+ total_len += sense_data_len;
}
} else {
iu->srp.rsp.sol_not = (sol_not & 0x02) >> 1;
@@ -285,7 +296,7 @@
unsigned n, unsigned buf_offset,
struct srp_direct_buf *ret)
{
- struct srp_cmd *cmd = &req->iu.srp.cmd;
+ struct srp_cmd *cmd = &req_iu(req)->srp.cmd;
switch (req->dma_fmt) {
case SRP_NO_DATA_DESC: {
@@ -473,7 +484,7 @@
static int vscsi_preprocess_desc(vscsi_req *req)
{
- struct srp_cmd *cmd = &req->iu.srp.cmd;
+ struct srp_cmd *cmd = &req_iu(req)->srp.cmd;
req->cdb_offset = cmd->add_cdb_len & ~3;
@@ -597,7 +608,7 @@
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_BUFFER(crq.raw, vscsi_req),
- VMSTATE_BUFFER(iu.srp.reserved, vscsi_req),
+ VMSTATE_BUFFER(viosrp_iu_buf, vscsi_req),
VMSTATE_UINT32(qtag, vscsi_req),
VMSTATE_BOOL(active, vscsi_req),
VMSTATE_UINT32(data_len, vscsi_req),
@@ -655,7 +666,7 @@
static void vscsi_process_login(VSCSIState *s, vscsi_req *req)
{
- union viosrp_iu *iu = &req->iu;
+ union viosrp_iu *iu = req_iu(req);
struct srp_login_rsp *rsp = &iu->srp.login_rsp;
uint64_t tag = iu->srp.rsp.tag;
@@ -671,8 +682,8 @@
*/
rsp->req_lim_delta = cpu_to_be32(VSCSI_REQ_LIMIT-2);
rsp->tag = tag;
- rsp->max_it_iu_len = cpu_to_be32(sizeof(union srp_iu));
- rsp->max_ti_iu_len = cpu_to_be32(sizeof(union srp_iu));
+ rsp->max_it_iu_len = cpu_to_be32(SRP_MAX_IU_LEN);
+ rsp->max_ti_iu_len = cpu_to_be32(SRP_MAX_IU_LEN);
/* direct and indirect */
rsp->buf_fmt = cpu_to_be16(SRP_BUF_FORMAT_DIRECT | SRP_BUF_FORMAT_INDIRECT);
@@ -681,7 +692,7 @@
static void vscsi_inquiry_no_target(VSCSIState *s, vscsi_req *req)
{
- uint8_t *cdb = req->iu.srp.cmd.cdb;
+ uint8_t *cdb = req_iu(req)->srp.cmd.cdb;
uint8_t resp_data[36];
int rc, len, alen;
@@ -770,7 +781,7 @@
static int vscsi_queue_cmd(VSCSIState *s, vscsi_req *req)
{
- union srp_iu *srp = &req->iu.srp;
+ union srp_iu *srp = &req_iu(req)->srp;
SCSIDevice *sdev;
int n, lun;
@@ -821,17 +832,16 @@
static int vscsi_process_tsk_mgmt(VSCSIState *s, vscsi_req *req)
{
- union viosrp_iu *iu = &req->iu;
+ union viosrp_iu *iu = req_iu(req);
vscsi_req *tmpreq;
int i, lun = 0, resp = SRP_TSK_MGMT_COMPLETE;
SCSIDevice *d;
uint64_t tag = iu->srp.rsp.tag;
uint8_t sol_not = iu->srp.cmd.sol_not;
- fprintf(stderr, "vscsi_process_tsk_mgmt %02x\n",
- iu->srp.tsk_mgmt.tsk_mgmt_func);
-
- d = vscsi_device_find(&s->bus, be64_to_cpu(req->iu.srp.tsk_mgmt.lun), &lun);
+ trace_spapr_vscsi_process_tsk_mgmt(iu->srp.tsk_mgmt.tsk_mgmt_func);
+ d = vscsi_device_find(&s->bus,
+ be64_to_cpu(req_iu(req)->srp.tsk_mgmt.lun), &lun);
if (!d) {
resp = SRP_TSK_MGMT_FIELDS_INVALID;
} else {
@@ -842,7 +852,7 @@
break;
}
- tmpreq = vscsi_find_req(s, req->iu.srp.tsk_mgmt.task_tag);
+ tmpreq = vscsi_find_req(s, req_iu(req)->srp.tsk_mgmt.task_tag);
if (tmpreq && tmpreq->sreq) {
assert(tmpreq->sreq->hba_private);
scsi_req_cancel(tmpreq->sreq);
@@ -867,7 +877,8 @@
for (i = 0; i < VSCSI_REQ_LIMIT; i++) {
tmpreq = &s->reqs[i];
- if (tmpreq->iu.srp.cmd.lun != req->iu.srp.tsk_mgmt.lun) {
+ if (req_iu(tmpreq)->srp.cmd.lun
+ != req_iu(req)->srp.tsk_mgmt.lun) {
continue;
}
if (!tmpreq->active || !tmpreq->sreq) {
@@ -889,6 +900,7 @@
}
/* Compose the response here as */
+ QEMU_BUILD_BUG_ON(SRP_MAX_IU_DATA_LEN < 4);
memset(iu, 0, sizeof(struct srp_rsp) + 4);
iu->srp.rsp.opcode = SRP_RSP;
iu->srp.rsp.req_lim_delta = cpu_to_be32(1);
@@ -911,7 +923,7 @@
static int vscsi_handle_srp_req(VSCSIState *s, vscsi_req *req)
{
- union srp_iu *srp = &req->iu.srp;
+ union srp_iu *srp = &req_iu(req)->srp;
int done = 1;
uint8_t opcode = srp->rsp.opcode;
@@ -948,7 +960,7 @@
struct mad_adapter_info_data info;
int rc;
- sinfo = &req->iu.mad.adapter_info;
+ sinfo = &req_iu(req)->mad.adapter_info;
#if 0 /* What for ? */
rc = spapr_vio_dma_read(&s->vdev, be64_to_cpu(sinfo->buffer),
@@ -984,7 +996,7 @@
uint64_t buffer;
int rc;
- vcap = &req->iu.mad.capabilities;
+ vcap = &req_iu(req)->mad.capabilities;
req_len = len = be16_to_cpu(vcap->common.length);
buffer = be64_to_cpu(vcap->buffer);
if (len > sizeof(cap)) {
@@ -1029,7 +1041,7 @@
static int vscsi_handle_mad_req(VSCSIState *s, vscsi_req *req)
{
- union mad_iu *mad = &req->iu.mad;
+ union mad_iu *mad = &req_iu(req)->mad;
bool request_handled = false;
uint64_t retlen = 0;
@@ -1088,7 +1100,7 @@
* in our 256 bytes IUs. If not we'll have to increase the size
* of the structure.
*/
- if (crq->s.IU_length > sizeof(union viosrp_iu)) {
+ if (crq->s.IU_length > SRP_MAX_IU_LEN) {
fprintf(stderr, "VSCSI: SRP IU too long (%d bytes) !\n",
crq->s.IU_length);
vscsi_put_req(req);
@@ -1096,7 +1108,7 @@
}
/* XXX Handle failure differently ? */
- if (spapr_vio_dma_read(&s->vdev, crq->s.IU_data_ptr, &req->iu,
+ if (spapr_vio_dma_read(&s->vdev, crq->s.IU_data_ptr, &req->viosrp_iu_buf,
crq->s.IU_length)) {
fprintf(stderr, "vscsi_got_payload: DMA read failure !\n");
vscsi_put_req(req);
diff --git a/hw/scsi/trace-events b/hw/scsi/trace-events
index b082005..9a4a60c 100644
--- a/hw/scsi/trace-events
+++ b/hw/scsi/trace-events
@@ -227,6 +227,7 @@
spapr_vscsi_save_request(uint32_t qtag, unsigned desc, unsigned offset) "saving tag=%"PRIu32", current desc#%u, offset=0x%x"
spapr_vscsi_load_request(uint32_t qtag, unsigned desc, unsigned offset) "restoring tag=%"PRIu32", current desc#%u, offset=0x%x"
spapr_vscsi_process_login(void) "Got login, sending response !"
+spapr_vscsi_process_tsk_mgmt(uint8_t func) "tsk_mgmt_func 0x%02x"
spapr_vscsi_queue_cmd_no_drive(uint64_t lun) "Command for lun 0x%08" PRIx64 " with no drive"
spapr_vscsi_queue_cmd(uint32_t qtag, unsigned cdb, const char *cmd, int lun, int ret) "Queued command tag 0x%"PRIx32" CMD 0x%x=%s LUN %d ret: %d"
spapr_vscsi_do_crq(unsigned c0, unsigned c1) "crq: %02x %02x ..."
diff --git a/hw/scsi/viosrp.h b/hw/scsi/viosrp.h
index d8e365d..e5f9768 100644
--- a/hw/scsi/viosrp.h
+++ b/hw/scsi/viosrp.h
@@ -34,6 +34,8 @@
#ifndef PPC_VIOSRP_H
#define PPC_VIOSRP_H
+#include "hw/scsi/srp.h"
+
#define SRP_VERSION "16.a"
#define SRP_MAX_IU_LEN 256
#define SRP_MAX_LOC_LEN 32
@@ -47,7 +49,6 @@
struct srp_tsk_mgmt tsk_mgmt;
struct srp_cmd cmd;
struct srp_rsp rsp;
- uint8_t reserved[SRP_MAX_IU_LEN];
};
enum viosrp_crq_formats {
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
index 91db069..829797b 100644
--- a/hw/sd/ssi-sd.c
+++ b/hw/sd/ssi-sd.c
@@ -255,13 +255,25 @@
carddev = qdev_create(BUS(&s->sdbus), TYPE_SD_CARD);
if (dinfo) {
qdev_prop_set_drive(carddev, "drive", blk_by_legacy_dinfo(dinfo), &err);
+ if (err) {
+ goto fail;
+ }
}
+
object_property_set_bool(OBJECT(carddev), true, "spi", &err);
+ if (err) {
+ goto fail;
+ }
+
object_property_set_bool(OBJECT(carddev), true, "realized", &err);
if (err) {
- error_setg(errp, "failed to init SD card: %s", error_get_pretty(err));
- return;
+ goto fail;
}
+
+ return;
+
+fail:
+ error_propagate_prepend(errp, err, "failed to init SD card: ");
}
static void ssi_sd_reset(DeviceState *dev)
diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c
index 68b14ee..f410c08 100644
--- a/hw/sh4/shix.c
+++ b/hw/sh4/shix.c
@@ -53,8 +53,7 @@
cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
/* Allocate memory space */
- memory_region_init_ram(rom, NULL, "shix.rom", 0x4000, &error_fatal);
- memory_region_set_readonly(rom, true);
+ memory_region_init_rom(rom, NULL, "shix.rom", 0x4000, &error_fatal);
memory_region_add_subregion(sysmem, 0x00000000, rom);
memory_region_init_ram(&sdram[0], NULL, "shix.sdram1", 0x01000000,
&error_fatal);
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index 5fa58aa..8f024da 100644
--- a/hw/sparc/leon3.c
+++ b/hw/sparc/leon3.c
@@ -255,8 +255,7 @@
/* Allocate BIOS */
prom_size = 8 * MiB;
- memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
- memory_region_set_readonly(prom, true);
+ memory_region_init_rom(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
/* Load boot prom */
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 32be2a0..9d5c696 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -788,11 +788,11 @@
case FAST_READ:
case DOR:
case QOR:
+ case FAST_READ_4:
case DOR_4:
case QOR_4:
return 1;
case DIOR:
- case FAST_READ_4:
case DIOR_4:
return 2;
case QIOR:
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index 5e70ed5..464348b 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -91,3 +91,8 @@
bool
default y
depends on USB
+
+config IMX_USBPHY
+ bool
+ default y
+ depends on USB
diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index 2b10868..66835e5 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -61,3 +61,5 @@
xen-usb.o-cflags := $(LIBUSB_CFLAGS)
xen-usb.o-libs := $(LIBUSB_LIBS)
endif
+
+common-obj-$(CONFIG_IMX_USBPHY) += imx-usb-phy.o
diff --git a/hw/usb/dev-network.c b/hw/usb/dev-network.c
index 9a78ad9..6210427 100644
--- a/hw/usb/dev-network.c
+++ b/hw/usb/dev-network.c
@@ -626,7 +626,7 @@
struct rndis_response {
QTAILQ_ENTRY(rndis_response) entries;
uint32_t length;
- uint8_t buf[0];
+ uint8_t buf[];
};
typedef struct USBNetState {
diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c
index 02693a2..ef72738 100644
--- a/hw/usb/dev-smartcard-reader.c
+++ b/hw/usb/dev-smartcard-reader.c
@@ -227,7 +227,7 @@
typedef struct QEMU_PACKED CCID_DataBlock {
CCID_BULK_IN b;
uint8_t bChainParameter;
- uint8_t abData[0];
+ uint8_t abData[];
} CCID_DataBlock;
/* 6.1.4 PC_to_RDR_XfrBlock */
@@ -235,7 +235,7 @@
CCID_Header hdr;
uint8_t bBWI; /* Block Waiting Timeout */
uint16_t wLevelParameter; /* XXX currently unused */
- uint8_t abData[0];
+ uint8_t abData[];
} CCID_XferBlock;
typedef struct QEMU_PACKED CCID_IccPowerOn {
diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c
new file mode 100644
index 0000000..e705a03
--- /dev/null
+++ b/hw/usb/imx-usb-phy.c
@@ -0,0 +1,225 @@
+/*
+ * i.MX USB PHY
+ *
+ * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * We need to implement basic reset control in the PHY control register.
+ * For everything else, it is sufficient to set whatever is written.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/usb/imx-usb-phy.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+
+static const VMStateDescription vmstate_imx_usbphy = {
+ .name = TYPE_IMX_USBPHY,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(usbphy, IMXUSBPHYState, USBPHY_MAX),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static void imx_usbphy_softreset(IMXUSBPHYState *s)
+{
+ s->usbphy[USBPHY_PWD] = 0x001e1c00;
+ s->usbphy[USBPHY_TX] = 0x10060607;
+ s->usbphy[USBPHY_RX] = 0x00000000;
+ s->usbphy[USBPHY_CTRL] = 0xc0200000;
+}
+
+static void imx_usbphy_reset(DeviceState *dev)
+{
+ IMXUSBPHYState *s = IMX_USBPHY(dev);
+
+ s->usbphy[USBPHY_STATUS] = 0x00000000;
+ s->usbphy[USBPHY_DEBUG] = 0x7f180000;
+ s->usbphy[USBPHY_DEBUG0_STATUS] = 0x00000000;
+ s->usbphy[USBPHY_DEBUG1] = 0x00001000;
+ s->usbphy[USBPHY_VERSION] = 0x04020000;
+
+ imx_usbphy_softreset(s);
+}
+
+static uint64_t imx_usbphy_read(void *opaque, hwaddr offset, unsigned size)
+{
+ IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
+ uint32_t index = offset >> 2;
+ uint32_t value;
+
+ switch (index) {
+ case USBPHY_PWD_SET:
+ case USBPHY_TX_SET:
+ case USBPHY_RX_SET:
+ case USBPHY_CTRL_SET:
+ case USBPHY_DEBUG_SET:
+ case USBPHY_DEBUG1_SET:
+ /*
+ * All REG_NAME_SET register access are in fact targeting the
+ * REG_NAME register.
+ */
+ value = s->usbphy[index - 1];
+ break;
+ case USBPHY_PWD_CLR:
+ case USBPHY_TX_CLR:
+ case USBPHY_RX_CLR:
+ case USBPHY_CTRL_CLR:
+ case USBPHY_DEBUG_CLR:
+ case USBPHY_DEBUG1_CLR:
+ /*
+ * All REG_NAME_CLR register access are in fact targeting the
+ * REG_NAME register.
+ */
+ value = s->usbphy[index - 2];
+ break;
+ case USBPHY_PWD_TOG:
+ case USBPHY_TX_TOG:
+ case USBPHY_RX_TOG:
+ case USBPHY_CTRL_TOG:
+ case USBPHY_DEBUG_TOG:
+ case USBPHY_DEBUG1_TOG:
+ /*
+ * All REG_NAME_TOG register access are in fact targeting the
+ * REG_NAME register.
+ */
+ value = s->usbphy[index - 3];
+ break;
+ default:
+ value = s->usbphy[index];
+ break;
+ }
+ return (uint64_t)value;
+}
+
+static void imx_usbphy_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
+ uint32_t index = offset >> 2;
+
+ switch (index) {
+ case USBPHY_CTRL:
+ s->usbphy[index] = value;
+ if (value & USBPHY_CTRL_SFTRST) {
+ imx_usbphy_softreset(s);
+ }
+ break;
+ case USBPHY_PWD:
+ case USBPHY_TX:
+ case USBPHY_RX:
+ case USBPHY_STATUS:
+ case USBPHY_DEBUG:
+ case USBPHY_DEBUG1:
+ s->usbphy[index] = value;
+ break;
+ case USBPHY_CTRL_SET:
+ s->usbphy[index - 1] |= value;
+ if (value & USBPHY_CTRL_SFTRST) {
+ imx_usbphy_softreset(s);
+ }
+ break;
+ case USBPHY_PWD_SET:
+ case USBPHY_TX_SET:
+ case USBPHY_RX_SET:
+ case USBPHY_DEBUG_SET:
+ case USBPHY_DEBUG1_SET:
+ /*
+ * All REG_NAME_SET register access are in fact targeting the
+ * REG_NAME register. So we change the value of the REG_NAME
+ * register, setting bits passed in the value.
+ */
+ s->usbphy[index - 1] |= value;
+ break;
+ case USBPHY_PWD_CLR:
+ case USBPHY_TX_CLR:
+ case USBPHY_RX_CLR:
+ case USBPHY_CTRL_CLR:
+ case USBPHY_DEBUG_CLR:
+ case USBPHY_DEBUG1_CLR:
+ /*
+ * All REG_NAME_CLR register access are in fact targeting the
+ * REG_NAME register. So we change the value of the REG_NAME
+ * register, unsetting bits passed in the value.
+ */
+ s->usbphy[index - 2] &= ~value;
+ break;
+ case USBPHY_CTRL_TOG:
+ s->usbphy[index - 3] ^= value;
+ if ((value & USBPHY_CTRL_SFTRST) &&
+ (s->usbphy[index - 3] & USBPHY_CTRL_SFTRST)) {
+ imx_usbphy_softreset(s);
+ }
+ break;
+ case USBPHY_PWD_TOG:
+ case USBPHY_TX_TOG:
+ case USBPHY_RX_TOG:
+ case USBPHY_DEBUG_TOG:
+ case USBPHY_DEBUG1_TOG:
+ /*
+ * All REG_NAME_TOG register access are in fact targeting the
+ * REG_NAME register. So we change the value of the REG_NAME
+ * register, toggling bits passed in the value.
+ */
+ s->usbphy[index - 3] ^= value;
+ break;
+ default:
+ /* Other registers are read-only */
+ break;
+ }
+}
+
+static const struct MemoryRegionOps imx_usbphy_ops = {
+ .read = imx_usbphy_read,
+ .write = imx_usbphy_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ /*
+ * Our device would not work correctly if the guest was doing
+ * unaligned access. This might not be a limitation on the real
+ * device but in practice there is no reason for a guest to access
+ * this device unaligned.
+ */
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void imx_usbphy_realize(DeviceState *dev, Error **errp)
+{
+ IMXUSBPHYState *s = IMX_USBPHY(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &imx_usbphy_ops, s,
+ "imx-usbphy", 0x1000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void imx_usbphy_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = imx_usbphy_reset;
+ dc->vmsd = &vmstate_imx_usbphy;
+ dc->desc = "i.MX USB PHY Module";
+ dc->realize = imx_usbphy_realize;
+}
+
+static const TypeInfo imx_usbphy_info = {
+ .name = TYPE_IMX_USBPHY,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(IMXUSBPHYState),
+ .class_init = imx_usbphy_class_init,
+};
+
+static void imx_usbphy_register_types(void)
+{
+ type_register_static(&imx_usbphy_info);
+}
+
+type_init(imx_usbphy_register_types)
diff --git a/hw/usb/quirks.c b/hw/usb/quirks.c
index 38a9c56..23ea7a2 100644
--- a/hw/usb/quirks.c
+++ b/hw/usb/quirks.c
@@ -22,10 +22,10 @@
uint8_t interface_protocol) {
int i;
- for (i = 0; ids[i].vendor_id != -1; i++) {
+ for (i = 0; ids[i].terminating_entry == 0; i++) {
if (ids[i].vendor_id == vendor_id &&
ids[i].product_id == product_id &&
- (ids[i].interface_class == -1 ||
+ (ids[i].interface_protocol_used == 0 ||
(ids[i].interface_class == interface_class &&
ids[i].interface_subclass == interface_subclass &&
ids[i].interface_protocol == interface_protocol))) {
diff --git a/hw/usb/quirks.h b/hw/usb/quirks.h
index 89480be..50ef2f9 100644
--- a/hw/usb/quirks.h
+++ b/hw/usb/quirks.h
@@ -21,19 +21,23 @@
#include "quirks-pl2303-ids.h"
struct usb_device_id {
- int vendor_id;
- int product_id;
- int interface_class;
- int interface_subclass;
- int interface_protocol;
+ uint16_t vendor_id;
+ uint16_t product_id;
+ uint8_t interface_class;
+ uint8_t interface_subclass;
+ uint8_t interface_protocol;
+ uint8_t interface_protocol_used:1,
+ terminating_entry:1,
+ reserved:6;
};
#define USB_DEVICE(vendor, product) \
- .vendor_id = vendor, .product_id = product, .interface_class = -1,
+ .vendor_id = vendor, .product_id = product, .interface_protocol_used = 0,
#define USB_DEVICE_AND_INTERFACE_INFO(vend, prod, iclass, isubclass, iproto) \
.vendor_id = vend, .product_id = prod, .interface_class = iclass, \
- .interface_subclass = isubclass, .interface_protocol = iproto
+ .interface_subclass = isubclass, .interface_protocol = iproto, \
+ .interface_protocol_used = 1
static const struct usb_device_id usbredir_raw_serial_ids[] = {
/*
@@ -206,7 +210,7 @@
{ USB_DEVICE(ADLINK_VENDOR_ID, ADLINK_ND6530_PRODUCT_ID) },
{ USB_DEVICE(SMART_VENDOR_ID, SMART_PRODUCT_ID) },
- { USB_DEVICE(-1, -1) } /* Terminating Entry */
+ { .terminating_entry = 1 } /* Terminating Entry */
};
static const struct usb_device_id usbredir_ftdi_serial_ids[] = {
@@ -906,7 +910,7 @@
{ USB_DEVICE(FTDI_VID, FTDI_DISTORTEC_JTAG_LOCK_PICK_PID) },
{ USB_DEVICE(FTDI_VID, FTDI_LUMEL_PD12_PID) },
- { USB_DEVICE(-1, -1) } /* Terminating Entry */
+ { .terminating_entry = 1 } /* Terminating Entry */
};
#undef USB_DEVICE
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index b2d415e..b6c8ef5 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -54,7 +54,7 @@
{
uint16_t flags;
uint16_t idx;
- uint16_t ring[0];
+ uint16_t ring[];
} VRingAvail;
typedef struct VRingUsedElem
@@ -67,7 +67,7 @@
{
uint16_t flags;
uint16_t idx;
- VRingUsedElem ring[0];
+ VRingUsedElem ring[];
} VRingUsed;
typedef struct VRingMemoryRegionCaches {
diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h
index 9167bba..179775d 100644
--- a/hw/xen/xen_pt.h
+++ b/hw/xen/xen_pt.h
@@ -203,7 +203,7 @@
uint64_t mmio_base_addr;
MemoryRegion mmio;
void *phys_iomem_base;
- XenPTMSIXEntry msix_entry[0];
+ XenPTMSIXEntry msix_entry[];
} XenPTMSIX;
struct XenPCIPassthroughState {
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index 0836396..30b909e 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -68,40 +68,76 @@
void gdbserver_fork(CPUState *);
#endif
/* Get or set a register. Returns the size of the register. */
-typedef int (*gdb_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);
+typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg);
+typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);
void gdb_register_coprocessor(CPUState *cpu,
- gdb_reg_cb get_reg, gdb_reg_cb set_reg,
+ gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,
int num_regs, const char *xml, int g_pos);
-/* The GDB remote protocol transfers values in target byte order. This means
- * we can use the raw memory access routines to access the value buffer.
- * Conveniently, these also handle the case where the buffer is mis-aligned.
+/*
+ * The GDB remote protocol transfers values in target byte order. As
+ * the gdbstub may be batching up several register values we always
+ * append to the array.
*/
-static inline int gdb_get_reg8(uint8_t *mem_buf, uint8_t val)
+static inline int gdb_get_reg8(GByteArray *buf, uint8_t val)
{
- stb_p(mem_buf, val);
+ g_byte_array_append(buf, &val, 1);
return 1;
}
-static inline int gdb_get_reg16(uint8_t *mem_buf, uint16_t val)
+static inline int gdb_get_reg16(GByteArray *buf, uint16_t val)
{
- stw_p(mem_buf, val);
+ uint16_t to_word = tswap16(val);
+ g_byte_array_append(buf, (uint8_t *) &to_word, 2);
return 2;
}
-static inline int gdb_get_reg32(uint8_t *mem_buf, uint32_t val)
+static inline int gdb_get_reg32(GByteArray *buf, uint32_t val)
{
- stl_p(mem_buf, val);
+ uint32_t to_long = tswap32(val);
+ g_byte_array_append(buf, (uint8_t *) &to_long, 4);
return 4;
}
-static inline int gdb_get_reg64(uint8_t *mem_buf, uint64_t val)
+static inline int gdb_get_reg64(GByteArray *buf, uint64_t val)
{
- stq_p(mem_buf, val);
+ uint64_t to_quad = tswap64(val);
+ g_byte_array_append(buf, (uint8_t *) &to_quad, 8);
return 8;
}
+static inline int gdb_get_reg128(GByteArray *buf, uint64_t val_hi,
+ uint64_t val_lo)
+{
+ uint64_t to_quad;
+#ifdef TARGET_WORDS_BIGENDIAN
+ to_quad = tswap64(val_hi);
+ g_byte_array_append(buf, (uint8_t *) &to_quad, 8);
+ to_quad = tswap64(val_lo);
+ g_byte_array_append(buf, (uint8_t *) &to_quad, 8);
+#else
+ to_quad = tswap64(val_lo);
+ g_byte_array_append(buf, (uint8_t *) &to_quad, 8);
+ to_quad = tswap64(val_hi);
+ g_byte_array_append(buf, (uint8_t *) &to_quad, 8);
+#endif
+ return 16;
+}
+
+/**
+ * gdb_get_reg_ptr: get pointer to start of last element
+ * @len: length of element
+ *
+ * This is a helper function to extract the pointer to the last
+ * element for additional processing. Some front-ends do additional
+ * dynamic swapping of the elements based on CPU state.
+ */
+static inline uint8_t * gdb_get_reg_ptr(GByteArray *buf, int len)
+{
+ return buf->data + buf->len - len;
+}
+
#if TARGET_LONG_BITS == 64
#define gdb_get_regl(buf, val) gdb_get_reg64(buf, val)
#define ldtul_p(addr) ldq_p(addr)
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 57a3f58..c13327f 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -152,7 +152,7 @@
*/
struct AcpiRsdtDescriptorRev1 {
ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t table_offset_entry[0]; /* Array of pointers to other */
+ uint32_t table_offset_entry[]; /* Array of pointers to other */
/* ACPI tables */
} QEMU_PACKED;
typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
@@ -162,7 +162,7 @@
*/
struct AcpiXsdtDescriptorRev2 {
ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint64_t table_offset_entry[0]; /* Array of pointers to other */
+ uint64_t table_offset_entry[]; /* Array of pointers to other */
/* ACPI tables */
} QEMU_PACKED;
typedef struct AcpiXsdtDescriptorRev2 AcpiXsdtDescriptorRev2;
@@ -518,7 +518,7 @@
struct {
uint8_t device;
uint8_t function;
- } path[0];
+ } path[];
} QEMU_PACKED;
typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope;
@@ -530,7 +530,7 @@
uint8_t reserved;
uint16_t pci_segment; /* The PCI Segment associated with this unit */
uint64_t address; /* Base address of remapping hardware register-set */
- AcpiDmarDeviceScope scope[0];
+ AcpiDmarDeviceScope scope[];
} QEMU_PACKED;
typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit;
@@ -541,7 +541,7 @@
uint8_t flags;
uint8_t reserved;
uint16_t pci_segment;
- AcpiDmarDeviceScope scope[0];
+ AcpiDmarDeviceScope scope[];
} QEMU_PACKED;
typedef struct AcpiDmarRootPortATS AcpiDmarRootPortATS;
@@ -604,7 +604,7 @@
struct AcpiIortItsGroup {
ACPI_IORT_NODE_HEADER_DEF
uint32_t its_count;
- uint32_t identifiers[0];
+ uint32_t identifiers[];
} QEMU_PACKED;
typedef struct AcpiIortItsGroup AcpiIortItsGroup;
@@ -621,7 +621,7 @@
uint32_t pri_gsiv;
uint32_t gerr_gsiv;
uint32_t sync_gsiv;
- AcpiIortIdMapping id_mapping_array[0];
+ AcpiIortIdMapping id_mapping_array[];
} QEMU_PACKED;
typedef struct AcpiIortSmmu3 AcpiIortSmmu3;
@@ -630,7 +630,7 @@
AcpiIortMemoryAccess memory_properties;
uint32_t ats_attribute;
uint32_t pci_segment_number;
- AcpiIortIdMapping id_mapping_array[0];
+ AcpiIortIdMapping id_mapping_array[];
} QEMU_PACKED;
typedef struct AcpiIortRC AcpiIortRC;
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index 60eadcc..973bcb7 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -30,6 +30,8 @@
#include "hw/sd/sdhci.h"
#include "hw/ssi/imx_spi.h"
#include "hw/net/imx_fec.h"
+#include "hw/usb/chipidea.h"
+#include "hw/usb/imx-usb-phy.h"
#include "exec/memory.h"
#include "cpu.h"
@@ -44,6 +46,8 @@
#define FSL_IMX6_NUM_ESDHCS 4
#define FSL_IMX6_NUM_ECSPIS 5
#define FSL_IMX6_NUM_WDTS 2
+#define FSL_IMX6_NUM_USB_PHYS 2
+#define FSL_IMX6_NUM_USBS 4
typedef struct FslIMX6State {
/*< private >*/
@@ -62,6 +66,8 @@
SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS];
IMXSPIState spi[FSL_IMX6_NUM_ECSPIS];
IMX2WdtState wdt[FSL_IMX6_NUM_WDTS];
+ IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
+ ChipideaState usb[FSL_IMX6_NUM_USBS];
IMXFECState eth;
MemoryRegion rom;
MemoryRegion caam;
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index eda389a..1a0bab8 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -34,6 +34,8 @@
#include "hw/sd/sdhci.h"
#include "hw/ssi/imx_spi.h"
#include "hw/net/imx_fec.h"
+#include "hw/usb/chipidea.h"
+#include "hw/usb/imx-usb-phy.h"
#include "exec/memory.h"
#include "cpu.h"
@@ -54,6 +56,8 @@
FSL_IMX6UL_NUM_I2CS = 4,
FSL_IMX6UL_NUM_ECSPIS = 4,
FSL_IMX6UL_NUM_ADCS = 2,
+ FSL_IMX6UL_NUM_USB_PHYS = 2,
+ FSL_IMX6UL_NUM_USBS = 2,
};
typedef struct FslIMX6ULState {
@@ -77,6 +81,8 @@
IMXFECState eth[FSL_IMX6UL_NUM_ETHS];
SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS];
IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS];
+ IMXUSBPHYState usbphy[FSL_IMX6UL_NUM_USB_PHYS];
+ ChipideaState usb[FSL_IMX6UL_NUM_USBS];
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
@@ -145,6 +151,10 @@
FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
+ FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000,
+ FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024),
+ FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000,
+ FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024),
FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
FSL_IMX6UL_CCM_ADDR = 0x020C4000,
FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
@@ -241,10 +251,10 @@
FSL_IMX6UL_UART7_IRQ = 39,
FSL_IMX6UL_UART8_IRQ = 40,
- FSL_IMX6UL_USB1_IRQ = 42,
- FSL_IMX6UL_USB2_IRQ = 43,
+ FSL_IMX6UL_USB1_IRQ = 43,
+ FSL_IMX6UL_USB2_IRQ = 42,
FSL_IMX6UL_USB_PHY1_IRQ = 44,
- FSL_IMX6UL_USB_PHY2_IRQ = 44,
+ FSL_IMX6UL_USB_PHY2_IRQ = 45,
FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
FSL_IMX6UL_CAAM_ERR_IRQ = 47,
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index 1f37844..ca4a4b1 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -85,7 +85,7 @@
typedef struct SMMUPciBus {
PCIBus *bus;
- SMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */
+ SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */
} SMMUPciBus;
typedef struct SMMUIOTLBKey {
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 9bc42df..c96120d 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -71,7 +71,7 @@
*/
typedef struct {
int len;
- CPUArchId cpus[0];
+ CPUArchId cpus[];
} CPUArchIdList;
/**
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 73e9a86..e1d6ee0 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -195,7 +195,7 @@
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
- int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
+ int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
void (*debug_excp_handler)(CPUState *cpu);
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index a1c4afc..3870052 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -114,7 +114,8 @@
struct VTDBus {
PCIBus* bus; /* A reference to the bus to provide translation for */
- VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */
+ /* A table of VTDAddressSpace objects indexed by devfn */
+ VTDAddressSpace *dev_as[];
};
struct VTDIOTLBEntry {
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 0911096..42d64a0 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -79,10 +79,10 @@
#define SPAPR_CAP_LARGE_DECREMENTER 0x08
/* Count Cache Flush Assist HW Instruction */
#define SPAPR_CAP_CCF_ASSIST 0x09
-/* FWNMI machine check handling */
-#define SPAPR_CAP_FWNMI_MCE 0x0A
+/* Implements PAPR FWNMI option */
+#define SPAPR_CAP_FWNMI 0x0A
/* Num Caps */
-#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI_MCE + 1)
+#define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1)
/*
* Capability Values
@@ -126,6 +126,7 @@
bool pre_4_1_migration; /* don't migrate hpt-max-page-size */
bool linux_pci_probe;
bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
+ hwaddr rma_limit; /* clamp the RMA to this size */
void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
uint64_t *buid, hwaddr *pio,
@@ -156,7 +157,6 @@
SpaprPendingHpt *pending_hpt; /* in-progress resize */
hwaddr rma_size;
- int vrma_adjust;
uint32_t fdt_size;
uint32_t fdt_initial_size;
void *fdt_blob;
@@ -192,14 +192,22 @@
* occurs during the unplug process. */
QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
- /* State related to "ibm,nmi-register" and "ibm,nmi-interlock" calls */
- target_ulong guest_machine_check_addr;
- /*
- * mc_status is set to -1 if mc is not in progress, else is set to the CPU
- * handling the mc.
+ /* State related to FWNMI option */
+
+ /* System Reset and Machine Check Notification Routine addresses
+ * registered by "ibm,nmi-register" RTAS call.
*/
- int mc_status;
- QemuCond mc_delivery_cond;
+ target_ulong fwnmi_system_reset_addr;
+ target_ulong fwnmi_machine_check_addr;
+
+ /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
+ * set to -1 if a FWNMI machine check is not in progress, else is set to
+ * the CPU that was delivered the machine check, and is set back to -1
+ * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used
+ * to synchronize other CPUs.
+ */
+ int fwnmi_machine_check_interlock;
+ QemuCond fwnmi_machine_check_interlock_cond;
/*< public >*/
char *kvm_type;
@@ -736,6 +744,7 @@
#define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
+#define RTAS_SIZE 2048
#define RTAS_ERROR_LOG_MAX 2048
/* Offset from rtas-base where error log is placed */
@@ -795,7 +804,7 @@
void spapr_events_init(SpaprMachineState *sm);
void spapr_dt_events(SpaprMachineState *sm, void *fdt);
void close_htab_fd(SpaprMachineState *spapr);
-void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr);
+void spapr_setup_hpt(SpaprMachineState *spapr);
void spapr_free_hpt(SpaprMachineState *spapr);
SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
void spapr_tce_table_enable(SpaprTceTable *tcet,
@@ -824,6 +833,7 @@
void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
Error **errp);
void spapr_clear_pending_events(SpaprMachineState *spapr);
+void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
int spapr_max_server_number(SpaprMachineState *spapr);
void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
uint64_t pte0, uint64_t pte1);
diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h
index 1c4cc65..7aed8f5 100644
--- a/include/hw/ppc/spapr_cpu_core.h
+++ b/include/hw/ppc/spapr_cpu_core.h
@@ -40,7 +40,9 @@
} SpaprCpuCoreClass;
const char *spapr_get_cpu_core_type(const char *cpu_type);
-void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3);
+void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
+ target_ulong r1, target_ulong r3,
+ target_ulong r4);
typedef struct SpaprCpuState {
uint64_t vpa_addr;
diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h
index 2bed517..d4dee9e 100644
--- a/include/hw/ppc/spapr_ovec.h
+++ b/include/hw/ppc/spapr_ovec.h
@@ -72,8 +72,8 @@
void spapr_ovec_clear(SpaprOptionVector *ov, long bitnr);
bool spapr_ovec_test(SpaprOptionVector *ov, long bitnr);
SpaprOptionVector *spapr_ovec_parse_vector(target_ulong table_addr, int vector);
-int spapr_ovec_populate_dt(void *fdt, int fdt_offset,
- SpaprOptionVector *ov, const char *name);
+int spapr_dt_ovec(void *fdt, int fdt_offset,
+ SpaprOptionVector *ov, const char *name);
/* migration */
extern const VMStateDescription vmstate_spapr_ovec;
diff --git a/include/hw/s390x/event-facility.h b/include/hw/s390x/event-facility.h
index bdc32a3..700a610 100644
--- a/include/hw/s390x/event-facility.h
+++ b/include/hw/s390x/event-facility.h
@@ -122,7 +122,7 @@
typedef struct MDB {
MdbHeader header;
- MDBO mdbo[0];
+ MDBO mdbo[];
} QEMU_PACKED MDB;
typedef struct SclpMsg {
diff --git a/include/hw/s390x/sclp.h b/include/hw/s390x/sclp.h
index c54413b..cd7b243 100644
--- a/include/hw/s390x/sclp.h
+++ b/include/hw/s390x/sclp.h
@@ -132,7 +132,7 @@
uint16_t highest_cpu;
uint8_t _reserved5[124 - 122]; /* 122-123 */
uint32_t hmfai;
- struct CPUEntry entries[0];
+ struct CPUEntry entries[];
} QEMU_PACKED ReadInfo;
typedef struct ReadCpuInfo {
@@ -142,7 +142,7 @@
uint16_t nr_standby; /* 12-13 */
uint16_t offset_standby; /* 14-15 */
uint8_t reserved0[24-16]; /* 16-23 */
- struct CPUEntry entries[0];
+ struct CPUEntry entries[];
} QEMU_PACKED ReadCpuInfo;
typedef struct ReadStorageElementInfo {
@@ -151,7 +151,7 @@
uint16_t assigned;
uint16_t standby;
uint8_t _reserved0[16 - 14]; /* 14-15 */
- uint32_t entries[0];
+ uint32_t entries[];
} QEMU_PACKED ReadStorageElementInfo;
typedef struct AttachStorageElement {
@@ -159,7 +159,7 @@
uint8_t _reserved0[10 - 8]; /* 8-9 */
uint16_t assigned;
uint8_t _reserved1[16 - 12]; /* 12-15 */
- uint32_t entries[0];
+ uint32_t entries[];
} QEMU_PACKED AttachStorageElement;
typedef struct AssignStorage {
diff --git a/include/hw/usb/imx-usb-phy.h b/include/hw/usb/imx-usb-phy.h
new file mode 100644
index 0000000..07f0235
--- /dev/null
+++ b/include/hw/usb/imx-usb-phy.h
@@ -0,0 +1,53 @@
+#ifndef IMX_USB_PHY_H
+#define IMX_USB_PHY_H
+
+#include "hw/sysbus.h"
+#include "qemu/bitops.h"
+
+enum IMXUsbPhyRegisters {
+ USBPHY_PWD,
+ USBPHY_PWD_SET,
+ USBPHY_PWD_CLR,
+ USBPHY_PWD_TOG,
+ USBPHY_TX,
+ USBPHY_TX_SET,
+ USBPHY_TX_CLR,
+ USBPHY_TX_TOG,
+ USBPHY_RX,
+ USBPHY_RX_SET,
+ USBPHY_RX_CLR,
+ USBPHY_RX_TOG,
+ USBPHY_CTRL,
+ USBPHY_CTRL_SET,
+ USBPHY_CTRL_CLR,
+ USBPHY_CTRL_TOG,
+ USBPHY_STATUS,
+ USBPHY_DEBUG = 0x14,
+ USBPHY_DEBUG_SET,
+ USBPHY_DEBUG_CLR,
+ USBPHY_DEBUG_TOG,
+ USBPHY_DEBUG0_STATUS,
+ USBPHY_DEBUG1 = 0x1c,
+ USBPHY_DEBUG1_SET,
+ USBPHY_DEBUG1_CLR,
+ USBPHY_DEBUG1_TOG,
+ USBPHY_VERSION,
+ USBPHY_MAX
+};
+
+#define USBPHY_CTRL_SFTRST BIT(31)
+
+#define TYPE_IMX_USBPHY "imx.usbphy"
+#define IMX_USBPHY(obj) OBJECT_CHECK(IMXUSBPHYState, (obj), TYPE_IMX_USBPHY)
+
+typedef struct IMXUSBPHYState {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion iomem;
+
+ uint32_t usbphy[USBPHY_MAX];
+} IMXUSBPHYState;
+
+#endif /* IMX_USB_PHY_H */
diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h
index 6f67f10..e653004 100644
--- a/include/hw/virtio/virtio-iommu.h
+++ b/include/hw/virtio/virtio-iommu.h
@@ -41,7 +41,7 @@
typedef struct IOMMUPciBus {
PCIBus *bus;
- IOMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */
+ IOMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */
} IOMMUPciBus;
typedef struct VirtIOIOMMU {
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 6930170..09fc245 100644
--- a/include/qemu/cpuid.h
+++ b/include/qemu/cpuid.h
@@ -45,6 +45,9 @@
#ifndef bit_AVX2
#define bit_AVX2 (1 << 5)
#endif
+#ifndef bit_AVX512F
+#define bit_AVX512F (1 << 16)
+#endif
#ifndef bit_BMI2
#define bit_BMI2 (1 << 8)
#endif
diff --git a/include/qemu/lockable.h b/include/qemu/lockable.h
index 84ea794..1aeb2cb 100644
--- a/include/qemu/lockable.h
+++ b/include/qemu/lockable.h
@@ -50,6 +50,7 @@
#define QEMU_LOCK_FUNC(x) ((QemuLockUnlockFunc *) \
QEMU_GENERIC(x, \
(QemuMutex *, qemu_mutex_lock), \
+ (QemuRecMutex *, qemu_rec_mutex_lock), \
(CoMutex *, qemu_co_mutex_lock), \
(QemuSpin *, qemu_spin_lock), \
unknown_lock_type))
@@ -57,6 +58,7 @@
#define QEMU_UNLOCK_FUNC(x) ((QemuLockUnlockFunc *) \
QEMU_GENERIC(x, \
(QemuMutex *, qemu_mutex_unlock), \
+ (QemuRecMutex *, qemu_rec_mutex_unlock), \
(CoMutex *, qemu_co_mutex_unlock), \
(QemuSpin *, qemu_spin_unlock), \
unknown_lock_type))
@@ -65,7 +67,7 @@
* In C++ it would be different, but then C++ wouldn't need QemuLockable
* either...
*/
-#define QEMU_MAKE_LOCKABLE_(x) qemu_make_lockable((x), &(QemuLockable) { \
+#define QEMU_MAKE_LOCKABLE_(x) (&(QemuLockable) { \
.object = (x), \
.lock = QEMU_LOCK_FUNC(x), \
.unlock = QEMU_UNLOCK_FUNC(x), \
@@ -73,12 +75,25 @@
/* QEMU_MAKE_LOCKABLE - Make a polymorphic QemuLockable
*
- * @x: a lock object (currently one of QemuMutex, CoMutex, QemuSpin).
+ * @x: a lock object (currently one of QemuMutex, QemuRecMutex, CoMutex, QemuSpin).
+ *
+ * Returns a QemuLockable object that can be passed around
+ * to a function that can operate with locks of any kind, or
+ * NULL if @x is %NULL.
+ */
+#define QEMU_MAKE_LOCKABLE(x) \
+ QEMU_GENERIC(x, \
+ (QemuLockable *, (x)), \
+ qemu_make_lockable((x), QEMU_MAKE_LOCKABLE_(x)))
+
+/* QEMU_MAKE_LOCKABLE_NONNULL - Make a polymorphic QemuLockable
+ *
+ * @x: a lock object (currently one of QemuMutex, QemuRecMutex, CoMutex, QemuSpin).
*
* Returns a QemuLockable object that can be passed around
* to a function that can operate with locks of any kind.
*/
-#define QEMU_MAKE_LOCKABLE(x) \
+#define QEMU_MAKE_LOCKABLE_NONNULL(x) \
QEMU_GENERIC(x, \
(QemuLockable *, (x)), \
QEMU_MAKE_LOCKABLE_(x))
@@ -93,4 +108,69 @@
x->unlock(x->object);
}
+static inline QemuLockable *qemu_lockable_auto_lock(QemuLockable *x)
+{
+ qemu_lockable_lock(x);
+ return x;
+}
+
+static inline void qemu_lockable_auto_unlock(QemuLockable *x)
+{
+ if (x) {
+ qemu_lockable_unlock(x);
+ }
+}
+
+G_DEFINE_AUTOPTR_CLEANUP_FUNC(QemuLockable, qemu_lockable_auto_unlock)
+
+#define WITH_QEMU_LOCK_GUARD_(x, var) \
+ for (g_autoptr(QemuLockable) var = \
+ qemu_lockable_auto_lock(QEMU_MAKE_LOCKABLE_NONNULL((x))); \
+ var; \
+ qemu_lockable_auto_unlock(var), var = NULL)
+
+/**
+ * WITH_QEMU_LOCK_GUARD - Lock a lock object for scope
+ *
+ * @x: a lock object (currently one of QemuMutex, CoMutex, QemuSpin).
+ *
+ * This macro defines a lock scope such that entering the scope takes the lock
+ * and leaving the scope releases the lock. Return statements are allowed
+ * within the scope and release the lock. Break and continue statements leave
+ * the scope early and release the lock.
+ *
+ * WITH_QEMU_LOCK_GUARD(&mutex) {
+ * ...
+ * if (error) {
+ * return; <-- mutex is automatically unlocked
+ * }
+ *
+ * if (early_exit) {
+ * break; <-- leave this scope early
+ * }
+ * ...
+ * }
+ */
+#define WITH_QEMU_LOCK_GUARD(x) \
+ WITH_QEMU_LOCK_GUARD_((x), qemu_lockable_auto##__COUNTER__)
+
+/**
+ * QEMU_LOCK_GUARD - Lock an object until the end of the scope
+ *
+ * @x: a lock object (currently one of QemuMutex, CoMutex, QemuSpin).
+ *
+ * This macro takes a lock until the end of the scope. Return statements
+ * release the lock.
+ *
+ * ... <-- mutex not locked
+ * QEMU_LOCK_GUARD(&mutex); <-- mutex locked from here onwards
+ * ...
+ * if (error) {
+ * return; <-- mutex is automatically unlocked
+ * }
+ */
+#define QEMU_LOCK_GUARD(x) \
+ g_autoptr(QemuLockable) qemu_lockable_auto##__COUNTER__ = \
+ qemu_lockable_auto_lock(QEMU_MAKE_LOCKABLE((x)))
+
#endif
diff --git a/include/qom/object.h b/include/qom/object.h
index 2954649..784c97c 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -1664,69 +1664,101 @@
void (*get)(Object *, struct tm *, Error **),
Error **errp);
+typedef enum {
+ /* Automatically add a getter to the property */
+ OBJ_PROP_FLAG_READ = 1 << 0,
+ /* Automatically add a setter to the property */
+ OBJ_PROP_FLAG_WRITE = 1 << 1,
+ /* Automatically add a getter and a setter to the property */
+ OBJ_PROP_FLAG_READWRITE = (OBJ_PROP_FLAG_READ | OBJ_PROP_FLAG_WRITE),
+} ObjectPropertyFlags;
+
/**
* object_property_add_uint8_ptr:
* @obj: the object to add a property to
* @name: the name of the property
* @v: pointer to value
+ * @flags: bitwise-or'd ObjectPropertyFlags
* @errp: if an error occurs, a pointer to an area to store the error
*
* Add an integer property in memory. This function will add a
* property of type 'uint8'.
*/
void object_property_add_uint8_ptr(Object *obj, const char *name,
- const uint8_t *v, Error **errp);
+ const uint8_t *v, ObjectPropertyFlags flags,
+ Error **errp);
+
ObjectProperty *object_class_property_add_uint8_ptr(ObjectClass *klass,
const char *name,
- const uint8_t *v, Error **errp);
+ const uint8_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp);
/**
* object_property_add_uint16_ptr:
* @obj: the object to add a property to
* @name: the name of the property
* @v: pointer to value
+ * @flags: bitwise-or'd ObjectPropertyFlags
* @errp: if an error occurs, a pointer to an area to store the error
*
* Add an integer property in memory. This function will add a
* property of type 'uint16'.
*/
void object_property_add_uint16_ptr(Object *obj, const char *name,
- const uint16_t *v, Error **errp);
+ const uint16_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp);
+
ObjectProperty *object_class_property_add_uint16_ptr(ObjectClass *klass,
const char *name,
- const uint16_t *v, Error **errp);
+ const uint16_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp);
/**
* object_property_add_uint32_ptr:
* @obj: the object to add a property to
* @name: the name of the property
* @v: pointer to value
+ * @flags: bitwise-or'd ObjectPropertyFlags
* @errp: if an error occurs, a pointer to an area to store the error
*
* Add an integer property in memory. This function will add a
* property of type 'uint32'.
*/
void object_property_add_uint32_ptr(Object *obj, const char *name,
- const uint32_t *v, Error **errp);
+ const uint32_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp);
+
ObjectProperty *object_class_property_add_uint32_ptr(ObjectClass *klass,
const char *name,
- const uint32_t *v, Error **errp);
+ const uint32_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp);
/**
* object_property_add_uint64_ptr:
* @obj: the object to add a property to
* @name: the name of the property
* @v: pointer to value
+ * @flags: bitwise-or'd ObjectPropertyFlags
* @errp: if an error occurs, a pointer to an area to store the error
*
* Add an integer property in memory. This function will add a
* property of type 'uint64'.
*/
void object_property_add_uint64_ptr(Object *obj, const char *name,
- const uint64_t *v, Error **errp);
+ const uint64_t *v,
+ ObjectPropertyFlags flags,
+ Error **Errp);
+
ObjectProperty *object_class_property_add_uint64_ptr(ObjectClass *klass,
const char *name,
- const uint64_t *v, Error **errp);
+ const uint64_t *v,
+ ObjectPropertyFlags flags,
+ Error **Errp);
/**
* object_property_add_alias:
diff --git a/include/sysemu/cryptodev.h b/include/sysemu/cryptodev.h
index a9afb7e..35eab06 100644
--- a/include/sysemu/cryptodev.h
+++ b/include/sysemu/cryptodev.h
@@ -143,7 +143,7 @@
uint8_t *dst;
uint8_t *aad_data;
uint8_t *digest_result;
- uint8_t data[0];
+ uint8_t data[];
} CryptoDevBackendSymOpInfo;
typedef struct CryptoDevBackendClass {
diff --git a/include/sysemu/whpx.h b/include/sysemu/whpx.h
index 4794e8e..a84b49e 100644
--- a/include/sysemu/whpx.h
+++ b/include/sysemu/whpx.h
@@ -35,4 +35,11 @@
#endif /* CONFIG_WHPX */
+/* state subset only touched by the VCPU itself during runtime */
+#define WHPX_SET_RUNTIME_STATE 1
+/* state subset modified during VCPU reset */
+#define WHPX_SET_RESET_STATE 2
+/* full state set, modified during initialization or on vmload */
+#define WHPX_SET_FULL_STATE 3
+
#endif /* QEMU_WHPX_H */
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 54e5446..c48bd76 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -267,7 +267,7 @@
typedef struct TCGPool {
struct TCGPool *next;
int size;
- uint8_t data[0] __attribute__ ((aligned));
+ uint8_t data[] __attribute__ ((aligned));
} TCGPool;
#define TCG_POOL_CHUNK_SIZE 32768
diff --git a/memory.c b/memory.c
index 09be40e..601b749 100644
--- a/memory.c
+++ b/memory.c
@@ -1170,15 +1170,6 @@
memory_region_do_init(mr, owner, name, size);
}
-static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- MemoryRegion *mr = MEMORY_REGION(obj);
- uint64_t value = mr->addr;
-
- visit_type_uint64(v, name, &value, errp);
-}
-
static void memory_region_get_container(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
@@ -1242,10 +1233,8 @@
NULL, NULL, &error_abort);
op->resolve = memory_region_resolve_container;
- object_property_add(OBJECT(mr), "addr", "uint64",
- memory_region_get_addr,
- NULL, /* memory_region_set_addr */
- NULL, NULL, &error_abort);
+ object_property_add_uint64_ptr(OBJECT(mr), "addr",
+ &mr->addr, OBJ_PROP_FLAG_READ, &error_abort);
object_property_add(OBJECT(mr), "priority", "uint32",
memory_region_get_priority,
NULL, /* memory_region_set_priority */
@@ -1671,19 +1660,8 @@
uint64_t size,
Error **errp)
{
- Error *err = NULL;
- memory_region_init(mr, owner, name, size);
- mr->ram = true;
+ memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
mr->readonly = true;
- mr->terminates = true;
- mr->destructor = memory_region_destructor_ram;
- mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
- mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
- if (err) {
- mr->size = int128_zero();
- object_unparent(OBJECT(mr));
- error_propagate(errp, err);
- }
}
void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
@@ -2830,6 +2808,9 @@
static const char *memory_region_type(MemoryRegion *mr)
{
+ if (mr->alias) {
+ return memory_region_type(mr->alias);
+ }
if (memory_region_is_ram_device(mr)) {
return "ramd";
} else if (memory_region_is_romd(mr)) {
diff --git a/net/queue.c b/net/queue.c
index 61276ca..0164727 100644
--- a/net/queue.c
+++ b/net/queue.c
@@ -46,7 +46,7 @@
unsigned flags;
int size;
NetPacketSent *sent_cb;
- uint8_t data[0];
+ uint8_t data[];
};
struct NetQueue {
diff --git a/pc-bios/README b/pc-bios/README
index d6d33d2..f54c274 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -14,7 +14,7 @@
- SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
implementation for certain IBM POWER hardware. The sources are at
https://github.com/aik/SLOF, and the image currently in qemu is
- built from git tag qemu-slof-20191217.
+ built from git tag qemu-slof-20200317.
- sgabios (the Serial Graphics Adapter option ROM) provides a means for
legacy x86 software to communicate with an attached serial console as
diff --git a/pc-bios/optionrom/pvh_main.c b/pc-bios/optionrom/pvh_main.c
index a015e1b..28e79d7 100644
--- a/pc-bios/optionrom/pvh_main.c
+++ b/pc-bios/optionrom/pvh_main.c
@@ -29,7 +29,7 @@
#define RSDP_SIGNATURE 0x2052545020445352LL /* "RSD PTR " */
#define RSDP_AREA_ADDR 0x000E0000
-#define RSDP_AREA_SIZE 2048
+#define RSDP_AREA_SIZE 0x00020000
#define EBDA_BASE_ADDR 0x0000040E
#define EBDA_SIZE 1024
diff --git a/pc-bios/s390-ccw/bootmap.h b/pc-bios/s390-ccw/bootmap.h
index 94f53a5..12a0166 100644
--- a/pc-bios/s390-ccw/bootmap.h
+++ b/pc-bios/s390-ccw/bootmap.h
@@ -136,7 +136,7 @@
typedef struct BootMapScript {
BootMapScriptHeader header;
- BootMapScriptEntry entry[0];
+ BootMapScriptEntry entry[];
} __attribute__ ((packed)) BootMapScript;
/*
diff --git a/pc-bios/s390-ccw/sclp.h b/pc-bios/s390-ccw/sclp.h
index 8450161..64b53ca 100644
--- a/pc-bios/s390-ccw/sclp.h
+++ b/pc-bios/s390-ccw/sclp.h
@@ -95,7 +95,7 @@
typedef struct WriteEventData {
SCCBHeader h;
EventBufferHeader ebh;
- char data[0];
+ char data[];
} __attribute__((packed)) WriteEventData;
typedef struct ReadEventData {
diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin
index 78d8b26..40499a1 100644
--- a/pc-bios/slof.bin
+++ b/pc-bios/slof.bin
Binary files differ
diff --git a/plugins/core.c b/plugins/core.c
index ed86301..51bfc94 100644
--- a/plugins/core.c
+++ b/plugins/core.c
@@ -15,6 +15,7 @@
#include "qemu/error-report.h"
#include "qemu/config-file.h"
#include "qapi/error.h"
+#include "qemu/lockable.h"
#include "qemu/option.h"
#include "qemu/rcu_queue.h"
#include "qemu/xxhash.h"
@@ -150,11 +151,11 @@
{
struct qemu_plugin_ctx *ctx;
- qemu_rec_mutex_lock(&plugin.lock);
+ QEMU_LOCK_GUARD(&plugin.lock);
ctx = plugin_id_to_ctx_locked(id);
/* if the plugin is on its way out, ignore this request */
if (unlikely(ctx->uninstalling)) {
- goto out_unlock;
+ return;
}
if (func) {
struct qemu_plugin_cb *cb = ctx->callbacks[ev];
@@ -178,8 +179,6 @@
} else {
plugin_unregister_cb__locked(ctx, ev);
}
- out_unlock:
- qemu_rec_mutex_unlock(&plugin.lock);
}
void plugin_register_cb(qemu_plugin_id_t id, enum qemu_plugin_event ev,
diff --git a/plugins/loader.c b/plugins/loader.c
index 15fc7e5..685d334 100644
--- a/plugins/loader.c
+++ b/plugins/loader.c
@@ -19,6 +19,7 @@
#include "qemu/error-report.h"
#include "qemu/config-file.h"
#include "qapi/error.h"
+#include "qemu/lockable.h"
#include "qemu/option.h"
#include "qemu/rcu_queue.h"
#include "qemu/qht.h"
@@ -367,15 +368,14 @@
struct qemu_plugin_reset_data *data;
struct qemu_plugin_ctx *ctx;
- qemu_rec_mutex_lock(&plugin.lock);
- ctx = plugin_id_to_ctx_locked(id);
- if (ctx->uninstalling || (reset && ctx->resetting)) {
- qemu_rec_mutex_unlock(&plugin.lock);
- return;
+ WITH_QEMU_LOCK_GUARD(&plugin.lock) {
+ ctx = plugin_id_to_ctx_locked(id);
+ if (ctx->uninstalling || (reset && ctx->resetting)) {
+ return;
+ }
+ ctx->resetting = reset;
+ ctx->uninstalling = !reset;
}
- ctx->resetting = reset;
- ctx->uninstalling = !reset;
- qemu_rec_mutex_unlock(&plugin.lock);
data = g_new(struct qemu_plugin_reset_data, 1);
data->ctx = ctx;
diff --git a/qom/object.c b/qom/object.c
index 555c8b9..1812f79 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -2498,6 +2498,22 @@
visit_type_uint8(v, name, &value, errp);
}
+static void property_set_uint8_ptr(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ uint8_t *field = opaque;
+ uint8_t value;
+ Error *local_err = NULL;
+
+ visit_type_uint8(v, name, &value, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ *field = value;
+}
+
static void property_get_uint16_ptr(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -2505,6 +2521,22 @@
visit_type_uint16(v, name, &value, errp);
}
+static void property_set_uint16_ptr(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ uint16_t *field = opaque;
+ uint16_t value;
+ Error *local_err = NULL;
+
+ visit_type_uint16(v, name, &value, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ *field = value;
+}
+
static void property_get_uint32_ptr(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -2512,6 +2544,22 @@
visit_type_uint32(v, name, &value, errp);
}
+static void property_set_uint32_ptr(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ uint32_t *field = opaque;
+ uint32_t value;
+ Error *local_err = NULL;
+
+ visit_type_uint32(v, name, &value, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ *field = value;
+}
+
static void property_get_uint64_ptr(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -2519,68 +2567,184 @@
visit_type_uint64(v, name, &value, errp);
}
-void object_property_add_uint8_ptr(Object *obj, const char *name,
- const uint8_t *v, Error **errp)
+static void property_set_uint64_ptr(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
{
- object_property_add(obj, name, "uint8", property_get_uint8_ptr,
- NULL, NULL, (void *)v, errp);
+ uint64_t *field = opaque;
+ uint64_t value;
+ Error *local_err = NULL;
+
+ visit_type_uint64(v, name, &value, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ *field = value;
+}
+
+void object_property_add_uint8_ptr(Object *obj, const char *name,
+ const uint8_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp)
+{
+ ObjectPropertyAccessor *getter = NULL;
+ ObjectPropertyAccessor *setter = NULL;
+
+ if ((flags & OBJ_PROP_FLAG_READ) == OBJ_PROP_FLAG_READ) {
+ getter = property_get_uint8_ptr;
+ }
+
+ if ((flags & OBJ_PROP_FLAG_WRITE) == OBJ_PROP_FLAG_WRITE) {
+ setter = property_set_uint8_ptr;
+ }
+
+ object_property_add(obj, name, "uint8",
+ getter, setter, NULL, (void *)v, errp);
}
ObjectProperty *
object_class_property_add_uint8_ptr(ObjectClass *klass, const char *name,
- const uint8_t *v, Error **errp)
+ const uint8_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp)
{
+ ObjectPropertyAccessor *getter = NULL;
+ ObjectPropertyAccessor *setter = NULL;
+
+ if ((flags & OBJ_PROP_FLAG_READ) == OBJ_PROP_FLAG_READ) {
+ getter = property_get_uint8_ptr;
+ }
+
+ if ((flags & OBJ_PROP_FLAG_WRITE) == OBJ_PROP_FLAG_WRITE) {
+ setter = property_set_uint8_ptr;
+ }
+
return object_class_property_add(klass, name, "uint8",
- property_get_uint8_ptr,
- NULL, NULL, (void *)v, errp);
+ getter, setter, NULL, (void *)v, errp);
}
void object_property_add_uint16_ptr(Object *obj, const char *name,
- const uint16_t *v, Error **errp)
+ const uint16_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp)
{
- object_property_add(obj, name, "uint16", property_get_uint16_ptr,
- NULL, NULL, (void *)v, errp);
+ ObjectPropertyAccessor *getter = NULL;
+ ObjectPropertyAccessor *setter = NULL;
+
+ if ((flags & OBJ_PROP_FLAG_READ) == OBJ_PROP_FLAG_READ) {
+ getter = property_get_uint16_ptr;
+ }
+
+ if ((flags & OBJ_PROP_FLAG_WRITE) == OBJ_PROP_FLAG_WRITE) {
+ setter = property_set_uint16_ptr;
+ }
+
+ object_property_add(obj, name, "uint16",
+ getter, setter, NULL, (void *)v, errp);
}
ObjectProperty *
object_class_property_add_uint16_ptr(ObjectClass *klass, const char *name,
- const uint16_t *v, Error **errp)
+ const uint16_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp)
{
+ ObjectPropertyAccessor *getter = NULL;
+ ObjectPropertyAccessor *setter = NULL;
+
+ if ((flags & OBJ_PROP_FLAG_READ) == OBJ_PROP_FLAG_READ) {
+ getter = property_get_uint16_ptr;
+ }
+
+ if ((flags & OBJ_PROP_FLAG_WRITE) == OBJ_PROP_FLAG_WRITE) {
+ setter = property_set_uint16_ptr;
+ }
+
return object_class_property_add(klass, name, "uint16",
- property_get_uint16_ptr,
- NULL, NULL, (void *)v, errp);
+ getter, setter, NULL, (void *)v, errp);
}
void object_property_add_uint32_ptr(Object *obj, const char *name,
- const uint32_t *v, Error **errp)
+ const uint32_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp)
{
- object_property_add(obj, name, "uint32", property_get_uint32_ptr,
- NULL, NULL, (void *)v, errp);
+ ObjectPropertyAccessor *getter = NULL;
+ ObjectPropertyAccessor *setter = NULL;
+
+ if ((flags & OBJ_PROP_FLAG_READ) == OBJ_PROP_FLAG_READ) {
+ getter = property_get_uint32_ptr;
+ }
+
+ if ((flags & OBJ_PROP_FLAG_WRITE) == OBJ_PROP_FLAG_WRITE) {
+ setter = property_set_uint32_ptr;
+ }
+
+ object_property_add(obj, name, "uint32",
+ getter, setter, NULL, (void *)v, errp);
}
ObjectProperty *
object_class_property_add_uint32_ptr(ObjectClass *klass, const char *name,
- const uint32_t *v, Error **errp)
+ const uint32_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp)
{
+ ObjectPropertyAccessor *getter = NULL;
+ ObjectPropertyAccessor *setter = NULL;
+
+ if ((flags & OBJ_PROP_FLAG_READ) == OBJ_PROP_FLAG_READ) {
+ getter = property_get_uint32_ptr;
+ }
+
+ if ((flags & OBJ_PROP_FLAG_WRITE) == OBJ_PROP_FLAG_WRITE) {
+ setter = property_set_uint32_ptr;
+ }
+
return object_class_property_add(klass, name, "uint32",
- property_get_uint32_ptr,
- NULL, NULL, (void *)v, errp);
+ getter, setter, NULL, (void *)v, errp);
}
void object_property_add_uint64_ptr(Object *obj, const char *name,
- const uint64_t *v, Error **errp)
+ const uint64_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp)
{
- object_property_add(obj, name, "uint64", property_get_uint64_ptr,
- NULL, NULL, (void *)v, errp);
+ ObjectPropertyAccessor *getter = NULL;
+ ObjectPropertyAccessor *setter = NULL;
+
+ if ((flags & OBJ_PROP_FLAG_READ) == OBJ_PROP_FLAG_READ) {
+ getter = property_get_uint64_ptr;
+ }
+
+ if ((flags & OBJ_PROP_FLAG_WRITE) == OBJ_PROP_FLAG_WRITE) {
+ setter = property_set_uint64_ptr;
+ }
+
+ object_property_add(obj, name, "uint64",
+ getter, setter, NULL, (void *)v, errp);
}
ObjectProperty *
object_class_property_add_uint64_ptr(ObjectClass *klass, const char *name,
- const uint64_t *v, Error **errp)
+ const uint64_t *v,
+ ObjectPropertyFlags flags,
+ Error **errp)
{
+ ObjectPropertyAccessor *getter = NULL;
+ ObjectPropertyAccessor *setter = NULL;
+
+ if ((flags & OBJ_PROP_FLAG_READ) == OBJ_PROP_FLAG_READ) {
+ getter = property_get_uint64_ptr;
+ }
+
+ if ((flags & OBJ_PROP_FLAG_WRITE) == OBJ_PROP_FLAG_WRITE) {
+ setter = property_set_uint64_ptr;
+ }
+
return object_class_property_add(klass, name, "uint64",
- property_get_uint64_ptr,
- NULL, NULL, (void *)v, errp);
+ getter, setter, NULL, (void *)v, errp);
}
typedef struct {
diff --git a/roms/SLOF b/roms/SLOF
index 9546892..ab6984f 160000
--- a/roms/SLOF
+++ b/roms/SLOF
@@ -1 +1 @@
-Subproject commit 9546892a80d5a4c73deea6719de46372f007f4a6
+Subproject commit ab6984f5a6d054e1f634dda855b32e5357111974
diff --git a/scripts/coccinelle/memory-region-housekeeping.cocci b/scripts/coccinelle/memory-region-housekeeping.cocci
new file mode 100644
index 0000000..c768d81
--- /dev/null
+++ b/scripts/coccinelle/memory-region-housekeeping.cocci
@@ -0,0 +1,159 @@
+/*
+ Usage:
+
+ spatch \
+ --macro-file scripts/cocci-macro-file.h \
+ --sp-file scripts/coccinelle/memory-region-housekeeping.cocci \
+ --keep-comments \
+ --in-place \
+ --dir .
+
+*/
+
+
+// Replace memory_region_init_ram(readonly) by memory_region_init_rom()
+@@
+expression E1, E2, E3, E4, E5;
+symbol true;
+@@
+(
+- memory_region_init_ram(E1, E2, E3, E4, E5);
++ memory_region_init_rom(E1, E2, E3, E4, E5);
+ ... WHEN != E1
+- memory_region_set_readonly(E1, true);
+|
+- memory_region_init_ram_nomigrate(E1, E2, E3, E4, E5);
++ memory_region_init_rom_nomigrate(E1, E2, E3, E4, E5);
+ ... WHEN != E1
+- memory_region_set_readonly(E1, true);
+)
+
+
+@possible_memory_region_init_rom@
+expression E1, E2, E3, E4, E5;
+position p;
+@@
+(
+ memory_region_init_ram@p(E1, E2, E3, E4, E5);
+ ...
+ memory_region_set_readonly(E1, true);
+|
+ memory_region_init_ram_nomigrate@p(E1, E2, E3, E4, E5);
+ ...
+ memory_region_set_readonly(E1, true);
+)
+@script:python@
+p << possible_memory_region_init_rom.p;
+@@
+cocci.print_main("potential use of memory_region_init_rom*() in ", p)
+
+
+// Do not call memory_region_set_readonly() on ROM alias
+@@
+expression ROM, E1, E2, E3, E4;
+expression ALIAS, E5, E6, E7, E8;
+@@
+(
+ memory_region_init_rom(ROM, E1, E2, E3, E4);
+|
+ memory_region_init_rom_nomigrate(ROM, E1, E2, E3, E4);
+)
+ ...
+ memory_region_init_alias(ALIAS, E5, E6, ROM, E7, E8);
+- memory_region_set_readonly(ALIAS, true);
+
+
+// Replace by-hand memory_region_init_ram_nomigrate/vmstate_register_ram
+// code sequences with use of the new memory_region_init_ram function.
+// Similarly for the _rom and _rom_device functions.
+// We don't try to replace sequences with a non-NULL owner, because
+// there are none in the tree that can be automatically converted
+// (and only a handful that can be manually converted).
+@@
+expression MR;
+expression NAME;
+expression SIZE;
+expression ERRP;
+@@
+-memory_region_init_ram_nomigrate(MR, NULL, NAME, SIZE, ERRP);
++memory_region_init_ram(MR, NULL, NAME, SIZE, ERRP);
+ ...
+-vmstate_register_ram_global(MR);
+@@
+expression MR;
+expression NAME;
+expression SIZE;
+expression ERRP;
+@@
+-memory_region_init_rom_nomigrate(MR, NULL, NAME, SIZE, ERRP);
++memory_region_init_rom(MR, NULL, NAME, SIZE, ERRP);
+ ...
+-vmstate_register_ram_global(MR);
+@@
+expression MR;
+expression OPS;
+expression OPAQUE;
+expression NAME;
+expression SIZE;
+expression ERRP;
+@@
+-memory_region_init_rom_device_nomigrate(MR, NULL, OPS, OPAQUE, NAME, SIZE, ERRP);
++memory_region_init_rom_device(MR, NULL, OPS, OPAQUE, NAME, SIZE, ERRP);
+ ...
+-vmstate_register_ram_global(MR);
+
+
+// Device is owner
+@@
+typedef DeviceState;
+identifier device_fn, dev, obj;
+expression E1, E2, E3, E4, E5;
+@@
+static void device_fn(DeviceState *dev, ...)
+{
+ ...
+ Object *obj = OBJECT(dev);
+ <+...
+(
+- memory_region_init(E1, NULL, E2, E3);
++ memory_region_init(E1, obj, E2, E3);
+|
+- memory_region_init_io(E1, NULL, E2, E3, E4, E5);
++ memory_region_init_io(E1, obj, E2, E3, E4, E5);
+|
+- memory_region_init_alias(E1, NULL, E2, E3, E4, E5);
++ memory_region_init_alias(E1, obj, E2, E3, E4, E5);
+|
+- memory_region_init_rom(E1, NULL, E2, E3, E4);
++ memory_region_init_rom(E1, obj, E2, E3, E4);
+|
+- memory_region_init_ram_shared_nomigrate(E1, NULL, E2, E3, E4, E5);
++ memory_region_init_ram_shared_nomigrate(E1, obj, E2, E3, E4, E5);
+)
+ ...+>
+}
+@@
+identifier device_fn, dev;
+expression E1, E2, E3, E4, E5;
+@@
+static void device_fn(DeviceState *dev, ...)
+{
+ <+...
+(
+- memory_region_init(E1, NULL, E2, E3);
++ memory_region_init(E1, OBJECT(dev), E2, E3);
+|
+- memory_region_init_io(E1, NULL, E2, E3, E4, E5);
++ memory_region_init_io(E1, OBJECT(dev), E2, E3, E4, E5);
+|
+- memory_region_init_alias(E1, NULL, E2, E3, E4, E5);
++ memory_region_init_alias(E1, OBJECT(dev), E2, E3, E4, E5);
+|
+- memory_region_init_rom(E1, NULL, E2, E3, E4);
++ memory_region_init_rom(E1, OBJECT(dev), E2, E3, E4);
+|
+- memory_region_init_ram_shared_nomigrate(E1, NULL, E2, E3, E4, E5);
++ memory_region_init_ram_shared_nomigrate(E1, OBJECT(dev), E2, E3, E4, E5);
+)
+ ...+>
+}
diff --git a/scripts/coccinelle/memory-region-init-ram.cocci b/scripts/coccinelle/memory-region-init-ram.cocci
deleted file mode 100644
index d290150..0000000
--- a/scripts/coccinelle/memory-region-init-ram.cocci
+++ /dev/null
@@ -1,38 +0,0 @@
-// Replace by-hand memory_region_init_ram_nomigrate/vmstate_register_ram
-// code sequences with use of the new memory_region_init_ram function.
-// Similarly for the _rom and _rom_device functions.
-// We don't try to replace sequences with a non-NULL owner, because
-// there are none in the tree that can be automatically converted
-// (and only a handful that can be manually converted).
-@@
-expression MR;
-expression NAME;
-expression SIZE;
-expression ERRP;
-@@
--memory_region_init_ram_nomigrate(MR, NULL, NAME, SIZE, ERRP);
-+memory_region_init_ram(MR, NULL, NAME, SIZE, ERRP);
- ...
--vmstate_register_ram_global(MR);
-@@
-expression MR;
-expression NAME;
-expression SIZE;
-expression ERRP;
-@@
--memory_region_init_rom_nomigrate(MR, NULL, NAME, SIZE, ERRP);
-+memory_region_init_rom(MR, NULL, NAME, SIZE, ERRP);
- ...
--vmstate_register_ram_global(MR);
-@@
-expression MR;
-expression OPS;
-expression OPAQUE;
-expression NAME;
-expression SIZE;
-expression ERRP;
-@@
--memory_region_init_rom_device_nomigrate(MR, NULL, OPS, OPAQUE, NAME, SIZE, ERRP);
-+memory_region_init_rom_device(MR, NULL, OPS, OPAQUE, NAME, SIZE, ERRP);
- ...
--vmstate_register_ram_global(MR);
diff --git a/scsi/qemu-pr-helper.c b/scsi/qemu-pr-helper.c
index 0659cee..181ed4a 100644
--- a/scsi/qemu-pr-helper.c
+++ b/scsi/qemu-pr-helper.c
@@ -421,10 +421,13 @@
int rq_servact = cdb[1];
int rq_scope = cdb[2] >> 4;
int rq_type = cdb[2] & 0xf;
- struct prout_param_descriptor paramp;
+ g_autofree struct prout_param_descriptor *paramp = NULL;
char transportids[PR_HELPER_DATA_SIZE];
int r;
+ paramp = g_malloc0(sizeof(struct prout_param_descriptor)
+ + sizeof(struct transportid *) * MPATH_MX_TIDS);
+
if (sz < PR_OUT_FIXED_PARAM_SIZE) {
/* Illegal request, Parameter list length error. This isn't fatal;
* we have read the data, send an error without closing the socket.
@@ -454,10 +457,9 @@
* used by libmpathpersist (which, of course, will immediately
* do the opposite).
*/
- memset(¶mp, 0, sizeof(paramp));
- memcpy(¶mp.key, ¶m[0], 8);
- memcpy(¶mp.sa_key, ¶m[8], 8);
- paramp.sa_flags = param[20];
+ memcpy(¶mp->key, ¶m[0], 8);
+ memcpy(¶mp->sa_key, ¶m[8], 8);
+ paramp->sa_flags = param[20];
if (sz > PR_OUT_FIXED_PARAM_SIZE) {
size_t transportid_len;
int i, j;
@@ -520,12 +522,13 @@
return CHECK_CONDITION;
}
- paramp.trnptid_list[paramp.num_transportid++] = id;
+ assert(paramp->num_transportid < MPATH_MX_TIDS);
+ paramp->trnptid_list[paramp->num_transportid++] = id;
}
}
r = mpath_persistent_reserve_out(fd, rq_servact, rq_scope, rq_type,
- ¶mp, noisy, verbose);
+ paramp, noisy, verbose);
return mpath_reconstruct_sense(fd, r, sense);
}
#endif
diff --git a/softmmu/vl.c b/softmmu/vl.c
index ff2685d..6a28592 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -3789,6 +3789,22 @@
*/
loc_set_none();
+ /*
+ * Check for -cpu help and -device help before we call select_machine(),
+ * which will return an error if the architecture has no default machine
+ * type and the user did not specify one, so that the user doesn't need
+ * to say '-cpu help -machine something'.
+ */
+ if (cpu_option && is_help_option(cpu_option)) {
+ list_cpus(cpu_option);
+ exit(0);
+ }
+
+ if (qemu_opts_foreach(qemu_find_opts("device"),
+ device_help_func, NULL, NULL)) {
+ exit(0);
+ }
+
user_register_global_props();
replay_configure(icount_opts);
@@ -3877,11 +3893,6 @@
qemu_set_hw_version(machine_class->hw_version);
}
- if (cpu_option && is_help_option(cpu_option)) {
- list_cpus(cpu_option);
- exit(0);
- }
-
if (!trace_init_backends()) {
exit(1);
}
@@ -4112,11 +4123,6 @@
fsdev_init_func, NULL, &error_fatal);
#endif
- if (qemu_opts_foreach(qemu_find_opts("device"),
- device_help_func, NULL, NULL)) {
- exit(0);
- }
-
/*
* Note: we need to create block backends before
* machine_set_property(), so machine properties can refer to
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 3f782c0..be29bdd 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -280,7 +280,7 @@
bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c
index 7f9cc09..0cd76dd 100644
--- a/target/alpha/gdbstub.c
+++ b/target/alpha/gdbstub.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/gdbstub.h"
-int alpha_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
CPUAlphaState *env = &cpu->env;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3623ece..3a5d137 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -195,9 +195,10 @@
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
/* and to the SVE instructions */
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
- /* with maximum vector length */
- env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
- cpu->sve_max_vq - 1 : 0;
+ /* with reasonable vector length */
+ if (cpu_isar_feature(aa64_sve, cpu)) {
+ env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3);
+ }
/*
* Enable TBI0 and TBI1. While the real kernel only enables TBI0,
* turning on both here will produce smaller code and otherwise
@@ -1153,22 +1154,6 @@
cpu->has_pmu = value;
}
-static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- visit_type_uint32(v, name, &cpu->init_svtor, errp);
-}
-
-static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- visit_type_uint32(v, name, &cpu->init_svtor, errp);
-}
-
unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
{
/*
@@ -1288,9 +1273,9 @@
* a simple DEFINE_PROP_UINT32 for this because we want to permit
* the property to be set after realize.
*/
- object_property_add(obj, "init-svtor", "uint32",
- arm_get_init_svtor, arm_set_init_svtor,
- NULL, NULL, &error_abort);
+ object_property_add_uint32_ptr(obj, "init-svtor",
+ &cpu->init_svtor,
+ OBJ_PROP_FLAG_READWRITE, &error_abort);
}
qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4ffd991..8b9f296 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -128,14 +128,20 @@
/**
* DynamicGDBXMLInfo:
* @desc: Contains the XML descriptions.
- * @num_cpregs: Number of the Coprocessor registers seen by GDB.
- * @cpregs_keys: Array that contains the corresponding Key of
- * a given cpreg with the same order of the cpreg in the XML description.
+ * @num: Number of the registers in this XML seen by GDB.
+ * @data: A union with data specific to the set of registers
+ * @cpregs_keys: Array that contains the corresponding Key of
+ * a given cpreg with the same order of the cpreg
+ * in the XML description.
*/
typedef struct DynamicGDBXMLInfo {
char *desc;
- int num_cpregs;
- uint32_t *cpregs_keys;
+ int num;
+ union {
+ struct {
+ uint32_t *keys;
+ } cpregs;
+ } data;
} DynamicGDBXMLInfo;
/* CPU state for each instance of a generic timer (in cp15 c14) */
@@ -749,7 +755,8 @@
uint64_t *cpreg_vmstate_values;
int32_t cpreg_vmstate_array_len;
- DynamicGDBXMLInfo dyn_xml;
+ DynamicGDBXMLInfo dyn_sysreg_xml;
+ DynamicGDBXMLInfo dyn_svereg_xml;
/* Timers used by the generic (architected) timer */
QEMUTimer *gt_timer[NUM_GTIMERS];
@@ -968,13 +975,15 @@
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
-int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-/* Dynamically generates for gdb stub an XML description of the sysregs from
- * the cp_regs hashtable. Returns the registered sysregs number.
+/*
+ * Helpers to dynamically generates XML descriptions of the sysregs
+ * and SVE registers. Returns the number of registers in each set.
*/
-int arm_gen_dynamic_xml(CPUState *cpu);
+int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
+int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
/* Returns the dynamically generated XML for the gdb stub.
* Returns a pointer to the XML contents for the specified XML file or NULL
@@ -988,7 +997,7 @@
int cpuid, void *opaque);
#ifdef TARGET_AARCH64
-int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
void aarch64_sve_change_el(CPUARMState *env, int old_el,
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 1239abd..d9ef7d2 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -24,6 +24,7 @@
typedef struct RegisterSysregXmlParam {
CPUState *cs;
GString *s;
+ int n;
} RegisterSysregXmlParam;
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
@@ -32,7 +33,7 @@
We hack round this by giving the FPA regs zero size when talking to a
newer gdb. */
-int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
@@ -106,15 +107,16 @@
return 0;
}
-static void arm_gen_one_xml_reg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
- ARMCPRegInfo *ri, uint32_t ri_key,
- int bitsize)
+static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
+ ARMCPRegInfo *ri, uint32_t ri_key,
+ int bitsize, int regnum)
{
g_string_append_printf(s, "<reg name=\"%s\"", ri->name);
g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
+ g_string_append_printf(s, " regnum=\"%d\"", regnum);
g_string_append_printf(s, " group=\"cp_regs\"/>");
- dyn_xml->num_cpregs++;
- dyn_xml->cpregs_keys[dyn_xml->num_cpregs - 1] = ri_key;
+ dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key;
+ dyn_xml->num++;
}
static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
@@ -126,12 +128,13 @@
GString *s = param->s;
ARMCPU *cpu = ARM_CPU(param->cs);
CPUARMState *env = &cpu->env;
- DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_xml;
+ DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml;
if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) {
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
if (ri->state == ARM_CP_STATE_AA64) {
- arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64);
+ arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
+ param->n++);
}
} else {
if (ri->state == ARM_CP_STATE_AA32) {
@@ -140,38 +143,174 @@
return;
}
if (ri->type & ARM_CP_64BIT) {
- arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 64);
+ arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
+ param->n++);
} else {
- arm_gen_one_xml_reg_tag(s , dyn_xml, ri, ri_key, 32);
+ arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32,
+ param->n++);
}
}
}
}
}
-int arm_gen_dynamic_xml(CPUState *cs)
+int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
{
ARMCPU *cpu = ARM_CPU(cs);
GString *s = g_string_new(NULL);
- RegisterSysregXmlParam param = {cs, s};
+ RegisterSysregXmlParam param = {cs, s, base_reg};
- cpu->dyn_xml.num_cpregs = 0;
- cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
+ cpu->dyn_sysreg_xml.num = 0;
+ cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
g_string_printf(s, "<?xml version=\"1.0\"?>");
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m);
g_string_append_printf(s, "</feature>");
- cpu->dyn_xml.desc = g_string_free(s, false);
- return cpu->dyn_xml.num_cpregs;
+ cpu->dyn_sysreg_xml.desc = g_string_free(s, false);
+ return cpu->dyn_sysreg_xml.num;
}
+struct TypeSize {
+ const char *gdb_type;
+ int size;
+ const char sz, suffix;
+};
+
+static const struct TypeSize vec_lanes[] = {
+ /* quads */
+ { "uint128", 128, 'q', 'u' },
+ { "int128", 128, 'q', 's' },
+ /* 64 bit */
+ { "uint64", 64, 'd', 'u' },
+ { "int64", 64, 'd', 's' },
+ { "ieee_double", 64, 'd', 'f' },
+ /* 32 bit */
+ { "uint32", 32, 's', 'u' },
+ { "int32", 32, 's', 's' },
+ { "ieee_single", 32, 's', 'f' },
+ /* 16 bit */
+ { "uint16", 16, 'h', 'u' },
+ { "int16", 16, 'h', 's' },
+ { "ieee_half", 16, 'h', 'f' },
+ /* bytes */
+ { "uint8", 8, 'b', 'u' },
+ { "int8", 8, 'b', 's' },
+};
+
+
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ GString *s = g_string_new(NULL);
+ DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+ g_autoptr(GString) ts = g_string_new("");
+ int i, bits, reg_width = (cpu->sve_max_vq * 128);
+ info->num = 0;
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+ g_string_append_printf(s, "<feature name=\"org.qemu.gdb.aarch64.sve\">");
+
+ /* First define types and totals in a whole VL */
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+ int count = reg_width / vec_lanes[i].size;
+ g_string_printf(ts, "vq%d%c%c", count,
+ vec_lanes[i].sz, vec_lanes[i].suffix);
+ g_string_append_printf(s,
+ "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
+ ts->str, vec_lanes[i].gdb_type, count);
+ }
+ /*
+ * Now define a union for each size group containing unsigned and
+ * signed and potentially float versions of each size from 128 to
+ * 8 bits.
+ */
+ for (bits = 128; bits >= 8; bits /= 2) {
+ int count = reg_width / bits;
+ g_string_append_printf(s, "<union id=\"vq%dn\">", count);
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+ if (vec_lanes[i].size == bits) {
+ g_string_append_printf(s, "<field name=\"%c\" type=\"vq%d%c%c\"/>",
+ vec_lanes[i].suffix,
+ count,
+ vec_lanes[i].sz, vec_lanes[i].suffix);
+ }
+ }
+ g_string_append(s, "</union>");
+ }
+ /* And now the final union of unions */
+ g_string_append(s, "<union id=\"vq\">");
+ for (bits = 128; bits >= 8; bits /= 2) {
+ int count = reg_width / bits;
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+ if (vec_lanes[i].size == bits) {
+ g_string_append_printf(s, "<field name=\"%c\" type=\"vq%dn\"/>",
+ vec_lanes[i].sz, count);
+ break;
+ }
+ }
+ }
+ g_string_append(s, "</union>");
+
+ /* Then define each register in parts for each vq */
+ for (i = 0; i < 32; i++) {
+ g_string_append_printf(s,
+ "<reg name=\"z%d\" bitsize=\"%d\""
+ " regnum=\"%d\" group=\"vector\""
+ " type=\"vq\"/>",
+ i, reg_width, base_reg++);
+ info->num++;
+ }
+ /* fpscr & status registers */
+ g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
+ " regnum=\"%d\" group=\"float\""
+ " type=\"int\"/>", base_reg++);
+ g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
+ " regnum=\"%d\" group=\"float\""
+ " type=\"int\"/>", base_reg++);
+ info->num += 2;
+ /*
+ * Predicate registers aren't so big they are worth splitting up
+ * but we do need to define a type to hold the array of quad
+ * references.
+ */
+ g_string_append_printf(s,
+ "<vector id=\"vqp\" type=\"uint16\" count=\"%d\"/>",
+ cpu->sve_max_vq);
+ for (i = 0; i < 16; i++) {
+ g_string_append_printf(s,
+ "<reg name=\"p%d\" bitsize=\"%d\""
+ " regnum=\"%d\" group=\"vector\""
+ " type=\"vqp\"/>",
+ i, cpu->sve_max_vq * 16, base_reg++);
+ info->num++;
+ }
+ g_string_append_printf(s,
+ "<reg name=\"ffr\" bitsize=\"%d\""
+ " regnum=\"%d\" group=\"vector\""
+ " type=\"vqp\"/>",
+ cpu->sve_max_vq * 16, base_reg++);
+ g_string_append_printf(s,
+ "<reg name=\"vg\" bitsize=\"64\""
+ " regnum=\"%d\" group=\"vector\""
+ " type=\"uint32\"/>",
+ base_reg++);
+ info->num += 2;
+ g_string_append_printf(s, "</feature>");
+ cpu->dyn_svereg_xml.desc = g_string_free(s, false);
+
+ return cpu->dyn_svereg_xml.num;
+}
+
+
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
{
ARMCPU *cpu = ARM_CPU(cs);
if (strcmp(xmlname, "system-registers.xml") == 0) {
- return cpu->dyn_xml.desc;
+ return cpu->dyn_sysreg_xml.desc;
+ } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
+ return cpu->dyn_svereg_xml.desc;
}
return NULL;
}
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 665ebb3..35d0b80 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -20,7 +20,7 @@
#include "cpu.h"
#include "exec/gdbstub.h"
-int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b61ee73..d2ec2c5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -48,30 +48,27 @@
static void switch_mode(CPUARMState *env, int mode);
-static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
+static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
{
ARMCPU *cpu = env_archcpu(env);
int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
/* VFP data registers are always little-endian. */
if (reg < nregs) {
- stq_le_p(buf, *aa32_vfp_dreg(env, reg));
- return 8;
+ return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
}
if (arm_feature(env, ARM_FEATURE_NEON)) {
/* Aliases for Q regs. */
nregs += 16;
if (reg < nregs) {
uint64_t *q = aa32_vfp_qreg(env, reg - 32);
- stq_le_p(buf, q[0]);
- stq_le_p(buf + 8, q[1]);
- return 16;
+ return gdb_get_reg128(buf, q[0], q[1]);
}
}
switch (reg - nregs) {
- case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
- case 1: stl_p(buf, vfp_get_fpscr(env)); return 4;
- case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
+ case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break;
+ case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break;
+ case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break;
}
return 0;
}
@@ -102,25 +99,21 @@
return 0;
}
-static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
+static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
{
switch (reg) {
case 0 ... 31:
- /* 128 bit FP register */
- {
- uint64_t *q = aa64_vfp_qreg(env, reg);
- stq_le_p(buf, q[0]);
- stq_le_p(buf + 8, q[1]);
- return 16;
- }
+ {
+ /* 128 bit FP register - quads are in LE order */
+ uint64_t *q = aa64_vfp_qreg(env, reg);
+ return gdb_get_reg128(buf, q[1], q[0]);
+ }
case 32:
/* FPSR */
- stl_p(buf, vfp_get_fpsr(env));
- return 4;
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
case 33:
/* FPCR */
- stl_p(buf, vfp_get_fpcr(env));
- return 4;
+ return gdb_get_reg32(buf,vfp_get_fpcr(env));
default:
return 0;
}
@@ -209,13 +202,22 @@
}
}
-static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg)
+/**
+ * arm_get/set_gdb_*: get/set a gdb register
+ * @env: the CPU state
+ * @buf: a buffer to copy to/from
+ * @reg: register number (offset from start of group)
+ *
+ * We return the number of bytes copied
+ */
+
+static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
{
ARMCPU *cpu = env_archcpu(env);
const ARMCPRegInfo *ri;
uint32_t key;
- key = cpu->dyn_xml.cpregs_keys[reg];
+ key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
ri = get_arm_cp_reginfo(cpu->cp_regs, key);
if (ri) {
if (cpreg_field_is_64bit(ri)) {
@@ -232,6 +234,102 @@
return 0;
}
+#ifdef TARGET_AARCH64
+static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ switch (reg) {
+ /* The first 32 registers are the zregs */
+ case 0 ... 31:
+ {
+ int vq, len = 0;
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
+ len += gdb_get_reg128(buf,
+ env->vfp.zregs[reg].d[vq * 2 + 1],
+ env->vfp.zregs[reg].d[vq * 2]);
+ }
+ return len;
+ }
+ case 32:
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
+ case 33:
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
+ /* then 16 predicates and the ffr */
+ case 34 ... 50:
+ {
+ int preg = reg - 34;
+ int vq, len = 0;
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
+ len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
+ }
+ return len;
+ }
+ case 51:
+ {
+ /*
+ * We report in Vector Granules (VG) which is 64bit in a Z reg
+ * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
+ */
+ int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
+ return gdb_get_reg32(buf, vq * 2);
+ }
+ default:
+ /* gdbstub asked for something out our range */
+ qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
+ break;
+ }
+
+ return 0;
+}
+
+static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ /* The first 32 registers are the zregs */
+ switch (reg) {
+ /* The first 32 registers are the zregs */
+ case 0 ... 31:
+ {
+ int vq, len = 0;
+ uint64_t *p = (uint64_t *) buf;
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
+ env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
+ env->vfp.zregs[reg].d[vq * 2] = *p++;
+ len += 16;
+ }
+ return len;
+ }
+ case 32:
+ vfp_set_fpsr(env, *(uint32_t *)buf);
+ return 4;
+ case 33:
+ vfp_set_fpcr(env, *(uint32_t *)buf);
+ return 4;
+ case 34 ... 50:
+ {
+ int preg = reg - 34;
+ int vq, len = 0;
+ uint64_t *p = (uint64_t *) buf;
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
+ env->vfp.pregs[preg].p[vq / 4] = *p++;
+ len += 8;
+ }
+ return len;
+ }
+ case 51:
+ /* cannot set vg via gdbstub */
+ return 0;
+ default:
+ /* gdbstub asked for something out our range */
+ break;
+ }
+
+ return 0;
+}
+#endif /* TARGET_AARCH64 */
+
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
{
/* Return true if the regdef would cause an assertion if you called
@@ -6599,6 +6697,7 @@
return pfr1;
}
+#ifndef CONFIG_USER_ONLY
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = env_archcpu(env);
@@ -6609,6 +6708,7 @@
}
return pfr0;
}
+#endif
/* Shared logic between LORID and the rest of the LOR* registers.
* Secure state has already been delt with.
@@ -7182,16 +7282,24 @@
* define new registers here.
*/
ARMCPRegInfo v8_idregs[] = {
- /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
- * know the right value for the GIC field until after we
- * define these regs.
+ /*
+ * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
+ * emulation because we don't know the right value for the
+ * GIC field until after we define these regs.
*/
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_NO_RAW,
+ .access = PL1_R,
+#ifdef CONFIG_USER_ONLY
+ .type = ARM_CP_CONST,
+ .resetvalue = cpu->isar.id_aa64pfr0
+#else
+ .type = ARM_CP_NO_RAW,
.accessfn = access_aa64_tid3,
.readfn = id_aa64pfr0_read,
- .writefn = arm_cp_write_ignore },
+ .writefn = arm_cp_write_ignore
+#endif
+ },
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -7966,9 +8074,22 @@
CPUARMState *env = &cpu->env;
if (arm_feature(env, ARM_FEATURE_AARCH64)) {
- gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
- aarch64_fpu_gdb_set_reg,
- 34, "aarch64-fpu.xml", 0);
+ /*
+ * The lower part of each SVE register aliases to the FPU
+ * registers so we don't need to include both.
+ */
+#ifdef TARGET_AARCH64
+ if (isar_feature_aa64_sve(&cpu->isar)) {
+ gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
+ arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
+ "sve-registers.xml", 0);
+ } else
+#endif
+ {
+ gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
+ aarch64_fpu_gdb_set_reg,
+ 34, "aarch64-fpu.xml", 0);
+ }
} else if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
51, "arm-neon.xml", 0);
@@ -7980,8 +8101,9 @@
19, "arm-vfp.xml", 0);
}
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
- arm_gen_dynamic_xml(cs),
+ arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
"system-registers.xml", 0);
+
}
/* Sort alphabetically by type name, except for "any". */
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index c2dc790..ea6598c 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -206,9 +206,7 @@
return NULL;
}
} else {
- Error *err = NULL;
- arm_cpu_finalize_features(ARM_CPU(obj), &err);
- assert(err == NULL);
+ arm_cpu_finalize_features(ARM_CPU(obj), &error_abort);
}
expansion_info = g_new0(CpuModelExpansionInfo, 1);
@@ -221,12 +219,10 @@
while ((name = cpu_model_advertised_features[i++]) != NULL) {
ObjectProperty *prop = object_property_find(obj, name, NULL);
if (prop) {
- Error *err = NULL;
QObject *value;
assert(prop->get);
- value = object_property_get_qobject(obj, name, &err);
- assert(!err);
+ value = object_property_get_qobject(obj, name, &error_abort);
qdict_put_obj(qdict_out, name, value);
}
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index ca240bc..8f08d76 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -195,8 +195,8 @@
hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
-int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
+int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
/* you can call this signal handler from your SIGBUS and SIGSEGV
diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c
index a3d76d2..b01b2aa 100644
--- a/target/cris/gdbstub.c
+++ b/target/cris/gdbstub.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/gdbstub.h"
-int crisv10_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
CRISCPU *cpu = CRIS_CPU(cs);
CPUCRISState *env = &cpu->env;
@@ -53,7 +53,7 @@
return 0;
}
-int cris_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int cris_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
CRISCPU *cpu = CRIS_CPU(cs);
CPUCRISState *env = &cpu->env;
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 6713d04..801a4fb 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -321,7 +321,7 @@
int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc);
hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
-int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void hppa_cpu_do_interrupt(CPUState *cpu);
bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c
index 341888a..a6428a2 100644
--- a/target/hppa/gdbstub.c
+++ b/target/hppa/gdbstub.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/gdbstub.h"
-int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 576f309..c2d8931 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1766,7 +1766,7 @@
hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
-int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void x86_cpu_exec_enter(CPUState *cpu);
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index 572ead6..f3d23b6 100644
--- a/target/i386/gdbstub.c
+++ b/target/i386/gdbstub.c
@@ -79,7 +79,7 @@
#endif
-int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
@@ -98,26 +98,22 @@
return gdb_get_reg64(mem_buf,
env->regs[gpr_map[n]] & 0xffffffffUL);
} else {
- memset(mem_buf, 0, sizeof(target_ulong));
- return sizeof(target_ulong);
+ return gdb_get_regl(mem_buf, 0);
}
} else {
return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
}
} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
-#ifdef USE_X86LDOUBLE
- /* FIXME: byteswap float values - after fixing fpregs layout. */
- memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
-#else
- memset(mem_buf, 0, 10);
-#endif
- return 10;
+ floatx80 *fp = (floatx80 *) &env->fpregs[n - IDX_FP_REGS];
+ int len = gdb_get_reg64(mem_buf, cpu_to_le64(fp->low));
+ len += gdb_get_reg16(mem_buf + len, cpu_to_le16(fp->high));
+ return len;
} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
n -= IDX_XMM_REGS;
if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
- stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0));
- stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1));
- return 16;
+ return gdb_get_reg128(mem_buf,
+ env->xmm_regs[n].ZMM_Q(0),
+ env->xmm_regs[n].ZMM_Q(1));
}
} else {
switch (n) {
@@ -290,10 +286,9 @@
return 4;
}
} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
-#ifdef USE_X86LDOUBLE
- /* FIXME: byteswap float values - after fixing fpregs layout. */
- memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
-#endif
+ floatx80 *fp = (floatx80 *) &env->fpregs[n - IDX_FP_REGS];
+ fp->low = le64_to_cpu(* (uint64_t *) mem_buf);
+ fp->high = le16_to_cpu(* (uint16_t *) (mem_buf + 8));
return 10;
} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
n -= IDX_XMM_REGS;
diff --git a/target/i386/hax-posix.c b/target/i386/hax-posix.c
index a5426a6..3bad89f 100644
--- a/target/i386/hax-posix.c
+++ b/target/i386/hax-posix.c
@@ -108,41 +108,12 @@
static char *hax_vm_devfs_string(int vm_id)
{
- char *name;
-
- if (vm_id > MAX_VM_ID) {
- fprintf(stderr, "Too big VM id\n");
- return NULL;
- }
-
-#define HAX_VM_DEVFS "/dev/hax_vm/vmxx"
- name = g_strdup(HAX_VM_DEVFS);
- if (!name) {
- return NULL;
- }
-
- snprintf(name, sizeof HAX_VM_DEVFS, "/dev/hax_vm/vm%02d", vm_id);
- return name;
+ return g_strdup_printf("/dev/hax_vm/vm%02d", vm_id);
}
static char *hax_vcpu_devfs_string(int vm_id, int vcpu_id)
{
- char *name;
-
- if (vm_id > MAX_VM_ID || vcpu_id > MAX_VCPU_ID) {
- fprintf(stderr, "Too big vm id %x or vcpu id %x\n", vm_id, vcpu_id);
- return NULL;
- }
-
-#define HAX_VCPU_DEVFS "/dev/hax_vmxx/vcpuxx"
- name = g_strdup(HAX_VCPU_DEVFS);
- if (!name) {
- return NULL;
- }
-
- snprintf(name, sizeof HAX_VCPU_DEVFS, "/dev/hax_vm%02d/vcpu%02d",
- vm_id, vcpu_id);
- return name;
+ return g_strdup_printf("/dev/hax_vm%02d/vcpu%02d", vm_id, vcpu_id);
}
int hax_host_create_vm(struct hax_state *hax, int *vmid)
diff --git a/target/i386/hax-windows.c b/target/i386/hax-windows.c
index 5729ad9..0ba488c 100644
--- a/target/i386/hax-windows.c
+++ b/target/i386/hax-windows.c
@@ -185,41 +185,12 @@
static char *hax_vm_devfs_string(int vm_id)
{
- char *name;
-
- if (vm_id > MAX_VM_ID) {
- fprintf(stderr, "Too big VM id\n");
- return NULL;
- }
-
-#define HAX_VM_DEVFS "\\\\.\\hax_vmxx"
- name = g_strdup(HAX_VM_DEVFS);
- if (!name) {
- return NULL;
- }
-
- snprintf(name, sizeof HAX_VM_DEVFS, "\\\\.\\hax_vm%02d", vm_id);
- return name;
+ return g_strdup_printf("/dev/hax_vm/vm%02d", vm_id);
}
static char *hax_vcpu_devfs_string(int vm_id, int vcpu_id)
{
- char *name;
-
- if (vm_id > MAX_VM_ID || vcpu_id > MAX_VCPU_ID) {
- fprintf(stderr, "Too big vm id %x or vcpu id %x\n", vm_id, vcpu_id);
- return NULL;
- }
-
-#define HAX_VCPU_DEVFS "\\\\.\\hax_vmxx_vcpuxx"
- name = g_strdup(HAX_VCPU_DEVFS);
- if (!name) {
- return NULL;
- }
-
- snprintf(name, sizeof HAX_VCPU_DEVFS, "\\\\.\\hax_vm%02d_vcpu%02d",
- vm_id, vcpu_id);
- return name;
+ return g_strdup_printf("/dev/hax_vm%02d/vcpu%02d", vm_id, vcpu_id);
}
int hax_host_create_vm(struct hax_state *hax, int *vmid)
diff --git a/target/i386/sev.c b/target/i386/sev.c
index 024bb24..846018a 100644
--- a/target/i386/sev.c
+++ b/target/i386/sev.c
@@ -267,109 +267,21 @@
}
static void
-qsev_guest_set_handle(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- QSevGuestInfo *sev = QSEV_GUEST_INFO(obj);
- uint32_t value;
-
- visit_type_uint32(v, name, &value, errp);
- sev->handle = value;
-}
-
-static void
-qsev_guest_set_policy(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- QSevGuestInfo *sev = QSEV_GUEST_INFO(obj);
- uint32_t value;
-
- visit_type_uint32(v, name, &value, errp);
- sev->policy = value;
-}
-
-static void
-qsev_guest_set_cbitpos(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- QSevGuestInfo *sev = QSEV_GUEST_INFO(obj);
- uint32_t value;
-
- visit_type_uint32(v, name, &value, errp);
- sev->cbitpos = value;
-}
-
-static void
-qsev_guest_set_reduced_phys_bits(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- QSevGuestInfo *sev = QSEV_GUEST_INFO(obj);
- uint32_t value;
-
- visit_type_uint32(v, name, &value, errp);
- sev->reduced_phys_bits = value;
-}
-
-static void
-qsev_guest_get_policy(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- uint32_t value;
- QSevGuestInfo *sev = QSEV_GUEST_INFO(obj);
-
- value = sev->policy;
- visit_type_uint32(v, name, &value, errp);
-}
-
-static void
-qsev_guest_get_handle(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- uint32_t value;
- QSevGuestInfo *sev = QSEV_GUEST_INFO(obj);
-
- value = sev->handle;
- visit_type_uint32(v, name, &value, errp);
-}
-
-static void
-qsev_guest_get_cbitpos(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- uint32_t value;
- QSevGuestInfo *sev = QSEV_GUEST_INFO(obj);
-
- value = sev->cbitpos;
- visit_type_uint32(v, name, &value, errp);
-}
-
-static void
-qsev_guest_get_reduced_phys_bits(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- uint32_t value;
- QSevGuestInfo *sev = QSEV_GUEST_INFO(obj);
-
- value = sev->reduced_phys_bits;
- visit_type_uint32(v, name, &value, errp);
-}
-
-static void
qsev_guest_init(Object *obj)
{
QSevGuestInfo *sev = QSEV_GUEST_INFO(obj);
sev->sev_device = g_strdup(DEFAULT_SEV_DEVICE);
sev->policy = DEFAULT_GUEST_POLICY;
- object_property_add(obj, "policy", "uint32", qsev_guest_get_policy,
- qsev_guest_set_policy, NULL, NULL, NULL);
- object_property_add(obj, "handle", "uint32", qsev_guest_get_handle,
- qsev_guest_set_handle, NULL, NULL, NULL);
- object_property_add(obj, "cbitpos", "uint32", qsev_guest_get_cbitpos,
- qsev_guest_set_cbitpos, NULL, NULL, NULL);
- object_property_add(obj, "reduced-phys-bits", "uint32",
- qsev_guest_get_reduced_phys_bits,
- qsev_guest_set_reduced_phys_bits, NULL, NULL, NULL);
+ object_property_add_uint32_ptr(obj, "policy", &sev->policy,
+ OBJ_PROP_FLAG_READWRITE, NULL);
+ object_property_add_uint32_ptr(obj, "handle", &sev->handle,
+ OBJ_PROP_FLAG_READWRITE, NULL);
+ object_property_add_uint32_ptr(obj, "cbitpos", &sev->cbitpos,
+ OBJ_PROP_FLAG_READWRITE, NULL);
+ object_property_add_uint32_ptr(obj, "reduced-phys-bits",
+ &sev->reduced_phys_bits,
+ OBJ_PROP_FLAG_READWRITE, NULL);
}
/* sev guest info */
diff --git a/target/i386/whp-dispatch.h b/target/i386/whp-dispatch.h
index 87d049c..e4695c3 100644
--- a/target/i386/whp-dispatch.h
+++ b/target/i386/whp-dispatch.h
@@ -23,6 +23,12 @@
X(HRESULT, WHvGetVirtualProcessorRegisters, (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, const WHV_REGISTER_NAME* RegisterNames, UINT32 RegisterCount, WHV_REGISTER_VALUE* RegisterValues)) \
X(HRESULT, WHvSetVirtualProcessorRegisters, (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, const WHV_REGISTER_NAME* RegisterNames, UINT32 RegisterCount, const WHV_REGISTER_VALUE* RegisterValues)) \
+/*
+ * These are supplemental functions that may not be present
+ * on all versions and are not critical for basic functionality.
+ */
+#define LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(X) \
+ X(HRESULT, WHvSuspendPartitionTime, (WHV_PARTITION_HANDLE Partition)) \
#define LIST_WINHVEMULATION_FUNCTIONS(X) \
X(HRESULT, WHvEmulatorCreateEmulator, (const WHV_EMULATOR_CALLBACKS* Callbacks, WHV_EMULATOR_HANDLE* Emulator)) \
@@ -40,10 +46,12 @@
/* Define function typedef */
LIST_WINHVPLATFORM_FUNCTIONS(WHP_DEFINE_TYPE)
LIST_WINHVEMULATION_FUNCTIONS(WHP_DEFINE_TYPE)
+LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_DEFINE_TYPE)
struct WHPDispatch {
LIST_WINHVPLATFORM_FUNCTIONS(WHP_DECLARE_MEMBER)
LIST_WINHVEMULATION_FUNCTIONS(WHP_DECLARE_MEMBER)
+ LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_DECLARE_MEMBER)
};
extern struct WHPDispatch whp_dispatch;
@@ -53,6 +61,7 @@
typedef enum WHPFunctionList {
WINHV_PLATFORM_FNS_DEFAULT,
WINHV_EMULATION_FNS_DEFAULT,
+ WINHV_PLATFORM_FNS_SUPPLEMENTAL
} WHPFunctionList;
#endif /* WHP_DISPATCH_H */
diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c
index 683d49d..c78baac 100644
--- a/target/i386/whpx-all.c
+++ b/target/i386/whpx-all.c
@@ -114,7 +114,6 @@
WHvX64RegisterXmmControlStatus,
/* X64 MSRs */
- WHvX64RegisterTsc,
WHvX64RegisterEfer,
#ifdef TARGET_X86_64
WHvX64RegisterKernelGsBase,
@@ -215,7 +214,44 @@
return qs;
}
-static void whpx_set_registers(CPUState *cpu)
+static int whpx_set_tsc(CPUState *cpu)
+{
+ struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
+ WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
+ WHV_REGISTER_VALUE tsc_val;
+ HRESULT hr;
+ struct whpx_state *whpx = &whpx_global;
+
+ /*
+ * Suspend the partition prior to setting the TSC to reduce the variance
+ * in TSC across vCPUs. When the first vCPU runs post suspend, the
+ * partition is automatically resumed.
+ */
+ if (whp_dispatch.WHvSuspendPartitionTime) {
+
+ /*
+ * Unable to suspend partition while setting TSC is not a fatal
+ * error. It just increases the likelihood of TSC variance between
+ * vCPUs and some guest OS are able to handle that just fine.
+ */
+ hr = whp_dispatch.WHvSuspendPartitionTime(whpx->partition);
+ if (FAILED(hr)) {
+ warn_report("WHPX: Failed to suspend partition, hr=%08lx", hr);
+ }
+ }
+
+ tsc_val.Reg64 = env->tsc;
+ hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
+ whpx->partition, cpu->cpu_index, &tsc_reg, 1, &tsc_val);
+ if (FAILED(hr)) {
+ error_report("WHPX: Failed to set TSC, hr=%08lx", hr);
+ return -1;
+ }
+
+ return 0;
+}
+
+static void whpx_set_registers(CPUState *cpu, int level)
{
struct whpx_state *whpx = &whpx_global;
struct whpx_vcpu *vcpu = get_whpx_vcpu(cpu);
@@ -230,6 +266,14 @@
assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
+ /*
+ * Following MSRs have side effects on the guest or are too heavy for
+ * runtime. Limit them to full state update.
+ */
+ if (level >= WHPX_SET_RESET_STATE) {
+ whpx_set_tsc(cpu);
+ }
+
memset(&vcxt, 0, sizeof(struct whpx_register_set));
v86 = (env->eflags & VM_MASK);
@@ -330,8 +374,6 @@
idx += 1;
/* MSRs */
- assert(whpx_register_names[idx] == WHvX64RegisterTsc);
- vcxt.values[idx++].Reg64 = env->tsc;
assert(whpx_register_names[idx] == WHvX64RegisterEfer);
vcxt.values[idx++].Reg64 = env->efer;
#ifdef TARGET_X86_64
@@ -379,6 +421,25 @@
return;
}
+static int whpx_get_tsc(CPUState *cpu)
+{
+ struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
+ WHV_REGISTER_NAME tsc_reg = WHvX64RegisterTsc;
+ WHV_REGISTER_VALUE tsc_val;
+ HRESULT hr;
+ struct whpx_state *whpx = &whpx_global;
+
+ hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
+ whpx->partition, cpu->cpu_index, &tsc_reg, 1, &tsc_val);
+ if (FAILED(hr)) {
+ error_report("WHPX: Failed to get TSC, hr=%08lx", hr);
+ return -1;
+ }
+
+ env->tsc = tsc_val.Reg64;
+ return 0;
+}
+
static void whpx_get_registers(CPUState *cpu)
{
struct whpx_state *whpx = &whpx_global;
@@ -394,6 +455,11 @@
assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
+ if (!env->tsc_valid) {
+ whpx_get_tsc(cpu);
+ env->tsc_valid = !runstate_is_running();
+ }
+
hr = whp_dispatch.WHvGetVirtualProcessorRegisters(
whpx->partition, cpu->cpu_index,
whpx_register_names,
@@ -492,8 +558,6 @@
idx += 1;
/* MSRs */
- assert(whpx_register_names[idx] == WHvX64RegisterTsc);
- env->tsc = vcxt.values[idx++].Reg64;
assert(whpx_register_names[idx] == WHvX64RegisterEfer);
env->efer = vcxt.values[idx++].Reg64;
#ifdef TARGET_X86_64
@@ -841,9 +905,8 @@
if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
!(env->hflags & HF_SMM_MASK)) {
-
+ whpx_cpu_synchronize_state(cpu);
do_cpu_init(x86_cpu);
- cpu->vcpu_dirty = true;
vcpu->interruptable = true;
}
@@ -859,17 +922,13 @@
}
if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) {
- if (!cpu->vcpu_dirty) {
- whpx_get_registers(cpu);
- }
+ whpx_cpu_synchronize_state(cpu);
do_cpu_sipi(x86_cpu);
}
if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
cpu->interrupt_request &= ~CPU_INTERRUPT_TPR;
- if (!cpu->vcpu_dirty) {
- whpx_get_registers(cpu);
- }
+ whpx_cpu_synchronize_state(cpu);
apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip,
env->tpr_access_type);
}
@@ -896,7 +955,7 @@
do {
if (cpu->vcpu_dirty) {
- whpx_set_registers(cpu);
+ whpx_set_registers(cpu, WHPX_SET_RUNTIME_STATE);
cpu->vcpu_dirty = false;
}
@@ -980,38 +1039,32 @@
WHV_REGISTER_VALUE reg_values[5];
WHV_REGISTER_NAME reg_names[5];
UINT32 reg_count = 5;
- UINT64 rip, rax, rcx, rdx, rbx;
+ UINT64 cpuid_fn, rip = 0, rax = 0, rcx = 0, rdx = 0, rbx = 0;
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
memset(reg_values, 0, sizeof(reg_values));
rip = vcpu->exit_ctx.VpContext.Rip +
vcpu->exit_ctx.VpContext.InstructionLength;
- switch (vcpu->exit_ctx.CpuidAccess.Rax) {
- case 1:
- rax = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
- /* Advertise that we are running on a hypervisor */
- rcx =
- vcpu->exit_ctx.CpuidAccess.DefaultResultRcx |
- CPUID_EXT_HYPERVISOR;
+ cpuid_fn = vcpu->exit_ctx.CpuidAccess.Rax;
- rdx = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
- rbx = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
- break;
+ /*
+ * Ideally, these should be supplied to the hypervisor during VCPU
+ * initialization and it should be able to satisfy this request.
+ * But, currently, WHPX doesn't support setting CPUID values in the
+ * hypervisor once the partition has been setup, which is too late
+ * since VCPUs are realized later. For now, use the values from
+ * QEMU to satisfy these requests, until WHPX adds support for
+ * being able to set these values in the hypervisor at runtime.
+ */
+ cpu_x86_cpuid(env, cpuid_fn, 0, (UINT32 *)&rax, (UINT32 *)&rbx,
+ (UINT32 *)&rcx, (UINT32 *)&rdx);
+ switch (cpuid_fn) {
case 0x80000001:
- rax = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
/* Remove any support of OSVW */
- rcx =
- vcpu->exit_ctx.CpuidAccess.DefaultResultRcx &
- ~CPUID_EXT3_OSVW;
-
- rdx = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
- rbx = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
+ rcx &= ~CPUID_EXT3_OSVW;
break;
- default:
- rax = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
- rcx = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;
- rdx = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
- rbx = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
}
reg_names[0] = WHvX64RegisterRip;
@@ -1067,21 +1120,23 @@
static void do_whpx_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
{
- whpx_get_registers(cpu);
- cpu->vcpu_dirty = true;
+ if (!cpu->vcpu_dirty) {
+ whpx_get_registers(cpu);
+ cpu->vcpu_dirty = true;
+ }
}
static void do_whpx_cpu_synchronize_post_reset(CPUState *cpu,
run_on_cpu_data arg)
{
- whpx_set_registers(cpu);
+ whpx_set_registers(cpu, WHPX_SET_RESET_STATE);
cpu->vcpu_dirty = false;
}
static void do_whpx_cpu_synchronize_post_init(CPUState *cpu,
run_on_cpu_data arg)
{
- whpx_set_registers(cpu);
+ whpx_set_registers(cpu, WHPX_SET_FULL_STATE);
cpu->vcpu_dirty = false;
}
@@ -1123,6 +1178,15 @@
static Error *whpx_migration_blocker;
+static void whpx_cpu_update_state(void *opaque, int running, RunState state)
+{
+ CPUX86State *env = opaque;
+
+ if (running) {
+ env->tsc_valid = false;
+ }
+}
+
int whpx_init_vcpu(CPUState *cpu)
{
HRESULT hr;
@@ -1178,6 +1242,7 @@
cpu->vcpu_dirty = true;
cpu->hax_vcpu = (struct hax_vcpu_state *)vcpu;
+ qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr);
return 0;
}
@@ -1367,6 +1432,10 @@
#define WINHV_PLATFORM_DLL "WinHvPlatform.dll"
#define WINHV_EMULATION_DLL "WinHvEmulation.dll"
+ #define WHP_LOAD_FIELD_OPTIONAL(return_type, function_name, signature) \
+ whp_dispatch.function_name = \
+ (function_name ## _t)GetProcAddress(hLib, #function_name); \
+
#define WHP_LOAD_FIELD(return_type, function_name, signature) \
whp_dispatch.function_name = \
(function_name ## _t)GetProcAddress(hLib, #function_name); \
@@ -1394,6 +1463,11 @@
WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib)
LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD)
break;
+
+ case WINHV_PLATFORM_FNS_SUPPLEMENTAL:
+ WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib)
+ LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_LOAD_FIELD_OPTIONAL)
+ break;
}
*handle = hLib;
@@ -1554,6 +1628,8 @@
goto error;
}
+ assert(load_whp_dispatch_fns(&hWinHvPlatform,
+ WINHV_PLATFORM_FNS_SUPPLEMENTAL));
whp_dispatch_initialized = true;
return true;
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 064c6b1..01d408e 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -202,7 +202,7 @@
bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req);
void lm32_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int lm32_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
typedef enum {
diff --git a/target/lm32/gdbstub.c b/target/lm32/gdbstub.c
index 82ede43..b6fe12e 100644
--- a/target/lm32/gdbstub.c
+++ b/target/lm32/gdbstub.c
@@ -22,7 +22,7 @@
#include "exec/gdbstub.h"
#include "hw/lm32/lm32_pic.h"
-int lm32_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int lm32_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
LM32CPU *cpu = LM32_CPU(cs);
CPULM32State *env = &cpu->env;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 3de8e06..521ac67 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -168,7 +168,7 @@
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void m68k_tcg_init(void);
diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c
index fdc96f5..eb2d030 100644
--- a/target/m68k/gdbstub.c
+++ b/target/m68k/gdbstub.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/gdbstub.h"
-int m68k_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
M68kCPU *cpu = M68K_CPU(cs);
CPUM68KState *env = &cpu->env;
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index baf7729..014657c 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -68,23 +68,19 @@
g_slist_free(list);
}
-static int cf_fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
+static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)
{
if (n < 8) {
float_status s;
- stfq_p(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
- return 8;
+ return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
}
switch (n) {
case 8: /* fpcontrol */
- stl_be_p(mem_buf, env->fpcr);
- return 4;
+ return gdb_get_reg32(mem_buf, env->fpcr);
case 9: /* fpstatus */
- stl_be_p(mem_buf, env->fpsr);
- return 4;
+ return gdb_get_reg32(mem_buf, env->fpsr);
case 10: /* fpiar, not implemented */
- memset(mem_buf, 0, 4);
- return 4;
+ return gdb_get_reg32(mem_buf, 0);
}
return 0;
}
@@ -109,24 +105,21 @@
return 0;
}
-static int m68k_fpu_gdb_get_reg(CPUM68KState *env, uint8_t *mem_buf, int n)
+static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)
{
if (n < 8) {
- stw_be_p(mem_buf, env->fregs[n].l.upper);
- memset(mem_buf + 2, 0, 2);
- stq_be_p(mem_buf + 4, env->fregs[n].l.lower);
- return 12;
+ int len = gdb_get_reg16(mem_buf, env->fregs[n].l.upper);
+ len += gdb_get_reg16(mem_buf + len, 0);
+ len += gdb_get_reg64(mem_buf + len, env->fregs[n].l.lower);
+ return len;
}
switch (n) {
case 8: /* fpcontrol */
- stl_be_p(mem_buf, env->fpcr);
- return 4;
+ return gdb_get_reg32(mem_buf, env->fpcr);
case 9: /* fpstatus */
- stl_be_p(mem_buf, env->fpsr);
- return 4;
+ return gdb_get_reg32(mem_buf, env->fpsr);
case 10: /* fpiar, not implemented */
- memset(mem_buf, 0, 4);
- return 4;
+ return gdb_get_reg32(mem_buf, 0);
}
return 0;
}
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 32522f6..1a700a8 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -313,7 +313,7 @@
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void mb_tcg_init(void);
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 30677b6..f41ebf1 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/gdbstub.h"
-int mb_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUMBState *env = &cpu->env;
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index bbb2544..98f56e6 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -22,7 +22,7 @@
#include "internal.h"
#include "exec/gdbstub.h"
-int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index df55f84..1bf274b 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -82,7 +82,7 @@
bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 1c0c855..1856b7f 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -124,7 +124,7 @@
#endif
}
-static int nios2_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUClass *cc = CPU_GET_CLASS(cs);
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 0ad02ea..d9484b8 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -320,7 +320,7 @@
bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void openrisc_translate_init(void);
bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c
index 0fcdb79..095bf76 100644
--- a/target/openrisc/gdbstub.c
+++ b/target/openrisc/gdbstub.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/gdbstub.h"
-int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index e499575..15d6b54 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -177,6 +177,7 @@
uint64_t insns_flags;
uint64_t insns_flags2;
uint64_t msr_mask;
+ uint64_t lpcr_mask; /* Available bits in the LPCR */
uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b283042..88d9449 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -24,8 +24,6 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
-/* #define PPC_EMULATE_32BITS_HYPV */
-
#define TCG_GUEST_DEFAULT_MO 0
#define TARGET_PAGE_BITS_64K 16
@@ -300,13 +298,12 @@
#define MSR_SF 63 /* Sixty-four-bit mode hflags */
#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
-#define MSR_SHV 60 /* hypervisor state hflags */
+#define MSR_HV 60 /* hypervisor state hflags */
#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
#define MSR_TS1 33
#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
#define MSR_CM 31 /* Computation mode for BookE hflags */
#define MSR_ICM 30 /* Interrupt computation mode for BookE */
-#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
#define MSR_GS 28 /* guest state for BookE */
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
#define MSR_VR 25 /* altivec available x hflags */
@@ -401,10 +398,13 @@
#define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1)
-#define msr_shv ((env->msr >> MSR_SHV) & 1)
+#if defined(TARGET_PPC64)
+#define msr_hv ((env->msr >> MSR_HV) & 1)
+#else
+#define msr_hv (0)
+#endif
#define msr_cm ((env->msr >> MSR_CM) & 1)
#define msr_icm ((env->msr >> MSR_ICM) & 1)
-#define msr_thv ((env->msr >> MSR_THV) & 1)
#define msr_gs ((env->msr >> MSR_GS) & 1)
#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
#define msr_vr ((env->msr >> MSR_VR) & 1)
@@ -449,16 +449,9 @@
/* Hypervisor bit is more specific */
#if defined(TARGET_PPC64)
-#define MSR_HVB (1ULL << MSR_SHV)
-#define msr_hv msr_shv
-#else
-#if defined(PPC_EMULATE_32BITS_HYPV)
-#define MSR_HVB (1ULL << MSR_THV)
-#define msr_hv msr_thv
+#define MSR_HVB (1ULL << MSR_HV)
#else
#define MSR_HVB (0ULL)
-#define msr_hv (0)
-#endif
#endif
/* DSISR */
@@ -1051,10 +1044,6 @@
uint32_t flags;
uint64_t insns_flags;
uint64_t insns_flags2;
-#if defined(TARGET_PPC64)
- ppc_slb_t vrma_slb;
- target_ulong rmls;
-#endif
int error_code;
uint32_t pending_interrupts;
@@ -1218,8 +1207,8 @@
void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
void ppc_cpu_dump_statistics(CPUState *cpu, int flags);
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
-int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
+int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
+int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
#ifndef CONFIG_USER_ONLY
@@ -1231,7 +1220,8 @@
int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque);
#ifndef CONFIG_USER_ONLY
-void ppc_cpu_do_system_reset(CPUState *cs);
+void ppc_cpu_do_system_reset(CPUState *cs, target_ulong vector);
+void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
extern const VMStateDescription vmstate_ppc_cpu;
#endif
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 027f54c..08bc885 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -128,6 +128,37 @@
return offset;
}
+static inline void powerpc_set_excp_state(PowerPCCPU *cpu,
+ target_ulong vector, target_ulong msr)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+
+ /*
+ * We don't use hreg_store_msr here as already have treated any
+ * special case that could occur. Just store MSR and update hflags
+ *
+ * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
+ * will prevent setting of the HV bit which some exceptions might need
+ * to do.
+ */
+ env->msr = msr & env->msr_mask;
+ hreg_compute_hflags(env);
+ env->nip = vector;
+ /* Reset exception state */
+ cs->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+
+ /* Reset the reservation */
+ env->reserve_addr = -1;
+
+ /*
+ * Any interrupt is context synchronizing, check if TCG TLB needs
+ * a delayed flush on ppc64
+ */
+ check_tlb_flush(env, false);
+}
+
/*
* Note that this function should be greatly optimized when called
* with a constant excp, from ppc_hw_interrupt
@@ -768,29 +799,8 @@
}
}
#endif
- /*
- * We don't use hreg_store_msr here as already have treated any
- * special case that could occur. Just store MSR and update hflags
- *
- * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
- * will prevent setting of the HV bit which some exceptions might need
- * to do.
- */
- env->msr = new_msr & env->msr_mask;
- hreg_compute_hflags(env);
- env->nip = vector;
- /* Reset exception state */
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
- /* Reset the reservation */
- env->reserve_addr = -1;
-
- /*
- * Any interrupt is context synchronizing, check if TCG TLB needs
- * a delayed flush on ppc64
- */
- check_tlb_flush(env, false);
+ powerpc_set_excp_state(cpu, vector, new_msr);
}
void ppc_cpu_do_interrupt(CPUState *cs)
@@ -951,12 +961,35 @@
}
}
-void ppc_cpu_do_system_reset(CPUState *cs)
+void ppc_cpu_do_system_reset(CPUState *cs, target_ulong vector)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
+ if (vector != -1) {
+ env->nip = vector;
+ }
+}
+
+void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ target_ulong msr = 0;
+
+ /*
+ * Set MSR and NIP for the handler, SRR0/1, DAR and DSISR have already
+ * been set by KVM.
+ */
+ msr = (1ULL << MSR_ME);
+ msr |= env->msr & (1ULL << MSR_SF);
+ if (!(*pcc->interrupts_big_endian)(cpu)) {
+ msr |= (1ULL << MSR_LE);
+ }
+
+ powerpc_set_excp_state(cpu, vector, msr);
}
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 823759c..eb362dd 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -114,10 +114,11 @@
* the FP regs zero size when talking to a newer gdb.
*/
-int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
+ uint8_t *mem_buf;
int r = ppc_gdb_register_len(n);
if (!r) {
@@ -126,17 +127,17 @@
if (n < 32) {
/* gprs */
- gdb_get_regl(mem_buf, env->gpr[n]);
+ gdb_get_regl(buf, env->gpr[n]);
} else if (n < 64) {
/* fprs */
- stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32));
+ gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32));
} else {
switch (n) {
case 64:
- gdb_get_regl(mem_buf, env->nip);
+ gdb_get_regl(buf, env->nip);
break;
case 65:
- gdb_get_regl(mem_buf, env->msr);
+ gdb_get_regl(buf, env->msr);
break;
case 66:
{
@@ -145,31 +146,33 @@
for (i = 0; i < 8; i++) {
cr |= env->crf[i] << (32 - ((i + 1) * 4));
}
- gdb_get_reg32(mem_buf, cr);
+ gdb_get_reg32(buf, cr);
break;
}
case 67:
- gdb_get_regl(mem_buf, env->lr);
+ gdb_get_regl(buf, env->lr);
break;
case 68:
- gdb_get_regl(mem_buf, env->ctr);
+ gdb_get_regl(buf, env->ctr);
break;
case 69:
- gdb_get_reg32(mem_buf, env->xer);
+ gdb_get_reg32(buf, env->xer);
break;
case 70:
- gdb_get_reg32(mem_buf, env->fpscr);
+ gdb_get_reg32(buf, env->fpscr);
break;
}
}
+ mem_buf = buf->data + buf->len - r;
ppc_maybe_bswap_register(env, mem_buf, r);
return r;
}
-int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
+int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
+ uint8_t *mem_buf;
int r = ppc_gdb_register_len_apple(n);
if (!r) {
@@ -178,21 +181,21 @@
if (n < 32) {
/* gprs */
- gdb_get_reg64(mem_buf, env->gpr[n]);
+ gdb_get_reg64(buf, env->gpr[n]);
} else if (n < 64) {
/* fprs */
- stfq_p(mem_buf, *cpu_fpr_ptr(env, n - 32));
+ gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32));
} else if (n < 96) {
/* Altivec */
- stq_p(mem_buf, n - 64);
- stq_p(mem_buf + 8, 0);
+ gdb_get_reg64(buf, n - 64);
+ gdb_get_reg64(buf, 0);
} else {
switch (n) {
case 64 + 32:
- gdb_get_reg64(mem_buf, env->nip);
+ gdb_get_reg64(buf, env->nip);
break;
case 65 + 32:
- gdb_get_reg64(mem_buf, env->msr);
+ gdb_get_reg64(buf, env->msr);
break;
case 66 + 32:
{
@@ -201,23 +204,24 @@
for (i = 0; i < 8; i++) {
cr |= env->crf[i] << (32 - ((i + 1) * 4));
}
- gdb_get_reg32(mem_buf, cr);
+ gdb_get_reg32(buf, cr);
break;
}
case 67 + 32:
- gdb_get_reg64(mem_buf, env->lr);
+ gdb_get_reg64(buf, env->lr);
break;
case 68 + 32:
- gdb_get_reg64(mem_buf, env->ctr);
+ gdb_get_reg64(buf, env->ctr);
break;
case 69 + 32:
- gdb_get_reg32(mem_buf, env->xer);
+ gdb_get_reg32(buf, env->xer);
break;
case 70 + 32:
- gdb_get_reg64(mem_buf, env->fpscr);
+ gdb_get_reg64(buf, env->fpscr);
break;
}
}
+ mem_buf = buf->data + buf->len - r;
ppc_maybe_bswap_register(env, mem_buf, r);
return r;
}
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 7f44b1a..597f72b 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2113,7 +2113,7 @@
#ifdef TARGET_PPC64
-uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
+uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
{
struct kvm_ppc_smmu_info info;
long rampagesize, best_page_shift;
@@ -2140,8 +2140,7 @@
}
}
- return MIN(current_size,
- 1ULL << (best_page_shift + hash_shift - 7));
+ return 1ULL << (best_page_shift + hash_shift - 7);
}
#endif
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index 9e4f235..332fa0a 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -47,7 +47,7 @@
int *pfd, bool need_vfio);
int kvmppc_remove_spapr_tce(void *table, int pfd, uint32_t window_size);
int kvmppc_reset_htab(int shift_hint);
-uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift);
+uint64_t kvmppc_vrma_limit(unsigned int hash_shift);
bool kvmppc_has_cap_spapr_vfio(void);
#endif /* !CONFIG_USER_ONLY */
bool kvmppc_has_cap_epr(void);
@@ -255,10 +255,9 @@
return 0;
}
-static inline uint64_t kvmppc_rma_size(uint64_t current_size,
- unsigned int hash_shift)
+static inline uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
{
- return ram_size;
+ g_assert_not_reached();
}
static inline bool kvmppc_hpt_needs_host_contiguous_pages(void)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index da8966c..34f6009 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -18,6 +18,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
@@ -668,6 +669,21 @@
return 0;
}
+static bool ppc_hash64_use_vrma(CPUPPCState *env)
+{
+ switch (env->mmu_model) {
+ case POWERPC_MMU_3_00:
+ /*
+ * ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR
+ * register no longer exist
+ */
+ return true;
+
+ default:
+ return !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ }
+}
+
static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code)
{
CPUPPCState *env = &POWERPC_CPU(cs)->env;
@@ -676,15 +692,7 @@
if (msr_ir) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- switch (env->mmu_model) {
- case POWERPC_MMU_3_00:
- /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
- vpm = true;
- break;
- default:
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
- break;
- }
+ vpm = ppc_hash64_use_vrma(env);
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HISI;
@@ -702,15 +710,7 @@
if (msr_dr) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- switch (env->mmu_model) {
- case POWERPC_MMU_3_00:
- /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
- vpm = true;
- break;
- default:
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
- break;
- }
+ vpm = ppc_hash64_use_vrma(env);
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HDSI;
@@ -758,11 +758,67 @@
stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
}
+static target_ulong rmls_limit(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+ /*
+ * In theory the meanings of RMLS values are implementation
+ * dependent. In practice, this seems to have been the set from
+ * POWER4+..POWER8, and RMLS is no longer supported in POWER9.
+ *
+ * Unsupported values mean the OS has shot itself in the
+ * foot. Return a 0-sized RMA in this case, which we expect
+ * to trigger an immediate DSI or ISI
+ */
+ static const target_ulong rma_sizes[16] = {
+ [0] = 256 * GiB,
+ [1] = 16 * GiB,
+ [2] = 1 * GiB,
+ [3] = 64 * MiB,
+ [4] = 256 * MiB,
+ [7] = 128 * MiB,
+ [8] = 32 * MiB,
+ };
+ target_ulong rmls = (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SHIFT;
+
+ return rma_sizes[rmls];
+}
+
+static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong lpcr = env->spr[SPR_LPCR];
+ uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
+ target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK);
+ int i;
+
+ for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
+ const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i];
+
+ if (!sps->page_shift) {
+ break;
+ }
+
+ if ((vsid & SLB_VSID_LLP_MASK) == sps->slb_enc) {
+ slb->esid = SLB_ESID_V;
+ slb->vsid = vsid;
+ slb->sps = sps;
+ return 0;
+ }
+ }
+
+ error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
+ TARGET_FMT_lx"\n", lpcr);
+
+ return -1;
+}
+
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
int rwx, int mmu_idx)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ ppc_slb_t vrma_slbe;
ppc_slb_t *slb;
unsigned apshift;
hwaddr ptex;
@@ -789,27 +845,32 @@
*/
raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
- /* In HV mode, add HRMOR if top EA bit is clear */
- if (msr_hv || !env->has_hv_mode) {
+ if (cpu->vhyp) {
+ /*
+ * In virtual hypervisor mode, there's nothing to do:
+ * EA == GPA == qemu guest address
+ */
+ } else if (msr_hv || !env->has_hv_mode) {
+ /* In HV mode, add HRMOR if top EA bit is clear */
if (!(eaddr >> 63)) {
raddr |= env->spr[SPR_HRMOR];
}
- } else {
- /* Otherwise, check VPM for RMA vs VRMA */
- if (env->spr[SPR_LPCR] & LPCR_VPM0) {
- slb = &env->vrma_slb;
- if (slb->sps) {
- goto skip_slb_search;
- }
- /* Not much else to do here */
+ } else if (ppc_hash64_use_vrma(env)) {
+ /* Emulated VRMA mode */
+ slb = &vrma_slbe;
+ if (build_vrma_slbe(cpu, slb) != 0) {
+ /* Invalid VRMA setup, machine check */
cs->exception_index = POWERPC_EXCP_MCHECK;
env->error_code = 0;
return 1;
- } else if (raddr < env->rmls) {
- /* RMA. Check bounds in RMLS */
- raddr |= env->spr[SPR_RMOR];
- } else {
- /* The access failed, generate the approriate interrupt */
+ }
+
+ goto skip_slb_search;
+ } else {
+ target_ulong limit = rmls_limit(cpu);
+
+ /* Emulated old-style RMO mode, bounds check against RMLS */
+ if (raddr >= limit) {
if (rwx == 2) {
ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
} else {
@@ -821,6 +882,8 @@
}
return 1;
}
+
+ raddr |= env->spr[SPR_RMOR];
}
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
@@ -943,6 +1006,7 @@
hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
{
CPUPPCState *env = &cpu->env;
+ ppc_slb_t vrma_slbe;
ppc_slb_t *slb;
hwaddr ptex, raddr;
ppc_hash_pte64_t pte;
@@ -953,22 +1017,29 @@
/* In real mode the top 4 effective address bits are ignored */
raddr = addr & 0x0FFFFFFFFFFFFFFFULL;
- /* In HV mode, add HRMOR if top EA bit is clear */
- if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) {
+ if (cpu->vhyp) {
+ /*
+ * In virtual hypervisor mode, there's nothing to do:
+ * EA == GPA == qemu guest address
+ */
+ return raddr;
+ } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) {
+ /* In HV mode, add HRMOR if top EA bit is clear */
return raddr | env->spr[SPR_HRMOR];
- }
-
- /* Otherwise, check VPM for RMA vs VRMA */
- if (env->spr[SPR_LPCR] & LPCR_VPM0) {
- slb = &env->vrma_slb;
- if (!slb->sps) {
+ } else if (ppc_hash64_use_vrma(env)) {
+ /* Emulated VRMA mode */
+ slb = &vrma_slbe;
+ if (build_vrma_slbe(cpu, slb) != 0) {
return -1;
}
- } else if (raddr < env->rmls) {
- /* RMA. Check bounds in RMLS */
- return raddr | env->spr[SPR_RMOR];
} else {
- return -1;
+ target_ulong limit = rmls_limit(cpu);
+
+ /* Emulated old-style RMO mode, bounds check against RMLS */
+ if (raddr >= limit) {
+ return -1;
+ }
+ return raddr | env->spr[SPR_RMOR];
}
} else {
slb = slb_lookup(cpu, addr);
@@ -997,168 +1068,12 @@
cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
}
-static void ppc_hash64_update_rmls(PowerPCCPU *cpu)
-{
- CPUPPCState *env = &cpu->env;
- uint64_t lpcr = env->spr[SPR_LPCR];
-
- /*
- * This is the full 4 bits encoding of POWER8. Previous
- * CPUs only support a subset of these but the filtering
- * is done when writing LPCR
- */
- switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) {
- case 0x8: /* 32MB */
- env->rmls = 0x2000000ull;
- break;
- case 0x3: /* 64MB */
- env->rmls = 0x4000000ull;
- break;
- case 0x7: /* 128MB */
- env->rmls = 0x8000000ull;
- break;
- case 0x4: /* 256MB */
- env->rmls = 0x10000000ull;
- break;
- case 0x2: /* 1GB */
- env->rmls = 0x40000000ull;
- break;
- case 0x1: /* 16GB */
- env->rmls = 0x400000000ull;
- break;
- default:
- /* What to do here ??? */
- env->rmls = 0;
- }
-}
-
-static void ppc_hash64_update_vrma(PowerPCCPU *cpu)
-{
- CPUPPCState *env = &cpu->env;
- const PPCHash64SegmentPageSizes *sps = NULL;
- target_ulong esid, vsid, lpcr;
- ppc_slb_t *slb = &env->vrma_slb;
- uint32_t vrmasd;
- int i;
-
- /* First clear it */
- slb->esid = slb->vsid = 0;
- slb->sps = NULL;
-
- /* Is VRMA enabled ? */
- lpcr = env->spr[SPR_LPCR];
- if (!(lpcr & LPCR_VPM0)) {
- return;
- }
-
- /*
- * Make one up. Mostly ignore the ESID which will not be needed
- * for translation
- */
- vsid = SLB_VSID_VRMA;
- vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
- vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
- esid = SLB_ESID_V;
-
- for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i];
-
- if (!sps1->page_shift) {
- break;
- }
-
- if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
- sps = sps1;
- break;
- }
- }
-
- if (!sps) {
- error_report("Bad page size encoding esid 0x"TARGET_FMT_lx
- " vsid 0x"TARGET_FMT_lx, esid, vsid);
- return;
- }
-
- slb->vsid = vsid;
- slb->esid = esid;
- slb->sps = sps;
-}
-
void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
- uint64_t lpcr = 0;
- /* Filter out bits */
- switch (env->mmu_model) {
- case POWERPC_MMU_64B: /* 970 */
- if (val & 0x40) {
- lpcr |= LPCR_LPES0;
- }
- if (val & 0x8000000000000000ull) {
- lpcr |= LPCR_LPES1;
- }
- if (val & 0x20) {
- lpcr |= (0x4ull << LPCR_RMLS_SHIFT);
- }
- if (val & 0x4000000000000000ull) {
- lpcr |= (0x2ull << LPCR_RMLS_SHIFT);
- }
- if (val & 0x2000000000000000ull) {
- lpcr |= (0x1ull << LPCR_RMLS_SHIFT);
- }
- env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26;
-
- /*
- * XXX We could also write LPID from HID4 here
- * but since we don't tag any translation on it
- * it doesn't actually matter
- *
- * XXX For proper emulation of 970 we also need
- * to dig HRMOR out of HID5
- */
- break;
- case POWERPC_MMU_2_03: /* P5p */
- lpcr = val & (LPCR_RMLS | LPCR_ILE |
- LPCR_LPES0 | LPCR_LPES1 |
- LPCR_RMI | LPCR_HDICE);
- break;
- case POWERPC_MMU_2_06: /* P7 */
- lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
- LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
- LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
- LPCR_MER | LPCR_TC |
- LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
- break;
- case POWERPC_MMU_2_07: /* P8 */
- lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
- LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
- LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
- LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
- LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
- break;
- case POWERPC_MMU_3_00: /* P9 */
- lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
- (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
- LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
- (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
- LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
- LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
- /*
- * If we have a virtual hypervisor, we need to bring back RMLS. It
- * doesn't exist on an actual P9 but that's all we know how to
- * configure with softmmu at the moment
- */
- if (cpu->vhyp) {
- lpcr |= (val & LPCR_RMLS);
- }
- break;
- default:
- ;
- }
- env->spr[SPR_LPCR] = lpcr;
- ppc_hash64_update_rmls(cpu);
- ppc_hash64_update_vrma(cpu);
+ env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
}
void helper_store_lpcr(CPUPPCState *env, target_ulong val)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 36fa273..127c82a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1938,15 +1938,17 @@
me += 32;
#endif
mask = MASK(mb, me);
- if (sh == 0) {
- tcg_gen_andi_tl(t_ra, t_rs, mask);
- } else if (mask <= 0xffffffffu) {
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t0, t_rs);
- tcg_gen_rotli_i32(t0, t0, sh);
- tcg_gen_andi_i32(t0, t0, mask);
- tcg_gen_extu_i32_tl(t_ra, t0);
- tcg_temp_free_i32(t0);
+ if (mask <= 0xffffffffu) {
+ if (sh == 0) {
+ tcg_gen_andi_tl(t_ra, t_rs, mask);
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, t_rs);
+ tcg_gen_rotli_i32(t0, t0, sh);
+ tcg_gen_andi_i32(t0, t0, mask);
+ tcg_gen_extu_i32_tl(t_ra, t0);
+ tcg_temp_free_i32(t0);
+ }
} else {
#if defined(TARGET_PPC64)
tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 53995f6..997c8b0 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -7895,25 +7895,21 @@
{
gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
}
-
-static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn)
-{
-#if defined(TARGET_PPC64)
- spr_write_generic(ctx, sprn, gprn);
- gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
-#endif
-}
-
#endif /* !defined(CONFIG_USER_ONLY) */
static void gen_spr_970_lpar(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
- /* Logical partitionning */
- /* PPC970: HID4 is effectively the LPCR */
+ /*
+ * PPC970: HID4 covers things later controlled by the LPCR and
+ * RMOR in later CPUs, but with a different encoding. We only
+ * support the 970 in "Apple mode" which has all hypervisor
+ * facilities disabled by strapping, so we can basically just
+ * ignore it
+ */
spr_register(env, SPR_970_HID4, "HID4",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_970_hid4,
+ &spr_read_generic, &spr_write_generic,
0x00000000);
#endif
}
@@ -8019,12 +8015,16 @@
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register_hv(env, SPR_RMOR, "RMOR",
+ spr_register_hv(env, SPR_HRMOR, "HRMOR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register_hv(env, SPR_HRMOR, "HRMOR",
+}
+
+static void gen_spr_rmor(CPUPPCState *env)
+{
+ spr_register_hv(env, SPR_RMOR, "RMOR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -8476,6 +8476,8 @@
(1ull << MSR_DR) |
(1ull << MSR_PMM) |
(1ull << MSR_RI);
+ pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
+ LPCR_RMI | LPCR_HDICE;
pcc->mmu_model = POWERPC_MMU_2_03;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -8492,44 +8494,6 @@
pcc->l1_icache_size = 0x10000;
}
-/*
- * The CPU used to have a "compat" property which set the
- * compatibility mode PVR. However, this was conceptually broken - it
- * only makes sense on the pseries machine type (otherwise the guest
- * owns the PCR and can control the compatibility mode itself). It's
- * been replaced with the 'max-cpu-compat' property on the pseries
- * machine type. For backwards compatibility, pseries specially
- * parses the -cpu parameter and converts old compat= parameters into
- * the appropriate machine parameters. This stub implementation of
- * the parameter catches any uses on explicitly created CPUs.
- */
-static void getset_compat_deprecated(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- QNull *null = NULL;
-
- if (!qtest_enabled()) {
- warn_report("CPU 'compat' property is deprecated and has no effect; "
- "use max-cpu-compat machine property instead");
- }
- visit_type_null(v, name, &null, NULL);
- qobject_unref(null);
-}
-
-static const PropertyInfo ppc_compat_deprecated_propinfo = {
- .name = "str",
- .description = "compatibility mode (deprecated)",
- .get = getset_compat_deprecated,
- .set = getset_compat_deprecated,
-};
-static Property powerpc_servercpu_properties[] = {
- {
- .name = "compat",
- .info = &ppc_compat_deprecated_propinfo,
- },
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void init_proc_POWER7(CPUPPCState *env)
{
/* Common Registers */
@@ -8539,6 +8503,7 @@
/* POWER7 Specific Registers */
gen_spr_book3s_ids(env);
+ gen_spr_rmor(env);
gen_spr_amr(env);
gen_spr_book3s_purr(env);
gen_spr_power5p_common(env);
@@ -8611,7 +8576,6 @@
dc->fw_name = "PowerPC,POWER7";
dc->desc = "POWER7";
- device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power7;
pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
@@ -8652,6 +8616,12 @@
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
+ LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
+ LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
+ LPCR_MER | LPCR_TC |
+ LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -8668,7 +8638,6 @@
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
- pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
}
static void init_proc_POWER8(CPUPPCState *env)
@@ -8680,6 +8649,7 @@
/* POWER8 Specific Registers */
gen_spr_book3s_ids(env);
+ gen_spr_rmor(env);
gen_spr_amr(env);
gen_spr_iamr(env);
gen_spr_book3s_purr(env);
@@ -8776,7 +8746,6 @@
dc->fw_name = "PowerPC,POWER8";
dc->desc = "POWER8";
- device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power8;
pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
@@ -8804,7 +8773,7 @@
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM | PPC2_PM_ISA206;
pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_SHV) |
+ (1ull << MSR_HV) |
(1ull << MSR_TM) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
@@ -8823,6 +8792,13 @@
(1ull << MSR_TS0) |
(1ull << MSR_TS1) |
(1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
+ LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
+ LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
+ LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
+ LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
+ LPCR_P8_PECE3 | LPCR_P8_PECE4;
pcc->mmu_model = POWERPC_MMU_2_07;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -8840,8 +8816,6 @@
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
- pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
- LPCR_P8_PECE3 | LPCR_P8_PECE4;
}
#ifdef CONFIG_SOFTMMU
@@ -8988,7 +8962,6 @@
dc->fw_name = "PowerPC,POWER9";
dc->desc = "POWER9";
- device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power9;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
@@ -9017,7 +8990,7 @@
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_SHV) |
+ (1ull << MSR_HV) |
(1ull << MSR_TM) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
@@ -9034,6 +9007,14 @@
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
+ (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+ LPCR_DEE | LPCR_OEE))
+ | LPCR_MER | LPCR_GTSE | LPCR_TC |
+ LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
pcc->mmu_model = POWERPC_MMU_3_00;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
@@ -9053,7 +9034,6 @@
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
- pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
}
#ifdef CONFIG_SOFTMMU
@@ -9198,7 +9178,6 @@
dc->fw_name = "PowerPC,POWER10";
dc->desc = "POWER10";
- device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power10;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
PCR_COMPAT_3_00;
@@ -9228,7 +9207,7 @@
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
pcc->msr_mask = (1ull << MSR_SF) |
- (1ull << MSR_SHV) |
+ (1ull << MSR_HV) |
(1ull << MSR_TM) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
@@ -9245,6 +9224,14 @@
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
+ (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+ LPCR_DEE | LPCR_OEE))
+ | LPCR_MER | LPCR_GTSE | LPCR_TC |
+ LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
pcc->mmu_model = POWERPC_MMU_3_00;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
@@ -9263,7 +9250,6 @@
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
- pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
}
#if !defined(CONFIG_USER_ONLY)
@@ -9857,7 +9843,7 @@
return -1;
}
-static int gdb_get_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)
{
int reg;
int len;
@@ -9868,8 +9854,8 @@
}
len = TARGET_LONG_SIZE;
- stn_p(mem_buf, len, env->spr[reg]);
- ppc_maybe_bswap_register(env, mem_buf, len);
+ gdb_get_regl(buf, env->spr[reg]);
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
return len;
}
@@ -9891,15 +9877,18 @@
}
#endif
-static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)
{
+ uint8_t *mem_buf;
if (n < 32) {
- stfq_p(mem_buf, *cpu_fpr_ptr(env, n));
+ gdb_get_reg64(buf, *cpu_fpr_ptr(env, n));
+ mem_buf = gdb_get_reg_ptr(buf, 8);
ppc_maybe_bswap_register(env, mem_buf, 8);
return 8;
}
if (n == 32) {
- stl_p(mem_buf, env->fpscr);
+ gdb_get_reg32(buf, env->fpscr);
+ mem_buf = gdb_get_reg_ptr(buf, 4);
ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
@@ -9921,28 +9910,31 @@
return 0;
}
-static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)
{
+ uint8_t *mem_buf;
+
if (n < 32) {
ppc_avr_t *avr = cpu_avr_ptr(env, n);
if (!avr_need_swap(env)) {
- stq_p(mem_buf, avr->u64[0]);
- stq_p(mem_buf + 8, avr->u64[1]);
+ gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]);
} else {
- stq_p(mem_buf, avr->u64[1]);
- stq_p(mem_buf + 8, avr->u64[0]);
+ gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]);
}
+ mem_buf = gdb_get_reg_ptr(buf, 16);
ppc_maybe_bswap_register(env, mem_buf, 8);
ppc_maybe_bswap_register(env, mem_buf + 8, 8);
return 16;
}
if (n == 32) {
- stl_p(mem_buf, helper_mfvscr(env));
+ gdb_get_reg32(buf, helper_mfvscr(env));
+ mem_buf = gdb_get_reg_ptr(buf, 4);
ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
if (n == 33) {
- stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
+ gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]);
+ mem_buf = gdb_get_reg_ptr(buf, 4);
ppc_maybe_bswap_register(env, mem_buf, 4);
return 4;
}
@@ -9977,25 +9969,25 @@
return 0;
}
-static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)
{
if (n < 32) {
#if defined(TARGET_PPC64)
- stl_p(mem_buf, env->gpr[n] >> 32);
- ppc_maybe_bswap_register(env, mem_buf, 4);
+ gdb_get_reg32(buf, env->gpr[n] >> 32);
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
#else
- stl_p(mem_buf, env->gprh[n]);
+ gdb_get_reg32(buf, env->gprh[n]);
#endif
return 4;
}
if (n == 32) {
- stq_p(mem_buf, env->spe_acc);
- ppc_maybe_bswap_register(env, mem_buf, 8);
+ gdb_get_reg64(buf, env->spe_acc);
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
return 8;
}
if (n == 33) {
- stl_p(mem_buf, env->spe_fscr);
- ppc_maybe_bswap_register(env, mem_buf, 4);
+ gdb_get_reg32(buf, env->spe_fscr);
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
return 4;
}
return 0;
@@ -10030,11 +10022,11 @@
return 0;
}
-static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
+static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)
{
if (n < 32) {
- stq_p(mem_buf, *cpu_vsrl_ptr(env, n));
- ppc_maybe_bswap_register(env, mem_buf, 8);
+ gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
+ ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
return 8;
}
return 0;
@@ -10486,6 +10478,8 @@
*s = '\0';
for (i = 0; inpieces[i]; i++) {
if (g_str_has_prefix(inpieces[i], "compat=")) {
+ warn_report_once("CPU 'compat' property is deprecated; "
+ "use max-cpu-compat machine property instead");
compat_str = inpieces[i];
continue;
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3dcdf92..31458c5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -293,7 +293,7 @@
extern const char * const riscv_intr_names[];
void riscv_cpu_do_interrupt(CPUState *cpu);
-int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 2f32750..eba12a8 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -270,7 +270,7 @@
CSR_MHCOUNTEREN,
};
-int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
@@ -301,14 +301,14 @@
return 0;
}
-static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
+static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
{
if (n < 32) {
if (env->misa & RVD) {
- return gdb_get_reg64(mem_buf, env->fpr[n]);
+ return gdb_get_reg64(buf, env->fpr[n]);
}
if (env->misa & RVF) {
- return gdb_get_reg32(mem_buf, env->fpr[n]);
+ return gdb_get_reg32(buf, env->fpr[n]);
}
/* there is hole between ft11 and fflags in fpu.xml */
} else if (n < 36 && n > 32) {
@@ -322,7 +322,7 @@
result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
0, 0);
if (result == 0) {
- return gdb_get_regl(mem_buf, val);
+ return gdb_get_regl(buf, val);
}
}
return 0;
@@ -351,7 +351,7 @@
return 0;
}
-static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
+static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
{
if (n < ARRAY_SIZE(csr_register_map)) {
target_ulong val = 0;
@@ -359,7 +359,7 @@
result = riscv_csrrw_debug(env, csr_register_map[n], &val, 0, 0);
if (result == 0) {
- return gdb_get_regl(mem_buf, val);
+ return gdb_get_regl(buf, val);
}
}
return 0;
@@ -379,13 +379,13 @@
return 0;
}
-static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
+static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
{
if (n == 0) {
#ifdef CONFIG_USER_ONLY
- return gdb_get_regl(mem_buf, 0);
+ return gdb_get_regl(buf, 0);
#else
- return gdb_get_regl(mem_buf, cs->priv);
+ return gdb_get_regl(buf, cs->priv);
#endif
}
return 0;
diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c
index e24a49f..d6fce5f 100644
--- a/target/s390x/gdbstub.c
+++ b/target/s390x/gdbstub.c
@@ -27,7 +27,7 @@
#include "sysemu/hw_accel.h"
#include "sysemu/tcg.h"
-int s390_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
S390CPU *cpu = S390_CPU(cs);
CPUS390XState *env = &cpu->env;
@@ -82,11 +82,11 @@
/* total number of registers in s390-acr.xml */
#define S390_NUM_AC_REGS 16
-static int cpu_read_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n)
{
switch (n) {
case S390_A0_REGNUM ... S390_A15_REGNUM:
- return gdb_get_reg32(mem_buf, env->aregs[n]);
+ return gdb_get_reg32(buf, env->aregs[n]);
default:
return 0;
}
@@ -111,13 +111,13 @@
/* total number of registers in s390-fpr.xml */
#define S390_NUM_FP_REGS 17
-static int cpu_read_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n)
{
switch (n) {
case S390_FPC_REGNUM:
- return gdb_get_reg32(mem_buf, env->fpc);
+ return gdb_get_reg32(buf, env->fpc);
case S390_F0_REGNUM ... S390_F15_REGNUM:
- return gdb_get_reg64(mem_buf, *get_freg(env, n - S390_F0_REGNUM));
+ return gdb_get_reg64(buf, *get_freg(env, n - S390_F0_REGNUM));
default:
return 0;
}
@@ -145,17 +145,17 @@
/* total number of registers in s390-vx.xml */
#define S390_NUM_VREGS 32
-static int cpu_read_vreg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n)
{
int ret;
switch (n) {
case S390_V0L_REGNUM ... S390_V15L_REGNUM:
- ret = gdb_get_reg64(mem_buf, env->vregs[n][1]);
+ ret = gdb_get_reg64(buf, env->vregs[n][1]);
break;
case S390_V16_REGNUM ... S390_V31_REGNUM:
- ret = gdb_get_reg64(mem_buf, env->vregs[n][0]);
- ret += gdb_get_reg64(mem_buf + 8, env->vregs[n][1]);
+ ret = gdb_get_reg64(buf, env->vregs[n][0]);
+ ret += gdb_get_reg64(buf, env->vregs[n][1]);
break;
default:
ret = 0;
@@ -186,11 +186,11 @@
#define S390_NUM_C_REGS 16
#ifndef CONFIG_USER_ONLY
-static int cpu_read_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n)
{
switch (n) {
case S390_C0_REGNUM ... S390_C15_REGNUM:
- return gdb_get_regl(mem_buf, env->cregs[n]);
+ return gdb_get_regl(buf, env->cregs[n]);
default:
return 0;
}
@@ -223,7 +223,7 @@
/* total number of registers in s390-virt.xml */
#define S390_NUM_VIRT_REGS 8
-static int cpu_read_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n)
{
switch (n) {
case S390_VIRT_CKC_REGNUM:
@@ -296,9 +296,9 @@
/* total number of registers in s390-gs.xml */
#define S390_NUM_GS_REGS 4
-static int cpu_read_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
+static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n)
{
- return gdb_get_regl(mem_buf, env->gscb[n]);
+ return gdb_get_regl(buf, env->gscb[n]);
}
static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n)
diff --git a/target/s390x/internal.h b/target/s390x/internal.h
index d378161..8c95c73 100644
--- a/target/s390x/internal.h
+++ b/target/s390x/internal.h
@@ -292,7 +292,7 @@
/* gdbstub.c */
-int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int s390_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void s390_cpu_gdb_init(CPUState *cs);
diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c
index c437a1d..0e840cc 100644
--- a/target/s390x/ioinst.c
+++ b/target/s390x/ioinst.c
@@ -347,7 +347,7 @@
uint16_t len;
uint16_t code;
uint32_t param;
- char data[0];
+ char data[];
} QEMU_PACKED ChscResp;
#define CHSC_MIN_RESP_LEN 0x0008
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 452a596..dbe58c7 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -208,7 +208,7 @@
bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int superh_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c
index 44c1679..49fc4a0 100644
--- a/target/sh4/gdbstub.c
+++ b/target/sh4/gdbstub.c
@@ -24,7 +24,7 @@
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
/* FIXME: We should use XML for this. */
-int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int superh_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
CPUSH4State *env = &cpu->env;
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index ae97c7d..b936939 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -571,7 +571,7 @@
void sparc_cpu_do_interrupt(CPUState *cpu);
void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
index 8be742b..78dc8dc 100644
--- a/target/sparc/gdbstub.c
+++ b/target/sparc/gdbstub.c
@@ -27,7 +27,7 @@
#define gdb_get_rega(buf, val) gdb_get_regl(buf, val)
#endif
-int sparc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 493f4fc..c0d69fa 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -569,7 +569,7 @@
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void xtensa_count_regs(const XtensaConfig *config,
unsigned *n_regs, unsigned *n_core_regs);
-int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c
index 5472788..0ee3fea 100644
--- a/target/xtensa/gdbstub.c
+++ b/target/xtensa/gdbstub.c
@@ -63,7 +63,7 @@
}
}
-int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+int xtensa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index cdedcb2..223dba9 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -3391,12 +3391,15 @@
case MO_64:
if (imm <= 32) {
- /* We can emulate a small sign extend by performing an arithmetic
+ /*
+ * We can emulate a small sign extend by performing an arithmetic
* 32-bit shift and overwriting the high half of a 64-bit logical
- * shift (note that the ISA says shift of 32 is valid).
+ * shift. Note that the ISA says shift of 32 is valid, but TCG
+ * does not, so we have to bound the smaller shift -- we get the
+ * same result in the high half either way.
*/
t1 = tcg_temp_new_vec(type);
- tcg_gen_sari_vec(MO_32, t1, v1, imm);
+ tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31));
tcg_gen_shri_vec(MO_64, v0, v1, imm);
vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
tcgv_vec_arg(v0), tcgv_vec_arg(v0),
diff --git a/tests/.gitignore b/tests/.gitignore
index 7306866..d03c037 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -10,6 +10,7 @@
rcutorture
test-*
!test-*.c
+!test-*.py
!docker/test-*
test-qapi-commands.[ch]
test-qapi-init-commands.[ch]
diff --git a/tests/docker/dockerfiles/debian-amd64.docker b/tests/docker/dockerfiles/debian-amd64.docker
index 3b860af..d4849f5 100644
--- a/tests/docker/dockerfiles/debian-amd64.docker
+++ b/tests/docker/dockerfiles/debian-amd64.docker
@@ -17,6 +17,7 @@
libbz2-dev \
liblzo2-dev \
librdmacm-dev \
+ libsasl2-dev \
libsnappy-dev \
libvte-dev
@@ -27,9 +28,9 @@
libegl1-mesa-dev \
libepoxy-dev \
libgbm-dev
-RUN git clone https://anongit.freedesktop.org/git/virglrenderer.git /usr/src/virglrenderer && \
- cd /usr/src/virglrenderer && git checkout virglrenderer-0.7.0
-RUN cd /usr/src/virglrenderer && ./autogen.sh && ./configure --with-glx --disable-tests && make install
+RUN git clone https://gitlab.freedesktop.org/virgl/virglrenderer.git /usr/src/virglrenderer && \
+ cd /usr/src/virglrenderer && git checkout virglrenderer-0.8.0
+RUN cd /usr/src/virglrenderer && ./autogen.sh && ./configure --disable-tests && make install
# netmap
RUN apt update && \
diff --git a/tests/docker/dockerfiles/debian10.docker b/tests/docker/dockerfiles/debian10.docker
index 5de79ae..2fcdc40 100644
--- a/tests/docker/dockerfiles/debian10.docker
+++ b/tests/docker/dockerfiles/debian10.docker
@@ -17,14 +17,17 @@
DEBIAN_FRONTEND=noninteractive apt install -yy eatmydata && \
DEBIAN_FRONTEND=noninteractive eatmydata \
apt install -y --no-install-recommends \
+ bc \
bison \
build-essential \
ca-certificates \
clang \
dbus \
flex \
+ gdb-multiarch \
gettext \
git \
+ libncurses5-dev \
pkg-config \
psmisc \
python3 \
diff --git a/tests/docker/dockerfiles/debian9.docker b/tests/docker/dockerfiles/debian9.docker
index 8cbd742..92edbbf 100644
--- a/tests/docker/dockerfiles/debian9.docker
+++ b/tests/docker/dockerfiles/debian9.docker
@@ -17,13 +17,16 @@
DEBIAN_FRONTEND=noninteractive apt install -yy eatmydata && \
DEBIAN_FRONTEND=noninteractive eatmydata \
apt install -y --no-install-recommends \
+ bc \
bison \
build-essential \
ca-certificates \
clang \
flex \
+ gdb-multiarch \
gettext \
git \
+ libncurses5-dev \
pkg-config \
psmisc \
python3 \
diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/run-test.py
new file mode 100755
index 0000000..8c49ee2
--- /dev/null
+++ b/tests/guest-debug/run-test.py
@@ -0,0 +1,57 @@
+#!/usr/bin/env python3
+#
+# Run a gdbstub test case
+#
+# Copyright (c) 2019 Linaro
+#
+# Author: Alex Bennée <alex.bennee@linaro.org>
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or later.
+# See the COPYING file in the top-level directory.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import argparse
+import subprocess
+import shutil
+import shlex
+
+def get_args():
+ parser = argparse.ArgumentParser(description="A gdbstub test runner")
+ parser.add_argument("--qemu", help="Qemu binary for test",
+ required=True)
+ parser.add_argument("--qargs", help="Qemu arguments for test")
+ parser.add_argument("--binary", help="Binary to debug",
+ required=True)
+ parser.add_argument("--test", help="GDB test script",
+ required=True)
+ parser.add_argument("--gdb", help="The gdb binary to use", default=None)
+
+ return parser.parse_args()
+
+if __name__ == '__main__':
+ args = get_args()
+
+ # Search for a gdb we can use
+ if not args.gdb:
+ args.gdb = shutil.which("gdb-multiarch")
+ if not args.gdb:
+ args.gdb = shutil.which("gdb")
+ if not args.gdb:
+ print("We need gdb to run the test")
+ exit(-1)
+
+ # Launch QEMU with binary
+ if "system" in args.qemu:
+ cmd = "%s %s %s -s -S" % (args.qemu, args.qargs, args.binary)
+ else:
+ cmd = "%s %s -g 1234 %s" % (args.qemu, args.qargs, args.binary)
+
+ inferior = subprocess.Popen(shlex.split(cmd))
+
+ # Now launch gdb with our test and collect the result
+ gdb_cmd = "%s %s -ex 'target remote localhost:1234' -x %s" % (args.gdb, args.binary, args.test)
+
+ result = subprocess.call(gdb_cmd, shell=True);
+
+ exit(result)
diff --git a/tests/qtest/fuzz/qos_fuzz.c b/tests/qtest/fuzz/qos_fuzz.c
index 1a99277..af28c92 100644
--- a/tests/qtest/fuzz/qos_fuzz.c
+++ b/tests/qtest/fuzz/qos_fuzz.c
@@ -55,10 +55,8 @@
QObject *response;
QDict *args = qdict_new();
QList *lst;
- Error *err = NULL;
- qmp_marshal_query_machines(NULL, &response, &err);
- assert(!err);
+ qmp_marshal_query_machines(NULL, &response, &error_abort);
lst = qobject_to(QList, response);
apply_to_qlist(lst, true);
@@ -70,8 +68,7 @@
qdict_put_bool(args, "abstract", true);
qdict_put_obj(req, "arguments", (QObject *) args);
- qmp_marshal_qom_list_types(args, &response, &err);
- assert(!err);
+ qmp_marshal_qom_list_types(args, &response, &error_abort);
lst = qobject_to(QList, response);
apply_to_qlist(lst, false);
qobject_unref(response);
diff --git a/tests/qtest/libqos/ahci.h b/tests/qtest/libqos/ahci.h
index f05b3e5..44ab110 100644
--- a/tests/qtest/libqos/ahci.h
+++ b/tests/qtest/libqos/ahci.h
@@ -351,7 +351,7 @@
typedef struct FIS {
uint8_t fis_type;
uint8_t flags;
- char data[0];
+ char data[];
} __attribute__((__packed__)) FIS;
/**
diff --git a/tests/qtest/libqos/libqos-spapr.h b/tests/qtest/libqos/libqos-spapr.h
index d9c4c22..49bd72d 100644
--- a/tests/qtest/libqos/libqos-spapr.h
+++ b/tests/qtest/libqos/libqos-spapr.h
@@ -12,7 +12,6 @@
"cap-cfpc=broken," \
"cap-sbbc=broken," \
"cap-ibs=broken," \
- "cap-ccf-assist=off," \
- "cap-fwnmi-mce=off"
+ "cap-ccf-assist=off,"
#endif
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 8ed477d..d99b2a9 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -42,4 +42,36 @@
run-plugin-semiconsole-with-%:
$(call skip-test, $<, "MANUAL ONLY")
+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE),)
+# System Registers Tests
+AARCH64_TESTS += sysregs
+sysregs: CFLAGS+=-march=armv8.1-a+sve
+
+# SVE ioctl test
+AARCH64_TESTS += sve-ioctls
+sve-ioctls: CFLAGS+=-march=armv8.1-a+sve
+
+ifneq ($(HAVE_GDB_BIN),)
+GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py
+
+AARCH64_TESTS += gdbstub-sysregs gdbstub-sve-ioctls
+
+.PHONY: gdbstub-sysregs gdbstub-sve-ioctls
+run-gdbstub-sysregs: sysregs
+ $(call run-test, $@, $(GDB_SCRIPT) \
+ --gdb $(HAVE_GDB_BIN) \
+ --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
+ --bin $< --test $(AARCH64_SRC)/gdbstub/test-sve.py, \
+ "basic gdbstub SVE support")
+
+run-gdbstub-sve-ioctls: sve-ioctls
+ $(call run-test, $@, $(GDB_SCRIPT) \
+ --gdb $(HAVE_GDB_BIN) \
+ --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
+ --bin $< --test $(AARCH64_SRC)/gdbstub/test-sve-ioctl.py, \
+ "basic gdbstub SVE ZLEN support")
+endif
+
+endif
+
TESTS += $(AARCH64_TESTS)
diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
new file mode 100644
index 0000000..984fbeb
--- /dev/null
+++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
@@ -0,0 +1,85 @@
+from __future__ import print_function
+#
+# Test the SVE ZReg reports the right amount of data. It uses the
+# sve-ioctl test and examines the register data each time the
+# __sve_ld_done breakpoint is hit.
+#
+# This is launched via tests/guest-debug/run-test.py
+#
+
+import gdb
+import sys
+
+initial_vlen = 0
+failcount = 0
+
+def report(cond, msg):
+ "Report success/fail of test"
+ if cond:
+ print ("PASS: %s" % (msg))
+ else:
+ print ("FAIL: %s" % (msg))
+ global failcount
+ failcount += 1
+
+class TestBreakpoint(gdb.Breakpoint):
+ def __init__(self, sym_name="__sve_ld_done"):
+ super(TestBreakpoint, self).__init__(sym_name)
+ # self.sym, ok = gdb.lookup_symbol(sym_name)
+
+ def stop(self):
+ val_i = gdb.parse_and_eval('i')
+ global initial_vlen
+ try:
+ for i in range(0, int(val_i)):
+ val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i)
+ report(int(val_z) == i, "z0.b.u[%d] == %d" % (i, i))
+ for i in range(i + 1, initial_vlen):
+ val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i)
+ report(int(val_z) == 0, "z0.b.u[%d] == 0" % (i))
+ except gdb.error:
+ report(False, "checking zregs (out of range)")
+
+
+def run_test():
+ "Run through the tests one by one"
+
+ print ("Setup breakpoint")
+ bp = TestBreakpoint()
+
+ global initial_vlen
+ vg = gdb.parse_and_eval("$vg")
+ initial_vlen = int(vg) * 8
+
+ gdb.execute("c")
+
+#
+# This runs as the script it sourced (via -x, via run-test.py)
+#
+try:
+ inferior = gdb.selected_inferior()
+ if inferior.was_attached == False:
+ print("SKIPPING (failed to attach)", file=sys.stderr)
+ exit(0)
+ arch = inferior.architecture()
+ report(arch.name() == "aarch64", "connected to aarch64")
+except (gdb.error, AttributeError):
+ print("SKIPPING (not connected)", file=sys.stderr)
+ exit(0)
+
+try:
+ # These are not very useful in scripts
+ gdb.execute("set pagination off")
+ gdb.execute("set confirm off")
+
+ # Run the actual tests
+ run_test()
+except:
+ print ("GDB Exception: %s" % (sys.exc_info()[0]))
+ failcount += 1
+ import code
+ code.InteractiveConsole(locals=globals()).interact()
+ raise
+
+print("All tests complete: %d failures" % failcount)
+exit(failcount)
diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbstub/test-sve.py
new file mode 100644
index 0000000..dbe7f2a
--- /dev/null
+++ b/tests/tcg/aarch64/gdbstub/test-sve.py
@@ -0,0 +1,84 @@
+from __future__ import print_function
+#
+# Test the SVE registers are visable and changeable via gdbstub
+#
+# This is launched via tests/guest-debug/run-test.py
+#
+
+import gdb
+import sys
+
+MAGIC = 0xDEADBEEF
+
+failcount = 0
+
+def report(cond, msg):
+ "Report success/fail of test"
+ if cond:
+ print ("PASS: %s" % (msg))
+ else:
+ print ("FAIL: %s" % (msg))
+ global failcount
+ failcount += 1
+
+def run_test():
+ "Run through the tests one by one"
+
+ gdb.execute("info registers")
+ report(True, "info registers")
+
+ gdb.execute("info registers vector")
+ report(True, "info registers vector")
+
+ # Now all the zregs
+ frame = gdb.selected_frame()
+ for i in range(0, 32):
+ rname = "z%d" % (i)
+ zreg = frame.read_register(rname)
+ report(True, "Reading %s" % rname)
+ for j in range(0, 4):
+ cmd = "set $%s.q.u[%d] = 0x%x" % (rname, j, MAGIC)
+ gdb.execute(cmd)
+ report(True, "%s" % cmd)
+ for j in range(0, 4):
+ reg = "$%s.q.u[%d]" % (rname, j)
+ v = gdb.parse_and_eval(reg)
+ report(str(v.type) == "uint128_t", "size of %s" % (reg))
+ for j in range(0, 8):
+ cmd = "set $%s.d.u[%d] = 0x%x" % (rname, j, MAGIC)
+ gdb.execute(cmd)
+ report(True, "%s" % cmd)
+ for j in range(0, 8):
+ reg = "$%s.d.u[%d]" % (rname, j)
+ v = gdb.parse_and_eval(reg)
+ report(str(v.type) == "uint64_t", "size of %s" % (reg))
+ report(int(v) == MAGIC, "%s is 0x%x" % (reg, MAGIC))
+
+#
+# This runs as the script it sourced (via -x, via run-test.py)
+#
+try:
+ inferior = gdb.selected_inferior()
+ if inferior.was_attached == False:
+ print("SKIPPING (failed to attach)", file=sys.stderr)
+ exit(0)
+ arch = inferior.architecture()
+ report(arch.name() == "aarch64", "connected to aarch64")
+except (gdb.error, AttributeError):
+ print("SKIPPING (not connected)", file=sys.stderr)
+ exit(0)
+
+try:
+ # These are not very useful in scripts
+ gdb.execute("set pagination off")
+ gdb.execute("set confirm off")
+
+ # Run the actual tests
+ run_test()
+except:
+ print ("GDB Exception: %s" % (sys.exc_info()[0]))
+ failcount += 1
+
+print("All tests complete: %d failures" % failcount)
+
+exit(failcount)
diff --git a/tests/tcg/aarch64/sve-ioctls.c b/tests/tcg/aarch64/sve-ioctls.c
new file mode 100644
index 0000000..9544dff
--- /dev/null
+++ b/tests/tcg/aarch64/sve-ioctls.c
@@ -0,0 +1,70 @@
+/*
+ * SVE ioctls tests
+ *
+ * Test the SVE width setting ioctls work and provide a base for
+ * testing the gdbstub.
+ *
+ * Copyright (c) 2019 Linaro Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include <sys/prctl.h>
+#include <asm/hwcap.h>
+#include <stdio.h>
+#include <sys/auxv.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#ifndef HWCAP_CPUID
+#define HWCAP_CPUID (1 << 11)
+#endif
+
+#define SVE_MAX_QUADS (2048 / 128)
+#define BYTES_PER_QUAD (128 / 8)
+
+#define get_cpu_reg(id) ({ \
+ unsigned long __val; \
+ asm("mrs %0, "#id : "=r" (__val)); \
+ __val; \
+ })
+
+static int do_sve_ioctl_test(void)
+{
+ int i, res, init_vq;
+
+ res = prctl(PR_SVE_GET_VL, 0, 0, 0, 0);
+ if (res < 0) {
+ printf("FAILED to PR_SVE_GET_VL (%d)", res);
+ return -1;
+ }
+ init_vq = res & PR_SVE_VL_LEN_MASK;
+
+ for (i = init_vq; i > 15; i /= 2) {
+ printf("Checking PR_SVE_SET_VL=%d\n", i);
+ res = prctl(PR_SVE_SET_VL, i, 0, 0, 0, 0);
+ if (res < 0) {
+ printf("FAILED to PR_SVE_SET_VL (%d)", res);
+ return -1;
+ }
+ asm("index z0.b, #0, #1\n"
+ ".global __sve_ld_done\n"
+ "__sve_ld_done:\n"
+ "mov z0.b, #0\n"
+ : /* no outputs kept */
+ : /* no inputs */
+ : "memory", "z0");
+ }
+ printf("PASS\n");
+ return 0;
+}
+
+int main(int argc, char **argv)
+{
+ /* we also need to probe for the ioctl support */
+ if (getauxval(AT_HWCAP) & HWCAP_SVE) {
+ return do_sve_ioctl_test();
+ } else {
+ printf("SKIP: no HWCAP_SVE on this system\n");
+ return 0;
+ }
+}
diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
new file mode 100644
index 0000000..40cf8d2
--- /dev/null
+++ b/tests/tcg/aarch64/sysregs.c
@@ -0,0 +1,172 @@
+/*
+ * Check emulated system register access for linux-user mode.
+ *
+ * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt
+ *
+ * Copyright (c) 2019 Linaro
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <asm/hwcap.h>
+#include <stdio.h>
+#include <sys/auxv.h>
+#include <signal.h>
+#include <string.h>
+#include <stdbool.h>
+
+#ifndef HWCAP_CPUID
+#define HWCAP_CPUID (1 << 11)
+#endif
+
+int failed_bit_count;
+
+/* Read and print system register `id' value */
+#define get_cpu_reg(id) ({ \
+ unsigned long __val = 0xdeadbeef; \
+ asm("mrs %0, "#id : "=r" (__val)); \
+ printf("%-20s: 0x%016lx\n", #id, __val); \
+ __val; \
+ })
+
+/* As above but also check no bits outside of `mask' are set*/
+#define get_cpu_reg_check_mask(id, mask) ({ \
+ unsigned long __cval = get_cpu_reg(id); \
+ unsigned long __extra = __cval & ~mask; \
+ if (__extra) { \
+ printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); \
+ failed_bit_count++; \
+ } \
+})
+
+/* As above but check RAZ */
+#define get_cpu_reg_check_zero(id) ({ \
+ unsigned long __val = 0xdeadbeef; \
+ asm("mrs %0, "#id : "=r" (__val)); \
+ if (__val) { \
+ printf("%-20s: 0x%016lx (not RAZ!)\n", #id, __val); \
+ failed_bit_count++; \
+ } \
+})
+
+/* Chunk up mask into 63:48, 47:32, 31:16, 15:0 to ease counting */
+#define _m(a, b, c, d) (0x ## a ## b ## c ## d ##ULL)
+
+bool should_fail;
+int should_fail_count;
+int should_not_fail_count;
+uintptr_t failed_pc[10];
+
+void sigill_handler(int signo, siginfo_t *si, void *data)
+{
+ ucontext_t *uc = (ucontext_t *)data;
+
+ if (should_fail) {
+ should_fail_count++;
+ } else {
+ uintptr_t pc = (uintptr_t) uc->uc_mcontext.pc;
+ failed_pc[should_not_fail_count++] = pc;
+ }
+ uc->uc_mcontext.pc += 4;
+}
+
+int main(void)
+{
+ struct sigaction sa;
+
+ /* Hook in a SIGILL handler */
+ memset(&sa, 0, sizeof(struct sigaction));
+ sa.sa_flags = SA_SIGINFO;
+ sa.sa_sigaction = &sigill_handler;
+ sigemptyset(&sa.sa_mask);
+
+ if (sigaction(SIGILL, &sa, 0) != 0) {
+ perror("sigaction");
+ return 1;
+ }
+
+ /* Counter values have been exposed since Linux 4.12 */
+ printf("Checking Counter registers\n");
+
+ get_cpu_reg(ctr_el0);
+ get_cpu_reg(cntvct_el0);
+ get_cpu_reg(cntfrq_el0);
+
+ /* HWCAP_CPUID indicates we can read feature registers, since Linux 4.11 */
+ if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
+ printf("CPUID registers unavailable\n");
+ return 1;
+ } else {
+ printf("Checking CPUID registers\n");
+ }
+
+ /*
+ * Some registers only expose some bits to user-space. Anything
+ * that is IMPDEF is exported as 0 to user-space. The _mask checks
+ * assert no extra bits are set.
+ *
+ * This check is *not* comprehensive as some fields are set to
+ * minimum valid fields - for the purposes of this check allowed
+ * to have non-zero values.
+ */
+ get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0));
+ get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff));
+ /* TGran4 & TGran64 as pegged to -1 */
+ get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000));
+ get_cpu_reg_check_zero(id_aa64mmfr1_el1);
+ /* EL1/EL0 reported as AA64 only */
+ get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011));
+ get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0));
+ /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
+ get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
+ get_cpu_reg_check_zero(id_aa64dfr1_el1);
+ get_cpu_reg_check_zero(id_aa64zfr0_el1);
+
+ get_cpu_reg_check_zero(id_aa64afr0_el1);
+ get_cpu_reg_check_zero(id_aa64afr1_el1);
+
+ get_cpu_reg_check_mask(midr_el1, _m(0000,0000,ffff,ffff));
+ /* mpidr sets bit 31, everything else hidden */
+ get_cpu_reg_check_mask(mpidr_el1, _m(0000,0000,8000,0000));
+ /* REVIDR is all IMPDEF so should be all zeros to user-space */
+ get_cpu_reg_check_zero(revidr_el1);
+
+ /*
+ * There are a block of more registers that are RAZ in the rest of
+ * the Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 space. However for
+ * brevity we don't check stuff that is currently un-allocated
+ * here. Feel free to add them ;-)
+ */
+
+ printf("Remaining registers should fail\n");
+ should_fail = true;
+
+ /* Unexposed register access causes SIGILL */
+ get_cpu_reg(id_mmfr0_el1);
+ get_cpu_reg(id_mmfr1_el1);
+ get_cpu_reg(id_mmfr2_el1);
+ get_cpu_reg(id_mmfr3_el1);
+
+ get_cpu_reg(mvfr0_el1);
+ get_cpu_reg(mvfr1_el1);
+
+ if (should_not_fail_count > 0) {
+ int i;
+ for (i = 0; i < should_not_fail_count; i++) {
+ uintptr_t pc = failed_pc[i];
+ uint32_t insn = *(uint32_t *) pc;
+ printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc);
+ }
+ return 1;
+ }
+
+ if (failed_bit_count > 0) {
+ printf("Extra information leaked to user-space!\n");
+ return 1;
+ }
+
+ return should_fail_count == 6 ? 0 : 1;
+}
diff --git a/ui/console.c b/ui/console.c
index 179901c..184e173 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -1299,8 +1299,8 @@
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG,
&error_abort);
- object_property_add_uint32_ptr(obj, "head",
- &s->head, &error_abort);
+ object_property_add_uint32_ptr(obj, "head", &s->head,
+ OBJ_PROP_FLAG_READ, &error_abort);
if (!active_console || ((active_console->console_type != GRAPHIC_CONSOLE) &&
(console_type == GRAPHIC_CONSOLE))) {
diff --git a/ui/curses.c b/ui/curses.c
index 3a1b714..a59b23a 100644
--- a/ui/curses.c
+++ b/ui/curses.c
@@ -54,13 +54,13 @@
};
static DisplayChangeListener *dcl;
-static console_ch_t screen[160 * 100];
+static console_ch_t *screen;
static WINDOW *screenpad = NULL;
static int width, height, gwidth, gheight, invalidate;
static int px, py, sminx, sminy, smaxx, smaxy;
static const char *font_charset = "CP437";
-static cchar_t vga_to_curses[256];
+static cchar_t *vga_to_curses;
static void curses_update(DisplayChangeListener *dcl,
int x, int y, int w, int h)
@@ -405,6 +405,8 @@
static void curses_atexit(void)
{
endwin();
+ g_free(vga_to_curses);
+ g_free(screen);
}
/*
@@ -529,7 +531,7 @@
* Control characters are normally non-printable, but VGA does have
* well-known glyphs for them.
*/
- static uint16_t control_characters[0x20] = {
+ static const uint16_t control_characters[0x20] = {
0x0020,
0x263a,
0x263b,
@@ -783,6 +785,8 @@
if (opts->u.curses.charset) {
font_charset = opts->u.curses.charset;
}
+ screen = g_new0(console_ch_t, 160 * 100);
+ vga_to_curses = g_new0(cchar_t, 256);
curses_setup();
curses_keyboard_setup();
atexit(curses_atexit);
diff --git a/util/bufferiszero.c b/util/bufferiszero.c
index bfb2605..6639035 100644
--- a/util/bufferiszero.c
+++ b/util/bufferiszero.c
@@ -63,11 +63,11 @@
}
}
-#if defined(CONFIG_AVX2_OPT) || defined(__SSE2__)
+#if defined(CONFIG_AVX512F_OPT) || defined(CONFIG_AVX2_OPT) || defined(__SSE2__)
/* Do not use push_options pragmas unnecessarily, because clang
* does not support them.
*/
-#ifdef CONFIG_AVX2_OPT
+#if defined(CONFIG_AVX512F_OPT) || defined(CONFIG_AVX2_OPT)
#pragma GCC push_options
#pragma GCC target("sse2")
#endif
@@ -104,7 +104,7 @@
return _mm_movemask_epi8(_mm_cmpeq_epi8(t, zero)) == 0xFFFF;
}
-#ifdef CONFIG_AVX2_OPT
+#if defined(CONFIG_AVX512F_OPT) || defined(CONFIG_AVX2_OPT)
#pragma GCC pop_options
#endif
@@ -187,18 +187,54 @@
#pragma GCC pop_options
#endif /* CONFIG_AVX2_OPT */
+#ifdef CONFIG_AVX512F_OPT
+#pragma GCC push_options
+#pragma GCC target("avx512f")
+#include <immintrin.h>
+
+static bool
+buffer_zero_avx512(const void *buf, size_t len)
+{
+ /* Begin with an unaligned head of 64 bytes. */
+ __m512i t = _mm512_loadu_si512(buf);
+ __m512i *p = (__m512i *)(((uintptr_t)buf + 5 * 64) & -64);
+ __m512i *e = (__m512i *)(((uintptr_t)buf + len) & -64);
+
+ /* Loop over 64-byte aligned blocks of 256. */
+ while (p <= e) {
+ __builtin_prefetch(p);
+ if (unlikely(_mm512_test_epi64_mask(t, t))) {
+ return false;
+ }
+ t = p[-4] | p[-3] | p[-2] | p[-1];
+ p += 4;
+ }
+
+ t |= _mm512_loadu_si512(buf + len - 4 * 64);
+ t |= _mm512_loadu_si512(buf + len - 3 * 64);
+ t |= _mm512_loadu_si512(buf + len - 2 * 64);
+ t |= _mm512_loadu_si512(buf + len - 1 * 64);
+
+ return !_mm512_test_epi64_mask(t, t);
+
+}
+#pragma GCC pop_options
+#endif
+
+
/* Note that for test_buffer_is_zero_next_accel, the most preferred
* ISA must have the least significant bit.
*/
-#define CACHE_AVX2 1
-#define CACHE_SSE4 2
-#define CACHE_SSE2 4
+#define CACHE_AVX512F 1
+#define CACHE_AVX2 2
+#define CACHE_SSE4 4
+#define CACHE_SSE2 8
/* Make sure that these variables are appropriately initialized when
* SSE2 is enabled on the compiler command-line, but the compiler is
* too old to support CONFIG_AVX2_OPT.
*/
-#ifdef CONFIG_AVX2_OPT
+#if defined(CONFIG_AVX512F_OPT) || defined(CONFIG_AVX2_OPT)
# define INIT_CACHE 0
# define INIT_ACCEL buffer_zero_int
#else
@@ -211,6 +247,7 @@
static unsigned cpuid_cache = INIT_CACHE;
static bool (*buffer_accel)(const void *, size_t) = INIT_ACCEL;
+static int length_to_accel = 64;
static void init_accel(unsigned cache)
{
@@ -226,10 +263,16 @@
fn = buffer_zero_avx2;
}
#endif
+#ifdef CONFIG_AVX512F_OPT
+ if (cache & CACHE_AVX512F) {
+ fn = buffer_zero_avx512;
+ length_to_accel = 256;
+ }
+#endif
buffer_accel = fn;
}
-#ifdef CONFIG_AVX2_OPT
+#if defined(CONFIG_AVX512F_OPT) || defined(CONFIG_AVX2_OPT)
#include "qemu/cpuid.h"
static void __attribute__((constructor)) init_cpuid_cache(void)
@@ -252,9 +295,17 @@
int bv;
__asm("xgetbv" : "=a"(bv), "=d"(d) : "c"(0));
__cpuid_count(7, 0, a, b, c, d);
- if ((bv & 6) == 6 && (b & bit_AVX2)) {
+ if ((bv & 0x6) == 0x6 && (b & bit_AVX2)) {
cache |= CACHE_AVX2;
}
+ /* 0xe6:
+ * XCR0[7:5] = 111b (OPMASK state, upper 256-bit of ZMM0-ZMM15
+ * and ZMM16-ZMM31 state are enabled by OS)
+ * XCR0[2:1] = 11b (XMM state and YMM state are enabled by OS)
+ */
+ if ((bv & 0xe6) == 0xe6 && (b & bit_AVX512F)) {
+ cache |= CACHE_AVX512F;
+ }
}
}
cpuid_cache = cache;
@@ -277,7 +328,7 @@
static bool select_accel_fn(const void *buf, size_t len)
{
- if (likely(len >= 64)) {
+ if (likely(len >= length_to_accel)) {
return buffer_accel(buf, len);
}
return buffer_zero_int(buf, len);
diff --git a/util/module.c b/util/module.c
index 236a7bb..5f78968 100644
--- a/util/module.c
+++ b/util/module.c
@@ -19,6 +19,9 @@
#endif
#include "qemu/queue.h"
#include "qemu/module.h"
+#ifdef CONFIG_MODULE_UPGRADES
+#include "qemu-version.h"
+#endif
typedef struct ModuleEntry
{
@@ -170,6 +173,9 @@
#ifdef CONFIG_MODULES
char *fname = NULL;
char *exec_dir;
+#ifdef CONFIG_MODULE_UPGRADES
+ char *version_dir;
+#endif
const char *search_dir;
char *dirs[4];
char *module_name;
@@ -201,6 +207,14 @@
dirs[n_dirs++] = g_strdup_printf("%s", CONFIG_QEMU_MODDIR);
dirs[n_dirs++] = g_strdup_printf("%s/..", exec_dir ? : "");
dirs[n_dirs++] = g_strdup_printf("%s", exec_dir ? : "");
+
+#ifdef CONFIG_MODULE_UPGRADES
+ version_dir = g_strcanon(g_strdup(QEMU_PKGVERSION),
+ G_CSET_A_2_Z G_CSET_a_2_z G_CSET_DIGITS "+-.~",
+ '_');
+ dirs[n_dirs++] = g_strdup_printf("/var/run/qemu/%s", version_dir);
+#endif
+
assert(n_dirs <= ARRAY_SIZE(dirs));
g_free(exec_dir);
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index 897e8f3..4dd6d7d 100644
--- a/util/oslib-posix.c
+++ b/util/oslib-posix.c
@@ -466,10 +466,17 @@
static bool touch_all_pages(char *area, size_t hpagesize, size_t numpages,
int smp_cpus)
{
+ static gsize initialized = 0;
size_t numpages_per_thread, leftover;
char *addr = area;
int i = 0;
+ if (g_once_init_enter(&initialized)) {
+ qemu_mutex_init(&page_mutex);
+ qemu_cond_init(&page_cond);
+ g_once_init_leave(&initialized, 1);
+ }
+
memset_thread_failed = false;
threads_created_flag = false;
memset_num_threads = get_memset_num_threads(smp_cpus);
diff --git a/util/qemu-timer.c b/util/qemu-timer.c
index ef52d28..d548d3c 100644
--- a/util/qemu-timer.c
+++ b/util/qemu-timer.c
@@ -25,6 +25,7 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "qemu/timer.h"
+#include "qemu/lockable.h"
#include "sysemu/replay.h"
#include "sysemu/cpus.h"
@@ -186,13 +187,12 @@
return false;
}
- qemu_mutex_lock(&timer_list->active_timers_lock);
- if (!timer_list->active_timers) {
- qemu_mutex_unlock(&timer_list->active_timers_lock);
- return false;
+ WITH_QEMU_LOCK_GUARD(&timer_list->active_timers_lock) {
+ if (!timer_list->active_timers) {
+ return false;
+ }
+ expire_time = timer_list->active_timers->expire_time;
}
- expire_time = timer_list->active_timers->expire_time;
- qemu_mutex_unlock(&timer_list->active_timers_lock);
return expire_time <= qemu_clock_get_ns(timer_list->clock->type);
}
@@ -225,13 +225,12 @@
* value but ->notify_cb() is called when the deadline changes. Therefore
* the caller should notice the change and there is no race condition.
*/
- qemu_mutex_lock(&timer_list->active_timers_lock);
- if (!timer_list->active_timers) {
- qemu_mutex_unlock(&timer_list->active_timers_lock);
- return -1;
+ WITH_QEMU_LOCK_GUARD(&timer_list->active_timers_lock) {
+ if (!timer_list->active_timers) {
+ return -1;
+ }
+ expire_time = timer_list->active_timers->expire_time;
}
- expire_time = timer_list->active_timers->expire_time;
- qemu_mutex_unlock(&timer_list->active_timers_lock);
delta = expire_time - qemu_clock_get_ns(timer_list->clock->type);
