Sign in
qemu
/
qemu
/
e8ad5817b250720321d44302a811cf7319f4b029
/
.
/
tcg
/
sparc64
/
tcg-target-reg-bits.h
blob: 34a6711013dd1a0fe4f838bfb4fb39e0ddd96e10 [
file
] [
log
] [
blame
]
/* SPDX-License-Identifier: MIT */
/*
* Define target-specific register size
* Copyright (c) 2023 Linaro
*/
#ifndef
TCG_TARGET_REG_BITS_H
#define
TCG_TARGET_REG_BITS_H
#define
TCG_TARGET_REG_BITS
64
#endif