| * Copyright (c) 2006 CodeSourcery. |
| * This code is licenced under the LGPL. |
| /* The CPU is also modeled as an interrupt controller. */ |
| #define ARM_PIC_CPU_IRQ 0 |
| #define ARM_PIC_CPU_FIQ 1 |
| qemu_irq *arm_pic_init_cpu(CPUState *env); |
| qemu_irq *armv7m_init(int flash_size, int sram_size, |
| const char *kernel_filename, const char *cpu_model); |
| const char *kernel_filename; |
| const char *kernel_cmdline; |
| const char *initrd_filename; |
| target_phys_addr_t loader_start; |
| target_phys_addr_t smp_loader_start; |
| int (*atag_board)(struct arm_boot_info *info, void *p); |
| void arm_load_kernel(CPUState *env, struct arm_boot_info *info); |
| /* Multiplication factor to convert from system clock ticks to qemu timer |
| extern int system_clock_scale; |
| qemu_irq *armv7m_nvic_init(CPUState *env); |
| void stellaris_enet_init(NICInfo *nd, uint32_t base, qemu_irq irq); |