| # |
| # RISC-V translation routines for the RVXI Base Integer Instruction Set. |
| # |
| # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de |
| # Bastian Koppelmann, kbastian@mail.uni-paderborn.de |
| # |
| # This program is free software; you can redistribute it and/or modify it |
| # under the terms and conditions of the GNU General Public License, |
| # version 2 or later, as published by the Free Software Foundation. |
| # |
| # This program is distributed in the hope it will be useful, but WITHOUT |
| # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| # more details. |
| # |
| # You should have received a copy of the GNU General Public License along with |
| # this program. If not, see <http://www.gnu.org/licenses/>. |
| |
| # Fields: |
| %rd 7:5 |
| %rs1_3 7:3 !function=ex_rvc_register |
| %rs2_3 2:3 !function=ex_rvc_register |
| %rs2_5 2:5 |
| |
| # Immediates: |
| %imm_ci 12:s1 2:5 |
| %nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2 |
| %uimm_cl_d 5:2 10:3 !function=ex_shift_3 |
| %uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2 |
| %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1 |
| %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1 |
| |
| %nzuimm_6bit 12:1 2:5 |
| %uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3 |
| %uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2 |
| %uimm_6bit_sd 7:3 10:3 !function=ex_shift_3 |
| %uimm_6bit_sw 7:2 9:4 !function=ex_shift_2 |
| |
| %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4 |
| %imm_lui 12:s1 2:5 !function=ex_shift_12 |
| |
| |
| |
| # Argument sets: |
| &cl rs1 rd |
| &cl_dw uimm rs1 rd |
| &ci imm rd |
| &ciw nzuimm rd |
| &cs rs1 rs2 |
| &cs_dw uimm rs1 rs2 |
| &cb imm rs1 |
| &cr rd rs2 |
| &cj imm |
| &c_shift shamt rd |
| |
| &c_ld uimm rd |
| &c_sd uimm rs2 |
| |
| &caddi16sp_lui imm_lui imm_addi16sp rd |
| &cflwsp_ldsp uimm_flwsp uimm_ldsp rd |
| &cfswsp_sdsp uimm_fswsp uimm_sdsp rs2 |
| |
| # Formats 16: |
| @cr .... ..... ..... .. &cr rs2=%rs2_5 %rd |
| @ci ... . ..... ..... .. &ci imm=%imm_ci %rd |
| @ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3 |
| @cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 |
| @cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 |
| @cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 |
| @cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3 |
| @cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3 |
| @cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 |
| @cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 |
| @cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3 |
| @cj ... ........... .. &cj imm=%imm_cj |
| |
| @c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd |
| @c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd |
| @c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5 |
| @c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5 |
| |
| @c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd |
| @c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \ |
| uimm_ldsp=%uimm_6bit_ld %rd |
| @c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \ |
| uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5 |
| |
| @c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit |
| @c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit |
| |
| @c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3 |
| |
| # *** RV64C Standard Extension (Quadrant 0) *** |
| c_addi4spn 000 ........ ... 00 @ciw |
| c_fld 001 ... ... .. ... 00 @cl_d |
| c_lw 010 ... ... .. ... 00 @cl_w |
| c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually |
| c_fsd 101 ... ... .. ... 00 @cs_d |
| c_sw 110 ... ... .. ... 00 @cs_w |
| c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually |
| |
| # *** RV64C Standard Extension (Quadrant 1) *** |
| c_addi 000 . ..... ..... 01 @ci |
| c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually |
| c_li 010 . ..... ..... 01 @ci |
| c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI |
| c_srli 100 . 00 ... ..... 01 @c_shift |
| c_srai 100 . 01 ... ..... 01 @c_shift |
| c_andi 100 . 10 ... ..... 01 @c_andi |
| c_sub 100 0 11 ... 00 ... 01 @cs_2 |
| c_xor 100 0 11 ... 01 ... 01 @cs_2 |
| c_or 100 0 11 ... 10 ... 01 @cs_2 |
| c_and 100 0 11 ... 11 ... 01 @cs_2 |
| c_subw 100 1 11 ... 00 ... 01 @cs_2 |
| c_addw 100 1 11 ... 01 ... 01 @cs_2 |
| c_j 101 ........... 01 @cj |
| c_beqz 110 ... ... ..... 01 @cb |
| c_bnez 111 ... ... ..... 01 @cb |
| |
| # *** RV64C Standard Extension (Quadrant 2) *** |
| c_slli 000 . ..... ..... 10 @c_shift2 |
| c_fldsp 001 . ..... ..... 10 @c_ld |
| c_lwsp 010 . ..... ..... 10 @c_lw |
| c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32 |
| c_jr_mv 100 0 ..... ..... 10 @cr |
| c_ebreak_jalr_add 100 1 ..... ..... 10 @cr |
| c_fsdsp 101 ...... ..... 10 @c_sd |
| c_swsp 110 . ..... ..... 10 @c_sw |
| c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32 |
