| commit | aecabd50b7432e7173f51b2dd9d845717c6796ea | [log] [tgz] |
|---|---|---|
| author | Wilfred Mallawa <wilfred.mallawa@wdc.com> | Fri Feb 18 16:38:39 2022 +1000 |
| committer | Alistair Francis <alistair.francis@wdc.com> | Thu Mar 03 13:14:50 2022 +1000 |
| tree | 0e3e3631e64dda3544870df1935c288ed88cf599 | |
| parent | 0631aaae31cccf5ae61e8c67c198e064bfaafc66 [diff] |
hw: riscv: opentitan: fixup SPI addresses This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1 base addresses. Also adds these as unimplemented devices. The address references can be found [1]. [1] https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107 Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>