| # AArch64 SVE instruction descriptions |
| # |
| # Copyright (c) 2017 Linaro, Ltd |
| # |
| # This library is free software; you can redistribute it and/or |
| # modify it under the terms of the GNU Lesser General Public |
| # License as published by the Free Software Foundation; either |
| # version 2 of the License, or (at your option) any later version. |
| # |
| # This library is distributed in the hope that it will be useful, |
| # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| # Lesser General Public License for more details. |
| # |
| # You should have received a copy of the GNU Lesser General Public |
| # License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| |
| # |
| # This file is processed by scripts/decodetree.py |
| # |
| |
| ########################################################################### |
| # Named fields. These are primarily for disjoint fields. |
| |
| %imm9_16_10 16:s6 10:3 |
| |
| ########################################################################### |
| # Named attribute sets. These are used to make nice(er) names |
| # when creating helpers common to those for the individual |
| # instruction patterns. |
| |
| &rri rd rn imm |
| &rrr_esz rd rn rm esz |
| |
| ########################################################################### |
| # Named instruction formats. These are generally used to |
| # reduce the amount of duplication between instruction patterns. |
| |
| # Three operand with unused vector element size |
| @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 |
| |
| # Basic Load/Store with 9-bit immediate offset |
| @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ |
| &rri imm=%imm9_16_10 |
| @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ |
| &rri imm=%imm9_16_10 |
| |
| ########################################################################### |
| # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. |
| |
| ### SVE Logical - Unpredicated Group |
| |
| # SVE bitwise logical operations (unpredicated) |
| AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 |
| ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 |
| EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 |
| BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 |
| |
| ### SVE Predicate Misc Group |
| |
| # SVE predicate test |
| PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 |
| |
| ### SVE Memory - 32-bit Gather and Unsized Contiguous Group |
| |
| # SVE load predicate register |
| LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 |
| |
| # SVE load vector register |
| LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 |
