| # SPDX-License-Identifier: LGPL-2.0+ |
| # |
| # Sparc instruction decode definitions. |
| # Copyright (c) 2023 Richard Henderson <rth@twiddle.net> |
| |
| ## |
| ## Major Opcodes 00 and 01 -- branches, call, and sethi. |
| ## |
| |
| &bcc i a cond cc |
| BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc |
| Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0 |
| FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc |
| FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0 |
| |
| %d16 20:s2 0:14 |
| BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 |
| |
| NCP 00 - ---- 111 ---------------------- # CBcc |
| |
| SETHI 00 rd:5 100 i:22 |
| |
| CALL 01 i:s30 |
| |
| ## |
| ## Major Opcode 10 -- integer, floating-point, vis, and system insns. |
| ## |
| |
| &r_r_ri rd rs1 rs2_or_imm imm:bool |
| @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 |
| @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri |
| |
| &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool |
| @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc |
| @r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0 |
| @r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1 |
| |
| &r_r_r rd rs1 rs2 |
| @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r |
| @r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r |
| |
| &r_r rd rs |
| @r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r |
| @r_r2 .. rd:5 ...... ..... . ........ rs:5 &r_r |
| |
| { |
| [ |
| STBAR 10 00000 101000 01111 0 0000000000000 |
| MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 |
| |
| RDCCR 10 rd:5 101000 00010 0 0000000000000 |
| RDASI 10 rd:5 101000 00011 0 0000000000000 |
| RDTICK 10 rd:5 101000 00100 0 0000000000000 |
| RDPC 10 rd:5 101000 00101 0 0000000000000 |
| RDFPRS 10 rd:5 101000 00110 0 0000000000000 |
| RDASR17 10 rd:5 101000 10001 0 0000000000000 |
| RDGSR 10 rd:5 101000 10011 0 0000000000000 |
| RDSOFTINT 10 rd:5 101000 10110 0 0000000000000 |
| RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000 |
| RDSTICK 10 rd:5 101000 11000 0 0000000000000 |
| RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 |
| RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 |
| ] |
| # Before v8, all rs1 accepted; otherwise rs1==0. |
| RDY 10 rd:5 101000 rs1:5 0 0000000000000 |
| } |
| |
| { |
| [ |
| WRY 10 00000 110000 ..... . ............. @n_r_ri |
| WRCCR 10 00010 110000 ..... . ............. @n_r_ri |
| WRASI 10 00011 110000 ..... . ............. @n_r_ri |
| WRFPRS 10 00110 110000 ..... . ............. @n_r_ri |
| { |
| WRGSR 10 10011 110000 ..... . ............. @n_r_ri |
| WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri |
| } |
| WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri |
| WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri |
| WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri |
| WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri |
| WRSTICK 10 11000 110000 ..... . ............. @n_r_ri |
| WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri |
| ] |
| # Before v8, rs1==0 was WRY, and the rest executed as nop. |
| [ |
| NOP_v7 10 ----- 110000 ----- 0 00000000 ----- |
| NOP_v7 10 ----- 110000 ----- 1 -------- ----- |
| ] |
| } |
| |
| { |
| RDPSR 10 rd:5 101001 00000 0 0000000000000 |
| RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 |
| } |
| RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000 |
| RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000 |
| RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 |
| RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 |
| RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 |
| |
| { |
| WRPSR 10 00000 110001 ..... . ............. @n_r_ri |
| SAVED 10 00000 110001 00000 0 0000000000000 |
| } |
| RESTORED 10 00001 110001 00000 0 0000000000000 |
| # UA2005 ALLCLEAN |
| # UA2005 OTHERW |
| # UA2005 NORMALW |
| # UA2005 INVALW |
| |
| { |
| RDWIM 10 rd:5 101010 00000 0 0000000000000 |
| RDPR_tpc 10 rd:5 101010 00000 0 0000000000000 |
| } |
| RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000 |
| RDPR_tstate 10 rd:5 101010 00010 0 0000000000000 |
| RDPR_tt 10 rd:5 101010 00011 0 0000000000000 |
| RDPR_tick 10 rd:5 101010 00100 0 0000000000000 |
| RDPR_tba 10 rd:5 101010 00101 0 0000000000000 |
| RDPR_pstate 10 rd:5 101010 00110 0 0000000000000 |
| RDPR_tl 10 rd:5 101010 00111 0 0000000000000 |
| RDPR_pil 10 rd:5 101010 01000 0 0000000000000 |
| RDPR_cwp 10 rd:5 101010 01001 0 0000000000000 |
| RDPR_cansave 10 rd:5 101010 01010 0 0000000000000 |
| RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000 |
| RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000 |
| RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000 |
| RDPR_wstate 10 rd:5 101010 01110 0 0000000000000 |
| RDPR_gl 10 rd:5 101010 10000 0 0000000000000 |
| RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 |
| RDPR_ver 10 rd:5 101010 11111 0 0000000000000 |
| |
| { |
| WRWIM 10 00000 110010 ..... . ............. @n_r_ri |
| WRPR_tpc 10 00000 110010 ..... . ............. @n_r_ri |
| } |
| WRPR_tnpc 10 00001 110010 ..... . ............. @n_r_ri |
| WRPR_tstate 10 00010 110010 ..... . ............. @n_r_ri |
| WRPR_tt 10 00011 110010 ..... . ............. @n_r_ri |
| WRPR_tick 10 00100 110010 ..... . ............. @n_r_ri |
| WRPR_tba 10 00101 110010 ..... . ............. @n_r_ri |
| WRPR_pstate 10 00110 110010 ..... . ............. @n_r_ri |
| WRPR_tl 10 00111 110010 ..... . ............. @n_r_ri |
| WRPR_pil 10 01000 110010 ..... . ............. @n_r_ri |
| WRPR_cwp 10 01001 110010 ..... . ............. @n_r_ri |
| WRPR_cansave 10 01010 110010 ..... . ............. @n_r_ri |
| WRPR_canrestore 10 01011 110010 ..... . ............. @n_r_ri |
| WRPR_cleanwin 10 01100 110010 ..... . ............. @n_r_ri |
| WRPR_otherwin 10 01101 110010 ..... . ............. @n_r_ri |
| WRPR_wstate 10 01110 110010 ..... . ............. @n_r_ri |
| WRPR_gl 10 10000 110010 ..... . ............. @n_r_ri |
| WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri |
| |
| { |
| FLUSHW 10 00000 101011 00000 0 0000000000000 |
| RDTBR 10 rd:5 101011 00000 0 0000000000000 |
| } |
| |
| { |
| WRTBR 10 00000 110011 ..... . ............. @n_r_ri |
| WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri |
| } |
| WRHPR_htstate 10 00001 110011 ..... . ............. @n_r_ri |
| WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri |
| WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri |
| WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri |
| |
| ADD 10 ..... 0.0000 ..... . ............. @r_r_ri_cc |
| AND 10 ..... 0.0001 ..... . ............. @r_r_ri_cc |
| OR 10 ..... 0.0010 ..... . ............. @r_r_ri_cc |
| XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc |
| SUB 10 ..... 0.0100 ..... . ............. @r_r_ri_cc |
| ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc |
| ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc |
| XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc |
| ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc |
| SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc |
| |
| MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0 |
| UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc |
| SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc |
| MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1 |
| |
| UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0 |
| SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0 |
| UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc |
| SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc |
| |
| TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1 |
| TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1 |
| TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1 |
| TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1 |
| |
| POPC 10 rd:5 101110 00000 imm:1 rs2_or_imm:s13 \ |
| &r_r_ri_cc rs1=0 cc=0 |
| |
| &shiftr rd rs1 rs2 x:bool |
| @shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr |
| |
| SLL_r 10 ..... 100101 ..... 0 . 0000000 ..... @shiftr |
| SRL_r 10 ..... 100110 ..... 0 . 0000000 ..... @shiftr |
| SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr |
| |
| &shifti rd rs1 i x:bool |
| @shifti .. rd:5 ...... rs1:5 . x:1 ...... i:6 &shifti |
| |
| SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti |
| SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti |
| SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti |
| |
| Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 |
| { |
| # For v7, the entire simm13 field is present, but masked to 7 bits. |
| # For v8, [12:7] are reserved. However, a compatibility note for |
| # the Tcc insn in the v9 manual suggests that the v8 reserved field |
| # was ignored and did not produce traps. |
| Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7 |
| |
| # For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0). |
| # Bits [10:8] are reserved and the OSA2011 manual says they must be 0. |
| Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8 |
| } |
| |
| MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11 |
| MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11 |
| MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10 |
| |
| JMPL 10 ..... 111000 ..... . ............. @r_r_ri |
| { |
| RETT 10 00000 111001 ..... . ............. @n_r_ri |
| RETURN 10 00000 111001 ..... . ............. @n_r_ri |
| } |
| NOP 10 00000 111011 ----- 0 00000000----- # FLUSH reg+reg |
| NOP 10 00000 111011 ----- 1 ------------- # FLUSH reg+imm |
| SAVE 10 ..... 111100 ..... . ............. @r_r_ri |
| RESTORE 10 ..... 111101 ..... . ............. @r_r_ri |
| |
| DONE 10 00000 111110 00000 0 0000000000000 |
| RETRY 10 00001 111110 00000 0 0000000000000 |
| |
| FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 |
| FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2 |
| FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @r_r2 |
| FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 |
| FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 |
| FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @r_r2 |
| FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 |
| FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 |
| FABSq 10 ..... 110100 00000 0 0000 1011 ..... @r_r2 |
| FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 |
| FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 |
| FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 |
| FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r |
| FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r |
| FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @r_r_r |
| FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r |
| FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r |
| FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @r_r_r |
| FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r |
| FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r |
| FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @r_r_r |
| FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r |
| FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r |
| FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r |
| FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r |
| FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r |
| FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2 |
| FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 |
| FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_r2 |
| FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 |
| FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 |
| FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @r_r2 |
| FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 |
| FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 |
| FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2 |
| FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 |
| FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 |
| FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2 |
| FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @r_r2 |
| FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @r_r2 |
| FdTOq 10 ..... 110100 00000 0 1100 1110 ..... @r_r2 |
| FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 |
| FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 |
| FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 |
| |
| FMOVscc 10 rd:5 110101 0 cond:4 1 cc:1 0 000001 rs2:5 |
| FMOVdcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000010 rs2:5 |
| FMOVqcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000011 rs2:5 |
| |
| FMOVsfcc 10 rd:5 110101 0 cond:4 0 cc:2 000001 rs2:5 |
| FMOVdfcc 10 rd:5 110101 0 cond:4 0 cc:2 000010 rs2:5 |
| FMOVqfcc 10 rd:5 110101 0 cond:4 0 cc:2 000011 rs2:5 |
| |
| FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5 |
| FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5 |
| FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5 |
| |
| FCMPs 10 000 cc:2 110101 rs1:5 0 0101 0001 rs2:5 |
| FCMPd 10 000 cc:2 110101 rs1:5 0 0101 0010 rs2:5 |
| FCMPq 10 000 cc:2 110101 rs1:5 0 0101 0011 rs2:5 |
| FCMPEs 10 000 cc:2 110101 rs1:5 0 0101 0101 rs2:5 |
| FCMPEd 10 000 cc:2 110101 rs1:5 0 0101 0110 rs2:5 |
| FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 |
| |
| { |
| [ |
| EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r |
| EDGE8N 10 ..... 110110 ..... 0 0000 0001 ..... @r_r_r |
| EDGE8Lcc 10 ..... 110110 ..... 0 0000 0010 ..... @r_r_r |
| EDGE8LN 10 ..... 110110 ..... 0 0000 0011 ..... @r_r_r |
| EDGE16cc 10 ..... 110110 ..... 0 0000 0100 ..... @r_r_r |
| EDGE16N 10 ..... 110110 ..... 0 0000 0101 ..... @r_r_r |
| EDGE16Lcc 10 ..... 110110 ..... 0 0000 0110 ..... @r_r_r |
| EDGE16LN 10 ..... 110110 ..... 0 0000 0111 ..... @r_r_r |
| EDGE32cc 10 ..... 110110 ..... 0 0000 1000 ..... @r_r_r |
| EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r |
| EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r |
| EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r |
| |
| ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r |
| ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r |
| ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r |
| |
| ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r |
| ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r |
| |
| BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r |
| |
| FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_r_r |
| FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_r_r |
| FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_r_r |
| FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_r_r |
| FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_r_r |
| FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_r_r |
| FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_r_r |
| FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_r_r |
| |
| FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r |
| FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r |
| FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r |
| FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @r_r_r |
| FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r |
| FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r |
| FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r |
| FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r |
| FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_r2 |
| FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_r2 |
| PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r |
| |
| FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r |
| FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r |
| BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r |
| FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r |
| |
| FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d |
| FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s |
| FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d |
| FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s |
| FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @r_r1 # FNOT1d |
| FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s |
| FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d |
| FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s |
| |
| FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @r_r_r |
| FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r |
| FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @r_r_r |
| FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r |
| FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @r_r_r |
| FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r |
| FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @r_r_r |
| FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r |
| |
| FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @r_r_r |
| FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r |
| FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @r_r_r # FANDNOT2d |
| FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FANDNOT2s |
| FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @r_r_r_swap # ... 1d |
| FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # ... 1s |
| FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @r_r_r |
| FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r |
| FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @r_r_r |
| FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r |
| FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @r_r_r |
| FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r |
| FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @r_r_r |
| FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r |
| FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @r_r_r # FORNOT2d |
| FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FORNOT2s |
| FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @r_r_r_swap # ... 1d |
| FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # ... 1s |
| FORd 10 ..... 110110 ..... 0 0111 1100 ..... @r_r_r |
| FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r |
| |
| FZEROd 10 rd:5 110110 00000 0 0110 0000 00000 |
| FZEROs 10 rd:5 110110 00000 0 0110 0001 00000 |
| FONEd 10 rd:5 110110 00000 0 0111 1110 00000 |
| FONEs 10 rd:5 110110 00000 0 0111 1111 00000 |
| ] |
| NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 |
| } |
| |
| NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 |
| |
| ## |
| ## Major Opcode 11 -- load and store instructions |
| ## |
| |
| %dfp_rd 25:5 !function=extract_dfpreg |
| %qfp_rd 25:5 !function=extract_qfpreg |
| |
| &r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool |
| @r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi=-1 |
| @d_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \ |
| &r_r_ri_asi rd=%dfp_rd asi=-1 |
| @q_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \ |
| &r_r_ri_asi rd=%qfp_rd asi=-1 |
| |
| @r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0 |
| @r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ |
| &r_r_ri_asi imm=1 asi=-2 |
| @d_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \ |
| &r_r_ri_asi rd=%dfp_rd imm=0 |
| @d_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \ |
| &r_r_ri_asi rd=%dfp_rd imm=1 asi=-2 |
| @q_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \ |
| &r_r_ri_asi rd=%qfp_rd imm=0 |
| @q_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \ |
| &r_r_ri_asi rd=%qfp_rd imm=1 asi=-2 |
| @casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \ |
| &r_r_ri_asi imm=1 asi=-2 |
| |
| LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na |
| LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na |
| LDUH 11 ..... 000010 ..... . ............. @r_r_ri_na |
| LDD 11 ..... 000011 ..... . ............. @r_r_ri_na |
| LDSW 11 ..... 001000 ..... . ............. @r_r_ri_na |
| LDSB 11 ..... 001001 ..... . ............. @r_r_ri_na |
| LDSH 11 ..... 001010 ..... . ............. @r_r_ri_na |
| LDX 11 ..... 001011 ..... . ............. @r_r_ri_na |
| |
| STW 11 ..... 000100 ..... . ............. @r_r_ri_na |
| STB 11 ..... 000101 ..... . ............. @r_r_ri_na |
| STH 11 ..... 000110 ..... . ............. @r_r_ri_na |
| STD 11 ..... 000111 ..... . ............. @r_r_ri_na |
| STX 11 ..... 001110 ..... . ............. @r_r_ri_na |
| |
| LDUW 11 ..... 010000 ..... . ............. @r_r_r_asi # LDUWA |
| LDUW 11 ..... 010000 ..... . ............. @r_r_i_asi # LDUWA |
| LDUB 11 ..... 010001 ..... . ............. @r_r_r_asi # LDUBA |
| LDUB 11 ..... 010001 ..... . ............. @r_r_i_asi # LDUBA |
| LDUH 11 ..... 010010 ..... . ............. @r_r_r_asi # LDUHA |
| LDUH 11 ..... 010010 ..... . ............. @r_r_i_asi # LDUHA |
| LDD 11 ..... 010011 ..... . ............. @r_r_r_asi # LDDA |
| LDD 11 ..... 010011 ..... . ............. @r_r_i_asi # LDDA |
| LDX 11 ..... 011011 ..... . ............. @r_r_r_asi # LDXA |
| LDX 11 ..... 011011 ..... . ............. @r_r_i_asi # LDXA |
| LDSB 11 ..... 011001 ..... . ............. @r_r_r_asi # LDSBA |
| LDSB 11 ..... 011001 ..... . ............. @r_r_i_asi # LDSBA |
| LDSH 11 ..... 011010 ..... . ............. @r_r_r_asi # LDSHA |
| LDSH 11 ..... 011010 ..... . ............. @r_r_i_asi # LDSHA |
| LDSW 11 ..... 011000 ..... . ............. @r_r_r_asi # LDSWA |
| LDSW 11 ..... 011000 ..... . ............. @r_r_i_asi # LDSWA |
| |
| STW 11 ..... 010100 ..... . ............. @r_r_r_asi # STWA |
| STW 11 ..... 010100 ..... . ............. @r_r_i_asi # STWA |
| STB 11 ..... 010101 ..... . ............. @r_r_r_asi # STBA |
| STB 11 ..... 010101 ..... . ............. @r_r_i_asi # STBA |
| STH 11 ..... 010110 ..... . ............. @r_r_r_asi # STHA |
| STH 11 ..... 010110 ..... . ............. @r_r_i_asi # STHA |
| STD 11 ..... 010111 ..... . ............. @r_r_r_asi # STDA |
| STD 11 ..... 010111 ..... . ............. @r_r_i_asi # STDA |
| STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA |
| STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA |
| |
| LDF 11 ..... 100000 ..... . ............. @r_r_ri_na |
| LDFSR 11 00000 100001 ..... . ............. @n_r_ri |
| LDXFSR 11 00001 100001 ..... . ............. @n_r_ri |
| LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na |
| LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na |
| |
| STF 11 ..... 100100 ..... . ............. @r_r_ri_na |
| STFSR 11 00000 100101 ..... . ............. @n_r_ri |
| STXFSR 11 00001 100101 ..... . ............. @n_r_ri |
| { |
| STQF 11 ..... 100110 ..... . ............. @q_r_ri_na |
| STDFQ 11 ----- 100110 ----- - ------------- |
| } |
| STDF 11 ..... 100111 ..... . ............. @d_r_ri_na |
| |
| LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na |
| LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LDSTUBA |
| LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LDSTUBA |
| |
| SWAP 11 ..... 001111 ..... . ............. @r_r_ri_na |
| SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SWAPA |
| SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SWAPA |
| |
| CASA 11 ..... 111100 ..... . ............. @r_r_r_asi |
| CASA 11 ..... 111100 ..... . ............. @casa_imm |
| CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi |
| CASXA 11 ..... 111110 ..... . ............. @casa_imm |
| |
| NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH |
| NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH |
| NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA |
| |
| { |
| [ |
| LDFA 11 ..... 110000 ..... . ............. @r_r_r_asi |
| LDFA 11 ..... 110000 ..... . ............. @r_r_i_asi |
| ] |
| NCP 11 ----- 110000 ----- --------- ----- # v8 LDC |
| } |
| NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR |
| LDQFA 11 ..... 110010 ..... . ............. @q_r_r_asi |
| LDQFA 11 ..... 110010 ..... . ............. @q_r_i_asi |
| { |
| [ |
| LDDFA 11 ..... 110011 ..... . ............. @d_r_r_asi |
| LDDFA 11 ..... 110011 ..... . ............. @d_r_i_asi |
| ] |
| NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC |
| } |
| |
| { |
| [ |
| STFA 11 ..... 110100 ..... . ............. @r_r_r_asi |
| STFA 11 ..... 110100 ..... . ............. @r_r_i_asi |
| ] |
| NCP 11 ----- 110100 ----- --------- ----- # v8 STC |
| } |
| NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR |
| { |
| [ |
| STQFA 11 ..... 110110 ..... . ............. @q_r_r_asi |
| STQFA 11 ..... 110110 ..... . ............. @q_r_i_asi |
| ] |
| NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ |
| } |
| { |
| [ |
| STDFA 11 ..... 110111 ..... . ............. @d_r_r_asi |
| STDFA 11 ..... 110111 ..... . ............. @d_r_i_asi |
| ] |
| NCP 11 ----- 110111 ----- --------- ----- # v8 STDC |
| } |
