blob: fccfc593bd423a6cfbb5b1c51760f09d4afd02bf [file]
/*
* Intel general target stuff that's common to all x86_64 details
*
* Copyright (c) 2022 M. Warner Losh <imp@bsdimp.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef TARGET_H
#define TARGET_H
/*
* x86 doesn't 'lump' the registers for 64-bit args, all args are 64 bits.
*/
static inline bool regpairs_aligned(CPUArchState *env)
{
return false;
}
#endif /* TARGET_H */