| # SPDX-License-Identifier: GPL-2.0-or-later |
| # |
| # LoongArch instruction decode definitions. |
| # |
| # Copyright (c) 2021 Loongson Technology Corporation Limited |
| # |
| |
| # |
| # Fields |
| # |
| %i14s2 10:s14 !function=shl_2 |
| %sa2p1 15:2 !function=plus_1 |
| %offs21 0:s5 10:16 !function=shl_2 |
| %offs16 10:s16 !function=shl_2 |
| %offs26 0:s10 10:16 !function=shl_2 |
| |
| # |
| # Argument sets |
| # |
| &i imm |
| &r_i rd imm |
| &rr rd rj |
| &rr_jk rj rk |
| &rrr rd rj rk |
| &rr_i rd rj imm |
| &hint_r_i hint rj imm |
| &rrr_sa rd rj rk sa |
| &rr_ms_ls rd rj ms ls |
| &ff fd fj |
| &fff fd fj fk |
| &ffff fd fj fk fa |
| &cff_fcond cd fj fk fcond |
| &fffc fd fj fk ca |
| &fr fd rj |
| &rf rd fj |
| &fcsrd_r fcsrd rj |
| &r_fcsrs rd fcsrs |
| &cf cd fj |
| &fc fd cj |
| &cr cd rj |
| &rc rd cj |
| &frr fd rj rk |
| &fr_i fd rj imm |
| &r_offs rj offs |
| &c_offs cj offs |
| &offs offs |
| &rr_offs rj rd offs |
| &r_csr rd csr |
| &rr_csr rd rj csr |
| &empty |
| &i_rr imm rj rk |
| &cop_r_i cop rj imm |
| &j_i rj imm |
| |
| # |
| # Formats |
| # |
| @i15 .... ........ ..... imm:15 &i |
| @rr .... ........ ..... ..... rj:5 rd:5 &rr |
| @rr_jk .... ........ ..... rk:5 rj:5 ..... &rr_jk |
| @rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr |
| @r_i20 .... ... imm:s20 rd:5 &r_i |
| @rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i |
| @rr_ui6 .... ........ .... imm:6 rj:5 rd:5 &rr_i |
| @rr_ui8 .. ........ .... imm:8 rj:5 rd:5 &rr_i |
| @rr_i12 .... ...... imm:s12 rj:5 rd:5 &rr_i |
| @rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i |
| @rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2 |
| @rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i |
| @rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16 |
| @hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i |
| @rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1 |
| @rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa |
| @rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa |
| @rr_2bw .... ....... ms:5 . ls:5 rj:5 rd:5 &rr_ms_ls |
| @rr_2bd .... ...... ms:6 ls:6 rj:5 rd:5 &rr_ms_ls |
| @ff .... ........ ..... ..... fj:5 fd:5 &ff |
| @fff .... ........ ..... fk:5 fj:5 fd:5 &fff |
| @ffff .... ........ fa:5 fk:5 fj:5 fd:5 &ffff |
| @cff_fcond .... ........ fcond:5 fk:5 fj:5 .. cd:3 &cff_fcond |
| @fffc .... ........ .. ca:3 fk:5 fj:5 fd:5 &fffc |
| @fr .... ........ ..... ..... rj:5 fd:5 &fr |
| @rf .... ........ ..... ..... fj:5 rd:5 &rf |
| @fcsrd_r .... ........ ..... ..... rj:5 fcsrd:5 &fcsrd_r |
| @r_fcsrs .... ........ ..... ..... fcsrs:5 rd:5 &r_fcsrs |
| @cf .... ........ ..... ..... fj:5 .. cd:3 &cf |
| @fc .... ........ ..... ..... .. cj:3 fd:5 &fc |
| @cr .... ........ ..... ..... rj:5 .. cd:3 &cr |
| @rc .... ........ ..... ..... .. cj:3 rd:5 &rc |
| @frr .... ........ ..... rk:5 rj:5 fd:5 &frr |
| @fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i |
| @r_offs21 .... .. ................ rj:5 ..... &r_offs offs=%offs21 |
| @c_offs21 .... .. ................ .. cj:3 ..... &c_offs offs=%offs21 |
| @offs26 .... .. .......................... &offs offs=%offs26 |
| @rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16 |
| @r_csr .... .... csr:14 ..... rd:5 &r_csr |
| @rr_csr .... .... csr:14 rj:5 rd:5 &rr_csr |
| @empty .... ........ ..... ..... ..... ..... &empty |
| @i_rr ...... ...... ..... rk:5 rj:5 imm:5 &i_rr |
| @cop_r_i .... ...... imm:s12 rj:5 cop:5 &cop_r_i |
| @j_i .... ........ .. imm:8 rj:5 ..... &j_i |
| |
| # |
| # Fixed point arithmetic operation instruction |
| # |
| add_w 0000 00000001 00000 ..... ..... ..... @rrr |
| add_d 0000 00000001 00001 ..... ..... ..... @rrr |
| sub_w 0000 00000001 00010 ..... ..... ..... @rrr |
| sub_d 0000 00000001 00011 ..... ..... ..... @rrr |
| slt 0000 00000001 00100 ..... ..... ..... @rrr |
| sltu 0000 00000001 00101 ..... ..... ..... @rrr |
| slti 0000 001000 ............ ..... ..... @rr_i12 |
| sltui 0000 001001 ............ ..... ..... @rr_i12 |
| nor 0000 00000001 01000 ..... ..... ..... @rrr |
| and 0000 00000001 01001 ..... ..... ..... @rrr |
| or 0000 00000001 01010 ..... ..... ..... @rrr |
| xor 0000 00000001 01011 ..... ..... ..... @rrr |
| orn 0000 00000001 01100 ..... ..... ..... @rrr |
| andn 0000 00000001 01101 ..... ..... ..... @rrr |
| mul_w 0000 00000001 11000 ..... ..... ..... @rrr |
| mulh_w 0000 00000001 11001 ..... ..... ..... @rrr |
| mulh_wu 0000 00000001 11010 ..... ..... ..... @rrr |
| mul_d 0000 00000001 11011 ..... ..... ..... @rrr |
| mulh_d 0000 00000001 11100 ..... ..... ..... @rrr |
| mulh_du 0000 00000001 11101 ..... ..... ..... @rrr |
| mulw_d_w 0000 00000001 11110 ..... ..... ..... @rrr |
| mulw_d_wu 0000 00000001 11111 ..... ..... ..... @rrr |
| div_w 0000 00000010 00000 ..... ..... ..... @rrr |
| mod_w 0000 00000010 00001 ..... ..... ..... @rrr |
| div_wu 0000 00000010 00010 ..... ..... ..... @rrr |
| mod_wu 0000 00000010 00011 ..... ..... ..... @rrr |
| div_d 0000 00000010 00100 ..... ..... ..... @rrr |
| mod_d 0000 00000010 00101 ..... ..... ..... @rrr |
| div_du 0000 00000010 00110 ..... ..... ..... @rrr |
| mod_du 0000 00000010 00111 ..... ..... ..... @rrr |
| alsl_w 0000 00000000 010 .. ..... ..... ..... @rrr_sa2p1 |
| alsl_wu 0000 00000000 011 .. ..... ..... ..... @rrr_sa2p1 |
| alsl_d 0000 00000010 110 .. ..... ..... ..... @rrr_sa2p1 |
| lu12i_w 0001 010 .................... ..... @r_i20 |
| lu32i_d 0001 011 .................... ..... @r_i20 |
| lu52i_d 0000 001100 ............ ..... ..... @rr_i12 |
| pcaddi 0001 100 .................... ..... @r_i20 |
| pcalau12i 0001 101 .................... ..... @r_i20 |
| pcaddu12i 0001 110 .................... ..... @r_i20 |
| pcaddu18i 0001 111 .................... ..... @r_i20 |
| addi_w 0000 001010 ............ ..... ..... @rr_i12 |
| addi_d 0000 001011 ............ ..... ..... @rr_i12 |
| addu16i_d 0001 00 ................ ..... ..... @rr_i16 |
| andi 0000 001101 ............ ..... ..... @rr_ui12 |
| ori 0000 001110 ............ ..... ..... @rr_ui12 |
| xori 0000 001111 ............ ..... ..... @rr_ui12 |
| |
| # |
| # Fixed point shift operation instruction |
| # |
| sll_w 0000 00000001 01110 ..... ..... ..... @rrr |
| srl_w 0000 00000001 01111 ..... ..... ..... @rrr |
| sra_w 0000 00000001 10000 ..... ..... ..... @rrr |
| sll_d 0000 00000001 10001 ..... ..... ..... @rrr |
| srl_d 0000 00000001 10010 ..... ..... ..... @rrr |
| sra_d 0000 00000001 10011 ..... ..... ..... @rrr |
| rotr_w 0000 00000001 10110 ..... ..... ..... @rrr |
| rotr_d 0000 00000001 10111 ..... ..... ..... @rrr |
| slli_w 0000 00000100 00001 ..... ..... ..... @rr_ui5 |
| slli_d 0000 00000100 0001 ...... ..... ..... @rr_ui6 |
| srli_w 0000 00000100 01001 ..... ..... ..... @rr_ui5 |
| srli_d 0000 00000100 0101 ...... ..... ..... @rr_ui6 |
| srai_w 0000 00000100 10001 ..... ..... ..... @rr_ui5 |
| srai_d 0000 00000100 1001 ...... ..... ..... @rr_ui6 |
| rotri_w 0000 00000100 11001 ..... ..... ..... @rr_ui5 |
| rotri_d 0000 00000100 1101 ...... ..... ..... @rr_ui6 |
| |
| # |
| # Fixed point bit operation instruction |
| # |
| ext_w_h 0000 00000000 00000 10110 ..... ..... @rr |
| ext_w_b 0000 00000000 00000 10111 ..... ..... @rr |
| clo_w 0000 00000000 00000 00100 ..... ..... @rr |
| clz_w 0000 00000000 00000 00101 ..... ..... @rr |
| cto_w 0000 00000000 00000 00110 ..... ..... @rr |
| ctz_w 0000 00000000 00000 00111 ..... ..... @rr |
| clo_d 0000 00000000 00000 01000 ..... ..... @rr |
| clz_d 0000 00000000 00000 01001 ..... ..... @rr |
| cto_d 0000 00000000 00000 01010 ..... ..... @rr |
| ctz_d 0000 00000000 00000 01011 ..... ..... @rr |
| revb_2h 0000 00000000 00000 01100 ..... ..... @rr |
| revb_4h 0000 00000000 00000 01101 ..... ..... @rr |
| revb_2w 0000 00000000 00000 01110 ..... ..... @rr |
| revb_d 0000 00000000 00000 01111 ..... ..... @rr |
| revh_2w 0000 00000000 00000 10000 ..... ..... @rr |
| revh_d 0000 00000000 00000 10001 ..... ..... @rr |
| bitrev_4b 0000 00000000 00000 10010 ..... ..... @rr |
| bitrev_8b 0000 00000000 00000 10011 ..... ..... @rr |
| bitrev_w 0000 00000000 00000 10100 ..... ..... @rr |
| bitrev_d 0000 00000000 00000 10101 ..... ..... @rr |
| bytepick_w 0000 00000000 100 .. ..... ..... ..... @rrr_sa2 |
| bytepick_d 0000 00000000 11 ... ..... ..... ..... @rrr_sa3 |
| maskeqz 0000 00000001 00110 ..... ..... ..... @rrr |
| masknez 0000 00000001 00111 ..... ..... ..... @rrr |
| bstrins_w 0000 0000011 ..... 0 ..... ..... ..... @rr_2bw |
| bstrpick_w 0000 0000011 ..... 1 ..... ..... ..... @rr_2bw |
| bstrins_d 0000 000010 ...... ...... ..... ..... @rr_2bd |
| bstrpick_d 0000 000011 ...... ...... ..... ..... @rr_2bd |
| |
| # |
| # Fixed point load/store instruction |
| # |
| ld_b 0010 100000 ............ ..... ..... @rr_i12 |
| ld_h 0010 100001 ............ ..... ..... @rr_i12 |
| ld_w 0010 100010 ............ ..... ..... @rr_i12 |
| ld_d 0010 100011 ............ ..... ..... @rr_i12 |
| st_b 0010 100100 ............ ..... ..... @rr_i12 |
| st_h 0010 100101 ............ ..... ..... @rr_i12 |
| st_w 0010 100110 ............ ..... ..... @rr_i12 |
| st_d 0010 100111 ............ ..... ..... @rr_i12 |
| ld_bu 0010 101000 ............ ..... ..... @rr_i12 |
| ld_hu 0010 101001 ............ ..... ..... @rr_i12 |
| ld_wu 0010 101010 ............ ..... ..... @rr_i12 |
| ldx_b 0011 10000000 00000 ..... ..... ..... @rrr |
| ldx_h 0011 10000000 01000 ..... ..... ..... @rrr |
| ldx_w 0011 10000000 10000 ..... ..... ..... @rrr |
| ldx_d 0011 10000000 11000 ..... ..... ..... @rrr |
| stx_b 0011 10000001 00000 ..... ..... ..... @rrr |
| stx_h 0011 10000001 01000 ..... ..... ..... @rrr |
| stx_w 0011 10000001 10000 ..... ..... ..... @rrr |
| stx_d 0011 10000001 11000 ..... ..... ..... @rrr |
| ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr |
| ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr |
| ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr |
| preld 0010 101011 ............ ..... ..... @hint_r_i12 |
| dbar 0011 10000111 00100 ............... @i15 |
| ibar 0011 10000111 00101 ............... @i15 |
| ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2 |
| stptr_w 0010 0101 .............. ..... ..... @rr_i14s2 |
| ldptr_d 0010 0110 .............. ..... ..... @rr_i14s2 |
| stptr_d 0010 0111 .............. ..... ..... @rr_i14s2 |
| ldgt_b 0011 10000111 10000 ..... ..... ..... @rrr |
| ldgt_h 0011 10000111 10001 ..... ..... ..... @rrr |
| ldgt_w 0011 10000111 10010 ..... ..... ..... @rrr |
| ldgt_d 0011 10000111 10011 ..... ..... ..... @rrr |
| ldle_b 0011 10000111 10100 ..... ..... ..... @rrr |
| ldle_h 0011 10000111 10101 ..... ..... ..... @rrr |
| ldle_w 0011 10000111 10110 ..... ..... ..... @rrr |
| ldle_d 0011 10000111 10111 ..... ..... ..... @rrr |
| stgt_b 0011 10000111 11000 ..... ..... ..... @rrr |
| stgt_h 0011 10000111 11001 ..... ..... ..... @rrr |
| stgt_w 0011 10000111 11010 ..... ..... ..... @rrr |
| stgt_d 0011 10000111 11011 ..... ..... ..... @rrr |
| stle_b 0011 10000111 11100 ..... ..... ..... @rrr |
| stle_h 0011 10000111 11101 ..... ..... ..... @rrr |
| stle_w 0011 10000111 11110 ..... ..... ..... @rrr |
| stle_d 0011 10000111 11111 ..... ..... ..... @rrr |
| |
| # |
| # Fixed point atomic instruction |
| # |
| ll_w 0010 0000 .............. ..... ..... @rr_i14s2 |
| sc_w 0010 0001 .............. ..... ..... @rr_i14s2 |
| ll_d 0010 0010 .............. ..... ..... @rr_i14s2 |
| sc_d 0010 0011 .............. ..... ..... @rr_i14s2 |
| amswap_w 0011 10000110 00000 ..... ..... ..... @rrr |
| amswap_d 0011 10000110 00001 ..... ..... ..... @rrr |
| amadd_w 0011 10000110 00010 ..... ..... ..... @rrr |
| amadd_d 0011 10000110 00011 ..... ..... ..... @rrr |
| amand_w 0011 10000110 00100 ..... ..... ..... @rrr |
| amand_d 0011 10000110 00101 ..... ..... ..... @rrr |
| amor_w 0011 10000110 00110 ..... ..... ..... @rrr |
| amor_d 0011 10000110 00111 ..... ..... ..... @rrr |
| amxor_w 0011 10000110 01000 ..... ..... ..... @rrr |
| amxor_d 0011 10000110 01001 ..... ..... ..... @rrr |
| ammax_w 0011 10000110 01010 ..... ..... ..... @rrr |
| ammax_d 0011 10000110 01011 ..... ..... ..... @rrr |
| ammin_w 0011 10000110 01100 ..... ..... ..... @rrr |
| ammin_d 0011 10000110 01101 ..... ..... ..... @rrr |
| ammax_wu 0011 10000110 01110 ..... ..... ..... @rrr |
| ammax_du 0011 10000110 01111 ..... ..... ..... @rrr |
| ammin_wu 0011 10000110 10000 ..... ..... ..... @rrr |
| ammin_du 0011 10000110 10001 ..... ..... ..... @rrr |
| amswap_db_w 0011 10000110 10010 ..... ..... ..... @rrr |
| amswap_db_d 0011 10000110 10011 ..... ..... ..... @rrr |
| amadd_db_w 0011 10000110 10100 ..... ..... ..... @rrr |
| amadd_db_d 0011 10000110 10101 ..... ..... ..... @rrr |
| amand_db_w 0011 10000110 10110 ..... ..... ..... @rrr |
| amand_db_d 0011 10000110 10111 ..... ..... ..... @rrr |
| amor_db_w 0011 10000110 11000 ..... ..... ..... @rrr |
| amor_db_d 0011 10000110 11001 ..... ..... ..... @rrr |
| amxor_db_w 0011 10000110 11010 ..... ..... ..... @rrr |
| amxor_db_d 0011 10000110 11011 ..... ..... ..... @rrr |
| ammax_db_w 0011 10000110 11100 ..... ..... ..... @rrr |
| ammax_db_d 0011 10000110 11101 ..... ..... ..... @rrr |
| ammin_db_w 0011 10000110 11110 ..... ..... ..... @rrr |
| ammin_db_d 0011 10000110 11111 ..... ..... ..... @rrr |
| ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr |
| ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr |
| ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr |
| ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr |
| |
| # |
| # Fixed point extra instruction |
| # |
| crc_w_b_w 0000 00000010 01000 ..... ..... ..... @rrr |
| crc_w_h_w 0000 00000010 01001 ..... ..... ..... @rrr |
| crc_w_w_w 0000 00000010 01010 ..... ..... ..... @rrr |
| crc_w_d_w 0000 00000010 01011 ..... ..... ..... @rrr |
| crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @rrr |
| crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @rrr |
| crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @rrr |
| crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @rrr |
| break 0000 00000010 10100 ............... @i15 |
| syscall 0000 00000010 10110 ............... @i15 |
| asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk |
| asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk |
| rdtimel_w 0000 00000000 00000 11000 ..... ..... @rr |
| rdtimeh_w 0000 00000000 00000 11001 ..... ..... @rr |
| rdtime_d 0000 00000000 00000 11010 ..... ..... @rr |
| cpucfg 0000 00000000 00000 11011 ..... ..... @rr |
| |
| # |
| # Floating point arithmetic operation instruction |
| # |
| fadd_s 0000 00010000 00001 ..... ..... ..... @fff |
| fadd_d 0000 00010000 00010 ..... ..... ..... @fff |
| fsub_s 0000 00010000 00101 ..... ..... ..... @fff |
| fsub_d 0000 00010000 00110 ..... ..... ..... @fff |
| fmul_s 0000 00010000 01001 ..... ..... ..... @fff |
| fmul_d 0000 00010000 01010 ..... ..... ..... @fff |
| fdiv_s 0000 00010000 01101 ..... ..... ..... @fff |
| fdiv_d 0000 00010000 01110 ..... ..... ..... @fff |
| fmadd_s 0000 10000001 ..... ..... ..... ..... @ffff |
| fmadd_d 0000 10000010 ..... ..... ..... ..... @ffff |
| fmsub_s 0000 10000101 ..... ..... ..... ..... @ffff |
| fmsub_d 0000 10000110 ..... ..... ..... ..... @ffff |
| fnmadd_s 0000 10001001 ..... ..... ..... ..... @ffff |
| fnmadd_d 0000 10001010 ..... ..... ..... ..... @ffff |
| fnmsub_s 0000 10001101 ..... ..... ..... ..... @ffff |
| fnmsub_d 0000 10001110 ..... ..... ..... ..... @ffff |
| fmax_s 0000 00010000 10001 ..... ..... ..... @fff |
| fmax_d 0000 00010000 10010 ..... ..... ..... @fff |
| fmin_s 0000 00010000 10101 ..... ..... ..... @fff |
| fmin_d 0000 00010000 10110 ..... ..... ..... @fff |
| fmaxa_s 0000 00010000 11001 ..... ..... ..... @fff |
| fmaxa_d 0000 00010000 11010 ..... ..... ..... @fff |
| fmina_s 0000 00010000 11101 ..... ..... ..... @fff |
| fmina_d 0000 00010000 11110 ..... ..... ..... @fff |
| fabs_s 0000 00010001 01000 00001 ..... ..... @ff |
| fabs_d 0000 00010001 01000 00010 ..... ..... @ff |
| fneg_s 0000 00010001 01000 00101 ..... ..... @ff |
| fneg_d 0000 00010001 01000 00110 ..... ..... @ff |
| fsqrt_s 0000 00010001 01000 10001 ..... ..... @ff |
| fsqrt_d 0000 00010001 01000 10010 ..... ..... @ff |
| frecip_s 0000 00010001 01000 10101 ..... ..... @ff |
| frecip_d 0000 00010001 01000 10110 ..... ..... @ff |
| frsqrt_s 0000 00010001 01000 11001 ..... ..... @ff |
| frsqrt_d 0000 00010001 01000 11010 ..... ..... @ff |
| fscaleb_s 0000 00010001 00001 ..... ..... ..... @fff |
| fscaleb_d 0000 00010001 00010 ..... ..... ..... @fff |
| flogb_s 0000 00010001 01000 01001 ..... ..... @ff |
| flogb_d 0000 00010001 01000 01010 ..... ..... @ff |
| fcopysign_s 0000 00010001 00101 ..... ..... ..... @fff |
| fcopysign_d 0000 00010001 00110 ..... ..... ..... @fff |
| fclass_s 0000 00010001 01000 01101 ..... ..... @ff |
| fclass_d 0000 00010001 01000 01110 ..... ..... @ff |
| |
| # |
| # Floating point compare instruction |
| # |
| fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @cff_fcond |
| fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @cff_fcond |
| |
| # |
| # Floating point conversion instruction |
| # |
| fcvt_s_d 0000 00010001 10010 00110 ..... ..... @ff |
| fcvt_d_s 0000 00010001 10010 01001 ..... ..... @ff |
| ftintrm_w_s 0000 00010001 10100 00001 ..... ..... @ff |
| ftintrm_w_d 0000 00010001 10100 00010 ..... ..... @ff |
| ftintrm_l_s 0000 00010001 10100 01001 ..... ..... @ff |
| ftintrm_l_d 0000 00010001 10100 01010 ..... ..... @ff |
| ftintrp_w_s 0000 00010001 10100 10001 ..... ..... @ff |
| ftintrp_w_d 0000 00010001 10100 10010 ..... ..... @ff |
| ftintrp_l_s 0000 00010001 10100 11001 ..... ..... @ff |
| ftintrp_l_d 0000 00010001 10100 11010 ..... ..... @ff |
| ftintrz_w_s 0000 00010001 10101 00001 ..... ..... @ff |
| ftintrz_w_d 0000 00010001 10101 00010 ..... ..... @ff |
| ftintrz_l_s 0000 00010001 10101 01001 ..... ..... @ff |
| ftintrz_l_d 0000 00010001 10101 01010 ..... ..... @ff |
| ftintrne_w_s 0000 00010001 10101 10001 ..... ..... @ff |
| ftintrne_w_d 0000 00010001 10101 10010 ..... ..... @ff |
| ftintrne_l_s 0000 00010001 10101 11001 ..... ..... @ff |
| ftintrne_l_d 0000 00010001 10101 11010 ..... ..... @ff |
| ftint_w_s 0000 00010001 10110 00001 ..... ..... @ff |
| ftint_w_d 0000 00010001 10110 00010 ..... ..... @ff |
| ftint_l_s 0000 00010001 10110 01001 ..... ..... @ff |
| ftint_l_d 0000 00010001 10110 01010 ..... ..... @ff |
| ffint_s_w 0000 00010001 11010 00100 ..... ..... @ff |
| ffint_s_l 0000 00010001 11010 00110 ..... ..... @ff |
| ffint_d_w 0000 00010001 11010 01000 ..... ..... @ff |
| ffint_d_l 0000 00010001 11010 01010 ..... ..... @ff |
| frint_s 0000 00010001 11100 10001 ..... ..... @ff |
| frint_d 0000 00010001 11100 10010 ..... ..... @ff |
| |
| # |
| # Floating point move instruction |
| # |
| fmov_s 0000 00010001 01001 00101 ..... ..... @ff |
| fmov_d 0000 00010001 01001 00110 ..... ..... @ff |
| fsel 0000 11010000 00 ... ..... ..... ..... @fffc |
| movgr2fr_w 0000 00010001 01001 01001 ..... ..... @fr |
| movgr2fr_d 0000 00010001 01001 01010 ..... ..... @fr |
| movgr2frh_w 0000 00010001 01001 01011 ..... ..... @fr |
| movfr2gr_s 0000 00010001 01001 01101 ..... ..... @rf |
| movfr2gr_d 0000 00010001 01001 01110 ..... ..... @rf |
| movfrh2gr_s 0000 00010001 01001 01111 ..... ..... @rf |
| movgr2fcsr 0000 00010001 01001 10000 ..... ..... @fcsrd_r |
| movfcsr2gr 0000 00010001 01001 10010 ..... ..... @r_fcsrs |
| movfr2cf 0000 00010001 01001 10100 ..... 00 ... @cf |
| movcf2fr 0000 00010001 01001 10101 00 ... ..... @fc |
| movgr2cf 0000 00010001 01001 10110 ..... 00 ... @cr |
| movcf2gr 0000 00010001 01001 10111 00 ... ..... @rc |
| |
| # |
| # Floating point load/store instruction |
| # |
| fld_s 0010 101100 ............ ..... ..... @fr_i12 |
| fst_s 0010 101101 ............ ..... ..... @fr_i12 |
| fld_d 0010 101110 ............ ..... ..... @fr_i12 |
| fst_d 0010 101111 ............ ..... ..... @fr_i12 |
| fldx_s 0011 10000011 00000 ..... ..... ..... @frr |
| fldx_d 0011 10000011 01000 ..... ..... ..... @frr |
| fstx_s 0011 10000011 10000 ..... ..... ..... @frr |
| fstx_d 0011 10000011 11000 ..... ..... ..... @frr |
| fldgt_s 0011 10000111 01000 ..... ..... ..... @frr |
| fldgt_d 0011 10000111 01001 ..... ..... ..... @frr |
| fldle_s 0011 10000111 01010 ..... ..... ..... @frr |
| fldle_d 0011 10000111 01011 ..... ..... ..... @frr |
| fstgt_s 0011 10000111 01100 ..... ..... ..... @frr |
| fstgt_d 0011 10000111 01101 ..... ..... ..... @frr |
| fstle_s 0011 10000111 01110 ..... ..... ..... @frr |
| fstle_d 0011 10000111 01111 ..... ..... ..... @frr |
| |
| # |
| # Branch instructions |
| # |
| beqz 0100 00 ................ ..... ..... @r_offs21 |
| bnez 0100 01 ................ ..... ..... @r_offs21 |
| bceqz 0100 10 ................ 00 ... ..... @c_offs21 |
| bcnez 0100 10 ................ 01 ... ..... @c_offs21 |
| jirl 0100 11 ................ ..... ..... @rr_i16s2 |
| b 0101 00 .......................... @offs26 |
| bl 0101 01 .......................... @offs26 |
| beq 0101 10 ................ ..... ..... @rr_offs16 |
| bne 0101 11 ................ ..... ..... @rr_offs16 |
| blt 0110 00 ................ ..... ..... @rr_offs16 |
| bge 0110 01 ................ ..... ..... @rr_offs16 |
| bltu 0110 10 ................ ..... ..... @rr_offs16 |
| bgeu 0110 11 ................ ..... ..... @rr_offs16 |
| |
| # |
| # Core instructions |
| # |
| { |
| csrrd 0000 0100 .............. 00000 ..... @r_csr |
| csrwr 0000 0100 .............. 00001 ..... @r_csr |
| csrxchg 0000 0100 .............. ..... ..... @rr_csr |
| } |
| |
| iocsrrd_b 0000 01100100 10000 00000 ..... ..... @rr |
| iocsrrd_h 0000 01100100 10000 00001 ..... ..... @rr |
| iocsrrd_w 0000 01100100 10000 00010 ..... ..... @rr |
| iocsrrd_d 0000 01100100 10000 00011 ..... ..... @rr |
| iocsrwr_b 0000 01100100 10000 00100 ..... ..... @rr |
| iocsrwr_h 0000 01100100 10000 00101 ..... ..... @rr |
| iocsrwr_w 0000 01100100 10000 00110 ..... ..... @rr |
| iocsrwr_d 0000 01100100 10000 00111 ..... ..... @rr |
| tlbsrch 0000 01100100 10000 01010 00000 00000 @empty |
| tlbrd 0000 01100100 10000 01011 00000 00000 @empty |
| tlbwr 0000 01100100 10000 01100 00000 00000 @empty |
| tlbfill 0000 01100100 10000 01101 00000 00000 @empty |
| tlbclr 0000 01100100 10000 01000 00000 00000 @empty |
| tlbflush 0000 01100100 10000 01001 00000 00000 @empty |
| invtlb 0000 01100100 10011 ..... ..... ..... @i_rr |
| cacop 0000 011000 ............ ..... ..... @cop_r_i |
| lddir 0000 01100100 00 ........ ..... ..... @rr_ui8 |
| ldpte 0000 01100100 01 ........ ..... 00000 @j_i |
| ertn 0000 01100100 10000 01110 00000 00000 @empty |
| idle 0000 01100100 10001 ............... @i15 |
| dbcl 0000 00000010 10101 ............... @i15 |
