target/ppc: Convert cache instructions to decodetree

Convert cache management instructions to decodetree using custom
X-form layouts (@X_ea, @X_l, @X_th) and dedicated translation functions.
This ensures reserved bits are accurately represented and ignored by
the decoder (using '-' in the patterns), rather than being erroneously
parsed into instruction fields.

Legacy GEN_HANDLER-based implementations are removed.

The implementation preserves legacy semantics, including:
  - MMU-visible accesses for instructions treated as loads
    (e.g. dcbt, dcbtst, dcbtep, dcbtstep)
  - Supervisor and BookE-specific constraints
  - Effective address computation via do_ea_calc()

Instructions that were defined as no-ops in the legacy implementation
remain no-ops here.

Note on intentional behavior changes:
  - dcbf now validates the L field against the Power ISA v3.1 set of
    legal values (0, 1, 3, 4, 6).
  - Reserved bits that were previously encoded as part of the opcode
    mask (and trapped if set) are now properly decoded as "don't care"
    ('-' in the pattern).

Testing:
  - Verified TCG equivalence for all cache operations

Signed-off-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com>
Tested-by: Tasmiya Nalatwad <tasmiya@linux.ibm.com>
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Tested-by: Aniket Sahu <asahu1x@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260827133010.278889-4-rathc@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>