)]}'
{
  "commit": "4e5b00a820efa3e5746bbac6b019ca4ba9bafe7d",
  "tree": "9ebc14b1c8bc0d354f66fbda9109c66283b0b879",
  "parents": [
    "57432acb9cc84ac8b791bccdd60dc158de0be324"
  ],
  "author": {
    "name": "Nikhil Kumar Singh",
    "email": "nikhilks@linux.ibm.com",
    "time": "Thu Aug 27 18:59:18 2026 +0530"
  },
  "committer": {
    "name": "Harsh Prateek Bora",
    "email": "harshpb@linux.ibm.com",
    "time": "Fri Aug 28 11:03:00 2026 +0530"
  },
  "message": "target/ppc: Convert cache instructions to decodetree\n\nConvert cache management instructions to decodetree using custom\nX-form layouts (@X_ea, @X_l, @X_th) and dedicated translation functions.\nThis ensures reserved bits are accurately represented and ignored by\nthe decoder (using \u0027-\u0027 in the patterns), rather than being erroneously\nparsed into instruction fields.\n\nLegacy GEN_HANDLER-based implementations are removed.\n\nThe implementation preserves legacy semantics, including:\n  - MMU-visible accesses for instructions treated as loads\n    (e.g. dcbt, dcbtst, dcbtep, dcbtstep)\n  - Supervisor and BookE-specific constraints\n  - Effective address computation via do_ea_calc()\n\nInstructions that were defined as no-ops in the legacy implementation\nremain no-ops here.\n\nNote on intentional behavior changes:\n  - dcbf now validates the L field against the Power ISA v3.1 set of\n    legal values (0, 1, 3, 4, 6).\n  - Reserved bits that were previously encoded as part of the opcode\n    mask (and trapped if set) are now properly decoded as \"don\u0027t care\"\n    (\u0027-\u0027 in the pattern).\n\nTesting:\n  - Verified TCG equivalence for all cache operations\n\nSigned-off-by: Nikhil Kumar Singh \u003cnikhilks@linux.ibm.com\u003e\nTested-by: Tasmiya Nalatwad \u003ctasmiya@linux.ibm.com\u003e\nReviewed-by: Glenn Miles \u003cmilesg@linux.ibm.com\u003e\nSigned-off-by: Chinmay Rath \u003crathc@linux.ibm.com\u003e\nReviewed-by: Amit Machhiwal \u003camachhiw@linux.ibm.com\u003e\nTested-by: Aniket Sahu \u003casahu1x@linux.ibm.com\u003e\nLink: https://lore.kernel.org/qemu-devel/20260827133010.278889-4-rathc@linux.ibm.com\nSigned-off-by: Harsh Prateek Bora \u003charshpb@linux.ibm.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6b2d19a3ad9bad68cb5be775f7b4842621013b8b",
      "old_mode": 33188,
      "old_path": "target/ppc/helper.h",
      "new_id": "82ec3a471b64712a71c92bd0bb996ef3a851e5d7",
      "new_mode": 33188,
      "new_path": "target/ppc/helper.h"
    },
    {
      "type": "modify",
      "old_id": "26948e08a76a701857ab7c9501d371c80e8d8a20",
      "old_mode": 33188,
      "old_path": "target/ppc/insn32.decode",
      "new_id": "92706e2097c0d47636babf6daa7beac2fa2babed",
      "new_mode": 33188,
      "new_path": "target/ppc/insn32.decode"
    },
    {
      "type": "modify",
      "old_id": "787ba2cdec59b2b130c21350584cc0a0326303a3",
      "old_mode": 33188,
      "old_path": "target/ppc/mem_helper.c",
      "new_id": "8ad6945590a7e28eba6499ed684184bda2273e88",
      "new_mode": 33188,
      "new_path": "target/ppc/mem_helper.c"
    },
    {
      "type": "modify",
      "old_id": "69c4443ddacd4bbf841d5dcd37c96ef5aa589617",
      "old_mode": 33188,
      "old_path": "target/ppc/translate.c",
      "new_id": "4bd7f44b3c8c4d55fb487cca0772cb1cfa28e855",
      "new_mode": 33188,
      "new_path": "target/ppc/translate.c"
    }
  ]
}