| # See docs/devel/tracing.rst for syntax documentation. |
| |
| # slavio_timer.c |
| slavio_timer_get_out(uint64_t limit, uint32_t counthigh, uint32_t count) "limit 0x%"PRIx64" count 0x%x0x%08x" |
| slavio_timer_irq(uint32_t counthigh, uint32_t count) "callback: count 0x%x0x%08x" |
| slavio_timer_mem_readl_invalid(uint64_t addr) "invalid read address 0x%"PRIx64 |
| slavio_timer_mem_readl(uint64_t addr, uint32_t ret) "read 0x%"PRIx64" = 0x%08x" |
| slavio_timer_mem_writel(uint64_t addr, uint32_t val) "write 0x%"PRIx64" = 0x%08x" |
| slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer set to 0x%016"PRIx64 |
| slavio_timer_mem_writel_counter_invalid(void) "not user timer" |
| slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started" |
| slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped" |
| slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer" |
| slavio_timer_mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter" |
| slavio_timer_mem_writel_mode_invalid(void) "not system timer" |
| slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address 0x%"PRIx64 |
| |
| # grlib_gptimer.c |
| grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run" |
| grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x" |
| grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x" |
| grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq:%uHz" |
| grlib_gptimer_hit(int id) "timer:%d HIT" |
| grlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" |
| grlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x" |
| |
| # aspeed_timer.c |
| aspeed_timer_ctrl_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" |
| aspeed_timer_ctrl_external_clock(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" |
| aspeed_timer_ctrl_overflow_interrupt(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" |
| aspeed_timer_ctrl_pulse_enable(uint8_t i, bool enable) "Timer %" PRIu8 ": %d" |
| aspeed_timer_set_ctrl2(uint32_t value) "Value: 0x%" PRIx32 |
| aspeed_timer_set_value(int timer, int reg, uint32_t value) "Timer %d register %d: 0x%" PRIx32 |
| aspeed_timer_read(uint64_t offset, unsigned size, uint64_t value) "From 0x%" PRIx64 ": of size %u: 0x%" PRIx64 |
| |
| # armv7m_systick.c |
| systick_reload(void) "systick reload" |
| systick_timer_tick(void) "systick tick" |
| systick_read(uint64_t addr, uint32_t value, unsigned size) "systick read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" |
| systick_write(uint64_t addr, uint32_t value, unsigned size) "systick write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" |
| |
| # cmsdk-apb-timer.c |
| cmsdk_apb_timer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| cmsdk_apb_timer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| cmsdk_apb_timer_reset(void) "CMSDK APB timer: reset" |
| |
| # cmsdk-apb-dualtimer.c |
| cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset" |
| |
| # imx_gpt.c |
| imx_gpt_set_freq(uint32_t clksrc, uint32_t freq) "Setting clksrc %u to %u Hz" |
| imx_gpt_read(const char *name, uint64_t value) "%s -> 0x%08" PRIx64 |
| imx_gpt_write(const char *name, uint64_t value) "%s <- 0x%08" PRIx64 |
| imx_gpt_timeout(void) "" |
| |
| # npcm7xx_timer.c |
| npcm7xx_timer_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 |
| npcm7xx_timer_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64 |
| npcm7xx_timer_irq(const char *id, int timer, int state) "%s timer %d state %d" |
| |
| # nrf51_timer.c |
| nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" |
| nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" |
| nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u count 0x%" PRIx32 |
| |
| # bcm2835_systmr.c |
| bcm2835_systmr_timer_expired(unsigned id) "timer #%u expired" |
| bcm2835_systmr_irq_ack(unsigned id) "timer #%u acked" |
| bcm2835_systmr_read(uint64_t offset, uint64_t data) "timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 |
| bcm2835_systmr_write(uint64_t offset, uint32_t data) "timer write: offset 0x%" PRIx64 " data 0x%" PRIx32 |
| bcm2835_systmr_run(unsigned id, uint64_t delay_us) "timer #%u expiring in %"PRIu64" us" |
| |
| # avr_timer16.c |
| avr_timer16_read(uint8_t addr, uint8_t value) "timer16 read addr:%u value:%u" |
| avr_timer16_read_ifr(uint8_t value) "timer16 read addr:ifr value:%u" |
| avr_timer16_read_imsk(uint8_t value) "timer16 read addr:imsk value:%u" |
| avr_timer16_write(uint8_t addr, uint8_t value) "timer16 write addr:%u value:%u" |
| avr_timer16_write_imsk(uint8_t value) "timer16 write addr:imsk value:%u" |
| avr_timer16_interrupt_count(uint8_t cnt) "count: %u" |
| avr_timer16_interrupt_overflow(const char *reason) "overflow: %s" |
| avr_timer16_next_alarm(uint64_t delay_ns) "next alarm: %" PRIu64 " ns from now" |
| avr_timer16_clksrc_update(uint64_t freq_hz, uint64_t period_ns, uint64_t delay_s) "timer frequency: %" PRIu64 " Hz, period: %" PRIu64 " ns (%" PRId64 " us)" |
| |
| # sse_counter.c |
| sse_counter_control_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter control frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| sse_counter_control_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter control framen write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| sse_counter_status_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status frame read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| sse_counter_status_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status frame write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| sse_counter_reset(void) "SSE system counter: reset" |
| |
| # sse_timer.c |
| sse_timer_read(uint64_t offset, uint64_t data, unsigned size) "SSE system timer read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| sse_timer_write(uint64_t offset, uint64_t data, unsigned size) "SSE system timer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" |
| sse_timer_reset(void) "SSE system timer: reset" |
| |
| # sifive_pwm.c |
| sifive_pwm_set_alarm(uint64_t alarm, uint64_t now) "Setting alarm to: 0x%" PRIx64 ", now: 0x%" PRIx64 |
| sifive_pwm_interrupt(int num) "Interrupt %d" |
| sifive_pwm_read(uint64_t offset) "Read at address: 0x%" PRIx64 |
| sifive_pwm_write(uint64_t data, uint64_t offset) "Write 0x%" PRIx64 " at address: 0x%" PRIx64 |
| |
| # sh_timer.c |
| sh_timer_start_stop(int enable, int current) "%d (%d)" |
| sh_timer_read(uint64_t offset) "tmu012_read 0x%" PRIx64 |
| sh_timer_write(uint64_t offset, uint64_t value) "tmu012_write 0x%" PRIx64 " 0x%08" PRIx64 |
| |
| # hpet.c |
| hpet_timer_id_out_of_range(uint8_t timer_id) "timer id out of range: 0x%" PRIx8 |
| hpet_invalid_hpet_cfg(uint8_t reg_off) "invalid HPET_CFG + %u" PRIx8 |
| hpet_ram_read(uint64_t addr) "enter hpet_ram_readl at 0x%" PRIx64 |
| hpet_ram_read_reading_counter(uint8_t reg_off, uint64_t cur_tick) "reading counter + %" PRIu8 " = 0x%" PRIx64 |
| hpet_ram_read_invalid(void) "invalid hpet_ram_readl" |
| hpet_ram_write(uint64_t addr, uint64_t value) "enter hpet_ram_writel at 0x%" PRIx64 " = 0x%" PRIx64 |
| hpet_ram_write_timer_id(uint64_t timer_id) "hpet_ram_writel timer_id = 0x%" PRIx64 |
| hpet_ram_write_tn_cfg(uint8_t reg_off) "hpet_ram_writel HPET_TN_CFG + %" PRIu8 |
| hpet_ram_write_tn_cmp(uint8_t reg_off) "hpet_ram_writel HPET_TN_CMP + %" PRIu8 |
| hpet_ram_write_invalid_tn_cmp(void) "invalid HPET_TN_CMP + 4 write" |
| hpet_ram_write_invalid(void) "invalid hpet_ram_writel" |
| hpet_ram_write_counter_write_while_enabled(void) "Writing counter while HPET enabled!" |
| hpet_ram_write_counter_written(uint8_t reg_off, uint64_t value, uint64_t counter) "HPET counter + %" PRIu8 "written. crt = 0x%" PRIx64 " -> 0x%" PRIx64 |
