commit 3cc050c54008d4e2a12ad3f4dbec9e24ad27bf1a
author Richard Henderson <richard.henderson@linaro.org> Wed Aug 14 07:01:00 2024 +1000
committer Richard Henderson <richard.henderson@linaro.org> Wed Aug 14 07:01:00 2024 +1000
tree ac0ca77d438d5a327a5a3360d693a9fe5b10946e
parent 9eb51530c12ae645b91e308d16196c68563ea883
parent 4c2c0474693229c1f533239bb983495c5427784d

Merge tag 'pull-target-arm-20240813' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values
 * target/arm: Clear high SVE elements in handle_vec_simd_wshli
 * target/arm: Fix usage of MMU indexes when EL3 is AArch32

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# gpg: Signature made Wed 14 Aug 2024 01:17:54 AM AEST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20240813' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Fix usage of MMU indexes when EL3 is AArch32
  target/arm: Update translation regime comment for new features
  target/arm: Clear high SVE elements in handle_vec_simd_wshli
  hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>