)]}'
{
  "commit": "3cc050c54008d4e2a12ad3f4dbec9e24ad27bf1a",
  "tree": "ac0ca77d438d5a327a5a3360d693a9fe5b10946e",
  "parents": [
    "9eb51530c12ae645b91e308d16196c68563ea883",
    "4c2c0474693229c1f533239bb983495c5427784d"
  ],
  "author": {
    "name": "Richard Henderson",
    "email": "richard.henderson@linaro.org",
    "time": "Wed Aug 14 07:01:00 2024 +1000"
  },
  "committer": {
    "name": "Richard Henderson",
    "email": "richard.henderson@linaro.org",
    "time": "Wed Aug 14 07:01:00 2024 +1000"
  },
  "message": "Merge tag \u0027pull-target-arm-20240813\u0027 of https://git.linaro.org/people/pmaydell/qemu-arm into staging\n\ntarget-arm queue:\n * hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values\n * target/arm: Clear high SVE elements in handle_vec_simd_wshli\n * target/arm: Fix usage of MMU indexes when EL3 is AArch32\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAma7eSIZHHBldGVyLm1h\n# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gbJEACHhZAvP4f1vic8DNGPw8Yr\n# v+pRQON+vF+PDBSyNkYCRL5Gy1P257Aujw1ed2dpoDhMemC/co67W2zdzToCvDd5\n# XZxlHb/iUCTeZbA/Zp66ZADlvVOdvvQL8EHbd4mSBEZp9rvPSmxatx4I5jstLiAV\n# 5HimP+AjjGMfklMu+RelW7A7WDRJ0h7F4PwXCA8tLeHPH5XHSkweGYt3OVfSlUAs\n# +RKiltByC/quujLHxrQcVtLZON1KKiB0P8VPRcaR1QIFARiR1IfLvzhKVpqyOlnV\n# 3a+ZILtCJE1YEM+h7Aunz/l9MQ0DZe5DzbIdKOQ7NUkerlhq81kriPp67yLv25lk\n# zgqkHGGDEnIGpSXdmbXTNLcGlH+5O+fWl2RMzYrSFJqvwyRu9egLLi6E0xaNCRvY\n# gdb6CGPhhu21C1o5Nax0CiaZe3vzzRvC5QsIJ0yww6y7VaGFVt/XRaKBdLHB97nZ\n# t/9ifa3fmhVEW6pQEy8VdAeFoxIT2lJ2xJgBdMwpZCJlCxB8xKU/rZfrXKS/UUqV\n# 9Klbcfrx1WFT7zrAWS0Ig7nPttJ+XgjYfgHI3q2e80F6xRmAmaAjnbtVRS+L3It9\n# eZ4SmuzurWipRLpdmxdOX1IXdZD9rJMzk9IUIZoklctlR/D+75Iuy0N7gY8G2dbp\n# fmh38lEQZ0IC90VmNtWltw\u003d\u003d\n# \u003dSo/3\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Wed 14 Aug 2024 01:17:54 AM AEST\n# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE\n# gpg:                issuer \"peter.maydell@linaro.org\"\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@gmail.com\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@chiark.greenend.org.uk\u003e\" [full]\n# gpg:                 aka \"Peter Maydell \u003cpeter@archaic.org.uk\u003e\" [unknown]\n\n* tag \u0027pull-target-arm-20240813\u0027 of https://git.linaro.org/people/pmaydell/qemu-arm:\n  target/arm: Fix usage of MMU indexes when EL3 is AArch32\n  target/arm: Update translation regime comment for new features\n  target/arm: Clear high SVE elements in handle_vec_simd_wshli\n  hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values\n\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n",
  "tree_diff": []
}