| # M-profile MVE instruction descriptions |
| # |
| # Copyright (c) 2021 Linaro, Ltd |
| # |
| # This library is free software; you can redistribute it and/or |
| # modify it under the terms of the GNU Lesser General Public |
| # License as published by the Free Software Foundation; either |
| # version 2.1 of the License, or (at your option) any later version. |
| # |
| # This library is distributed in the hope that it will be useful, |
| # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| # Lesser General Public License for more details. |
| # |
| # You should have received a copy of the GNU Lesser General Public |
| # License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| |
| # |
| # This file is processed by scripts/decodetree.py |
| # |
| |
| %qd 22:1 13:3 |
| %qm 5:1 1:3 |
| %qn 7:1 17:3 |
| |
| # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit |
| %size_28 28:1 !function=plus_1 |
| |
| &vldr_vstr rn qd imm p a w size l u |
| &1op qd qm size |
| &2op qd qm qn size |
| &2scalar qd qn rm size |
| |
| @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 |
| # Note that both Rn and Qd are 3 bits only (no D bit) |
| @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr |
| |
| @1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm |
| @1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0 |
| @2op .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn |
| @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 |
| |
| @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn |
| @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn |
| |
| # Vector loads and stores |
| |
| # Widening loads and narrowing stores: |
| # for these P=0 W=0 is 'related encoding'; sz=11 is 'related encoding' |
| # This means we need to expand out to multiple patterns for P, W, SZ. |
| # For stores the U bit must be 0 but we catch that in the trans_ function. |
| # The naming scheme here is "VLDSTB_H == in-memory byte load/store to/from |
| # signed halfword element in register", etc. |
| VLDSTB_H 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 01 ....... @vldst_wn \ |
| p=0 w=1 size=1 |
| VLDSTB_H 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 01 ....... @vldst_wn \ |
| p=1 size=1 |
| VLDSTB_W 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 10 ....... @vldst_wn \ |
| p=0 w=1 size=2 |
| VLDSTB_W 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 10 ....... @vldst_wn \ |
| p=1 size=2 |
| VLDSTH_W 111 . 110 0 a:1 0 1 . 1 ... ... 0 111 10 ....... @vldst_wn \ |
| p=0 w=1 size=2 |
| VLDSTH_W 111 . 110 1 a:1 0 w:1 . 1 ... ... 0 111 10 ....... @vldst_wn \ |
| p=1 size=2 |
| |
| # Non-widening loads/stores (P=0 W=0 is 'related encoding') |
| VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111100 ....... @vldr_vstr \ |
| size=0 p=0 w=1 |
| VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111101 ....... @vldr_vstr \ |
| size=1 p=0 w=1 |
| VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111110 ....... @vldr_vstr \ |
| size=2 p=0 w=1 |
| VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111100 ....... @vldr_vstr \ |
| size=0 p=1 |
| VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \ |
| size=1 p=1 |
| VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ |
| size=2 p=1 |
| |
| # Vector 2-op |
| VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| VORR 1110 1111 0 . 10 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| VORN 1110 1111 0 . 11 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| VEOR 1111 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
| |
| VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op |
| VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op |
| VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op |
| |
| VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op |
| VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op |
| |
| VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
| VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
| |
| VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op |
| VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op |
| VMIN_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op |
| VMIN_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op |
| |
| VABD_S 111 0 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op |
| VABD_U 111 1 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op |
| |
| VHADD_S 111 0 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op |
| VHADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op |
| VHSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op |
| VHSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op |
| |
| VMULL_BS 111 0 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op |
| VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op |
| VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op |
| VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op |
| |
| VQDMULH 1110 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op |
| VQRDMULH 1111 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op |
| |
| # Vector miscellaneous |
| |
| VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op |
| VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op |
| |
| VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op |
| VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op |
| VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op |
| |
| VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz |
| |
| VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . 0 ... 0 @1op |
| VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op |
| VNEG 1111 1111 1 . 11 .. 01 ... 0 0011 11 . 0 ... 0 @1op |
| VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op |
| |
| &vdup qd rt size |
| # Qd is in the fields usually named Qn |
| @vdup .... .... . . .. ... . rt:4 .... . . . . .... qd=%qn &vdup |
| |
| # B and E bits encode size, which we decode here to the usual size values |
| VDUP 1110 1110 1 1 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=0 |
| VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 1 1 0000 @vdup size=1 |
| VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2 |
| |
| # multiply-add long dual accumulate |
| # rdahi: bits [3:1] from insn, bit 0 is 1 |
| # rdalo: bits [3:1] from insn, bit 0 is 0 |
| %rdahi 20:3 !function=times_2_plus_1 |
| %rdalo 13:3 !function=times_2 |
| # size bit is 0 for 16 bit, 1 for 32 bit |
| %size_16 16:1 !function=plus_1 |
| |
| &vmlaldav rdahi rdalo size qn qm x a |
| |
| @vmlaldav .... .... . ... ... . ... . .... .... qm:3 . \ |
| qn=%qn rdahi=%rdahi rdalo=%rdalo size=%size_16 &vmlaldav |
| @vmlaldav_nosz .... .... . ... ... . ... . .... .... qm:3 . \ |
| qn=%qn rdahi=%rdahi rdalo=%rdalo size=0 &vmlaldav |
| VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav |
| VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav |
| |
| VMLSLDAV 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav |
| |
| VRMLALDAVH_S 1110 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlaldav_nosz |
| VRMLALDAVH_U 1111 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlaldav_nosz |
| |
| VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav_nosz |
| |
| # Scalar operations |
| |
| VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar |
| VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar |
| VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar |
| VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar |
| VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar |
| VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar |
| VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar |
| |
| { |
| VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar |
| VQADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar |
| VQDMULLB_scalar 111 . 1110 0 . 11 ... 0 ... 0 1111 . 110 .... @2scalar_nosz \ |
| size=%size_28 |
| } |
| |
| { |
| VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar |
| VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar |
| VQDMULLT_scalar 111 . 1110 0 . 11 ... 0 ... 1 1111 . 110 .... @2scalar_nosz \ |
| size=%size_28 |
| } |
| |
| VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar |
| |
| VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar |
| VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar |
| |
| |
| # Predicate operations |
| %mask_22_13 22:1 13:3 |
| VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 |
