target/arm: GICv5 cpuif: Implement PPI enable register Implement the GICv5 register which holds the enable state of PPIs: ICC_PPI_ENABLER<n>_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-id: 20260327111700.795099-40-peter.maydell@linaro.org