)]}'
{
  "commit": "2f36257492dcd66438f2f00560b37fd9044ef00a",
  "tree": "89262e9c0ee6b9d84b0b8406e6c8a3f9aebe6f2f",
  "parents": [
    "585dad9e79e1d64075e99448ee34adbeeeeea056"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Mar 27 11:16:34 2026 +0000"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu May 07 15:13:47 2026 +0100"
  },
  "message": "target/arm: GICv5 cpuif: Implement PPI enable register\n\nImplement the GICv5 register which holds the enable state of PPIs:\nICC_PPI_ENABLER\u003cn\u003e_EL1.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Jonathan Cameron \u003cjonathan.cameron@huawei.com\u003e\nMessage-id: 20260327111700.795099-40-peter.maydell@linaro.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b0fc90a994b73bf8695fd2aee19e482788084c39",
      "old_mode": 33188,
      "old_path": "target/arm/cpu.h",
      "new_id": "9b12b0114b7ca0b8c36939a26a6e0193f08e533b",
      "new_mode": 33188,
      "new_path": "target/arm/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "ee97d98d7e6730de7d6e8105f1bea9fd05151196",
      "old_mode": 33188,
      "old_path": "target/arm/tcg/gicv5-cpuif.c",
      "new_id": "09cd56cbfa4567f155c0da5bbcab665cad5edd91",
      "new_mode": 33188,
      "new_path": "target/arm/tcg/gicv5-cpuif.c"
    }
  ]
}