| /* |
| * OpenPOWER Palmetto BMC |
| * |
| * Andrew Jeffery <andrew@aj.id.au> |
| * |
| * Copyright 2016 IBM Corp. |
| * |
| * This code is licensed under the GPL version 2 or later. See |
| * the COPYING file in the top-level directory. |
| */ |
| |
| #include "qemu/osdep.h" |
| #include "qapi/error.h" |
| #include "hw/arm/boot.h" |
| #include "hw/arm/aspeed.h" |
| #include "hw/arm/aspeed_soc.h" |
| #include "hw/arm/aspeed_eeprom.h" |
| #include "hw/arm/machines-qom.h" |
| #include "hw/block/flash.h" |
| #include "hw/i2c/i2c_mux_pca954x.h" |
| #include "hw/i2c/smbus_eeprom.h" |
| #include "hw/gpio/pca9552.h" |
| #include "hw/gpio/pca9554.h" |
| #include "hw/nvram/eeprom_at24c.h" |
| #include "hw/sensor/tmp105.h" |
| #include "hw/misc/led.h" |
| #include "hw/qdev-properties.h" |
| #include "system/block-backend.h" |
| #include "system/reset.h" |
| #include "qemu/error-report.h" |
| #include "qemu/units.h" |
| #include "hw/qdev-clock.h" |
| #include "system/system.h" |
| |
| static struct arm_boot_info aspeed_board_binfo = { |
| .board_id = -1, /* device-tree-only board */ |
| }; |
| |
| /* AST2600 evb hardware value */ |
| #define AST2600_EVB_HW_STRAP1 0x000000C0 |
| #define AST2600_EVB_HW_STRAP2 0x00000003 |
| |
| #ifdef TARGET_AARCH64 |
| /* AST2700 evb hardware value */ |
| /* SCU HW Strap1 */ |
| #define AST2700_EVB_HW_STRAP1 0x00000800 |
| /* SCUIO HW Strap1 */ |
| #define AST2700_EVB_HW_STRAP2 0x00000700 |
| #endif |
| |
| /* Rainier hardware value: (QEMU prototype) */ |
| #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC) |
| #define RAINIER_BMC_HW_STRAP2 0x80000848 |
| |
| #define AST_SMP_MAILBOX_BASE 0x1e6e2180 |
| #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) |
| #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) |
| #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) |
| #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) |
| #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) |
| #define AST_SMP_MBOX_GOSIGN 0xabbaab00 |
| |
| static void aspeed_write_smpboot(ARMCPU *cpu, |
| const struct arm_boot_info *info) |
| { |
| AddressSpace *as = arm_boot_address_space(cpu, info); |
| static const ARMInsnFixup poll_mailbox_ready[] = { |
| /* |
| * r2 = per-cpu go sign value |
| * r1 = AST_SMP_MBOX_FIELD_ENTRY |
| * r0 = AST_SMP_MBOX_FIELD_GOSIGN |
| */ |
| { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ |
| { 0xe21000ff }, /* ands r0, r0, #255 */ |
| { 0xe59f201c }, /* ldr r2, [pc, #28] */ |
| { 0xe1822000 }, /* orr r2, r2, r0 */ |
| |
| { 0xe59f1018 }, /* ldr r1, [pc, #24] */ |
| { 0xe59f0018 }, /* ldr r0, [pc, #24] */ |
| |
| { 0xe320f002 }, /* wfe */ |
| { 0xe5904000 }, /* ldr r4, [r0] */ |
| { 0xe1520004 }, /* cmp r2, r4 */ |
| { 0x1afffffb }, /* bne <wfe> */ |
| { 0xe591f000 }, /* ldr pc, [r1] */ |
| { AST_SMP_MBOX_GOSIGN }, |
| { AST_SMP_MBOX_FIELD_ENTRY }, |
| { AST_SMP_MBOX_FIELD_GOSIGN }, |
| { 0, FIXUP_TERMINATOR } |
| }; |
| static const uint32_t fixupcontext[FIXUP_MAX] = { 0 }; |
| |
| arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, |
| poll_mailbox_ready, fixupcontext); |
| } |
| |
| static void aspeed_reset_secondary(ARMCPU *cpu, |
| const struct arm_boot_info *info) |
| { |
| AddressSpace *as = arm_boot_address_space(cpu, info); |
| CPUState *cs = CPU(cpu); |
| |
| /* info->smp_bootreg_addr */ |
| address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, |
| MEMTXATTRS_UNSPECIFIED, NULL); |
| cpu_set_pc(cs, info->smp_loader_start); |
| } |
| |
| static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc, |
| bool boot_emmc) |
| { |
| DeviceState *card; |
| |
| if (!dinfo) { |
| return; |
| } |
| card = qdev_new(emmc ? TYPE_EMMC : TYPE_SD_CARD); |
| |
| /* |
| * Force the boot properties of the eMMC device only when the |
| * machine is strapped to boot from eMMC. Without these |
| * settings, the machine would not boot. |
| * |
| * This also allows the machine to use an eMMC device without |
| * boot areas when booting from the flash device (or -kernel) |
| * Ideally, the device and its properties should be defined on |
| * the command line. |
| */ |
| if (emmc && boot_emmc) { |
| qdev_prop_set_uint64(card, "boot-partition-size", 1 * MiB); |
| qdev_prop_set_uint8(card, "boot-config", 0x1 << 3); |
| } |
| qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), |
| &error_fatal); |
| qdev_realize_and_unref(card, |
| qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), |
| &error_fatal); |
| } |
| |
| static void connect_serial_hds_to_uarts(AspeedMachineState *bmc) |
| { |
| AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); |
| AspeedSoCState *s = bmc->soc; |
| AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
| int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; |
| |
| aspeed_soc_uart_set_chr(s->uart, uart_chosen, sc->uarts_base, |
| sc->uarts_num, serial_hd(0)); |
| for (int i = 1, uart = sc->uarts_base; i < sc->uarts_num; uart++) { |
| if (uart == uart_chosen) { |
| continue; |
| } |
| aspeed_soc_uart_set_chr(s->uart, uart, sc->uarts_base, sc->uarts_num, |
| serial_hd(i++)); |
| } |
| } |
| |
| static void aspeed_machine_init(MachineState *machine) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(machine); |
| AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); |
| AspeedSoCClass *sc; |
| int i; |
| const char *bios_name = NULL; |
| DriveInfo *emmc0 = NULL; |
| bool boot_emmc; |
| |
| bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); |
| object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); |
| object_unref(OBJECT(bmc->soc)); |
| sc = ASPEED_SOC_GET_CLASS(bmc->soc); |
| |
| /* |
| * This will error out if the RAM size is not supported by the |
| * memory controller of the SoC. |
| */ |
| object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size, |
| &error_fatal); |
| |
| for (i = 0; i < sc->macs_num; i++) { |
| if ((amc->macs_mask & (1 << i)) && |
| !qemu_configure_nic_device(DEVICE(&bmc->soc->ftgmac100[i]), |
| true, NULL)) { |
| break; /* No configs left; stop asking */ |
| } |
| } |
| |
| object_property_set_int(OBJECT(bmc->soc), "hw-strap1", bmc->hw_strap1, |
| &error_abort); |
| object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2, |
| &error_abort); |
| object_property_set_link(OBJECT(bmc->soc), "memory", |
| OBJECT(get_system_memory()), &error_abort); |
| object_property_set_link(OBJECT(bmc->soc), "dram", |
| OBJECT(machine->ram), &error_abort); |
| if (amc->sdhci_wp_inverted) { |
| for (i = 0; i < bmc->soc->sdhci.num_slots; i++) { |
| object_property_set_bool(OBJECT(&bmc->soc->sdhci.slots[i]), |
| "wp-inverted", true, &error_abort); |
| } |
| } |
| if (machine->kernel_filename) { |
| /* |
| * When booting with a -kernel command line there is no u-boot |
| * that runs to unlock the SCU. In this case set the default to |
| * be unlocked as the kernel expects |
| */ |
| object_property_set_int(OBJECT(bmc->soc), "hw-prot-key", |
| ASPEED_SCU_PROT_KEY, &error_abort); |
| } |
| connect_serial_hds_to_uarts(bmc); |
| qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); |
| |
| if (defaults_enabled()) { |
| aspeed_board_init_flashes(&bmc->soc->fmc, |
| bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, |
| amc->num_cs, 0); |
| aspeed_board_init_flashes(&bmc->soc->spi[0], |
| bmc->spi_model ? bmc->spi_model : amc->spi_model, |
| 1, amc->num_cs); |
| aspeed_board_init_flashes(&bmc->soc->spi[1], |
| amc->spi2_model, 1, amc->num_cs2); |
| } |
| |
| if (machine->kernel_filename && sc->num_cpus > 1) { |
| /* With no u-boot we must set up a boot stub for the secondary CPU */ |
| MemoryRegion *smpboot = g_new(MemoryRegion, 1); |
| memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", |
| 0x80, &error_abort); |
| memory_region_add_subregion(get_system_memory(), |
| AST_SMP_MAILBOX_BASE, smpboot); |
| |
| aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; |
| aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; |
| aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; |
| } |
| |
| aspeed_board_binfo.ram_size = machine->ram_size; |
| aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; |
| |
| if (amc->i2c_init) { |
| amc->i2c_init(bmc); |
| } |
| |
| for (i = 0; i < bmc->soc->sdhci.num_slots && defaults_enabled(); i++) { |
| sdhci_attach_drive(&bmc->soc->sdhci.slots[i], |
| drive_get(IF_SD, 0, i), false, false); |
| } |
| |
| boot_emmc = sc->boot_from_emmc(bmc->soc); |
| |
| if (bmc->soc->emmc.num_slots && defaults_enabled()) { |
| emmc0 = drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots); |
| sdhci_attach_drive(&bmc->soc->emmc.slots[0], emmc0, true, boot_emmc); |
| } |
| |
| if (!bmc->mmio_exec) { |
| DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0); |
| BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; |
| |
| if (fmc0 && !boot_emmc) { |
| uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot); |
| aspeed_install_boot_rom(bmc->soc, fmc0, &bmc->boot_rom, rom_size); |
| } else if (emmc0) { |
| aspeed_install_boot_rom(bmc->soc, blk_by_legacy_dinfo(emmc0), |
| &bmc->boot_rom, 64 * KiB); |
| } |
| } |
| |
| if (amc->vbootrom) { |
| bios_name = machine->firmware ?: VBOOTROM_FILE_NAME; |
| aspeed_load_vbootrom(bmc->soc, bios_name, &error_abort); |
| } |
| |
| arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); |
| } |
| |
| static void ast2600_evb_i2c_init(AspeedMachineState *bmc) |
| { |
| AspeedSoCState *soc = bmc->soc; |
| uint8_t *eeprom_buf = g_malloc0(8 * 1024); |
| |
| smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, |
| eeprom_buf); |
| |
| /* LM75 is compatible with TMP105 driver */ |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), |
| TYPE_TMP105, 0x4d); |
| } |
| |
| void aspeed_create_pca9552(AspeedSoCState *soc, int bus_id, int addr) |
| { |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), |
| TYPE_PCA9552, addr); |
| } |
| |
| I2CSlave *aspeed_create_pca9554(AspeedSoCState *soc, int bus_id, int addr) |
| { |
| return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id), |
| TYPE_PCA9554, addr); |
| } |
| |
| static void rainier_bmc_i2c_init(AspeedMachineState *bmc) |
| { |
| AspeedSoCState *soc = bmc->soc; |
| I2CSlave *i2c_mux; |
| |
| at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB); |
| |
| aspeed_create_pca9552(soc, 3, 0x61); |
| |
| /* The rainier expects a TMP275 but a TMP105 is compatible */ |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, |
| 0x48); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, |
| 0x49); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, |
| 0x4a); |
| i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), |
| "pca9546", 0x70); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB); |
| aspeed_create_pca9552(soc, 4, 0x60); |
| |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, |
| 0x48); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, |
| 0x49); |
| aspeed_create_pca9552(soc, 5, 0x60); |
| aspeed_create_pca9552(soc, 5, 0x61); |
| i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), |
| "pca9546", 0x70); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); |
| |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, |
| 0x48); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, |
| 0x4a); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, |
| 0x4b); |
| i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), |
| "pca9546", 0x70); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB); |
| |
| aspeed_create_pca9552(soc, 7, 0x30); |
| aspeed_create_pca9552(soc, 7, 0x31); |
| aspeed_create_pca9552(soc, 7, 0x32); |
| aspeed_create_pca9552(soc, 7, 0x33); |
| aspeed_create_pca9552(soc, 7, 0x60); |
| aspeed_create_pca9552(soc, 7, 0x61); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76); |
| /* Bus 7: TODO si7021-a20@20 */ |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, |
| 0x48); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52); |
| at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB); |
| at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB); |
| |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, |
| 0x48); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, |
| 0x4a); |
| at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, |
| 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len); |
| at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, |
| 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len); |
| aspeed_create_pca9552(soc, 8, 0x60); |
| aspeed_create_pca9552(soc, 8, 0x61); |
| /* Bus 8: ucd90320@11 */ |
| /* Bus 8: ucd90320@b */ |
| /* Bus 8: ucd90320@c */ |
| |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); |
| at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB); |
| |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); |
| at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB); |
| |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, |
| 0x48); |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, |
| 0x49); |
| i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), |
| "pca9546", 0x70); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB); |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB); |
| aspeed_create_pca9552(soc, 11, 0x60); |
| |
| |
| at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB); |
| aspeed_create_pca9552(soc, 13, 0x60); |
| |
| at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB); |
| aspeed_create_pca9552(soc, 14, 0x60); |
| |
| at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB); |
| aspeed_create_pca9552(soc, 15, 0x60); |
| } |
| |
| #define TYPE_LM75 TYPE_TMP105 |
| #define TYPE_TMP75 TYPE_TMP105 |
| #define TYPE_TMP421 "tmp421" |
| #define TYPE_DS1338 "ds1338" |
| |
| /* Catalina hardware value */ |
| #define CATALINA_BMC_HW_STRAP1 0x00002002 |
| #define CATALINA_BMC_HW_STRAP2 0x00000800 |
| |
| #define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) |
| |
| static void catalina_bmc_i2c_init(AspeedMachineState *bmc) |
| { |
| /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */ |
| |
| AspeedSoCState *soc = bmc->soc; |
| I2CBus *i2c[16] = {}; |
| I2CSlave *i2c_mux; |
| |
| /* busses 0-15 are all used. */ |
| for (int i = 0; i < ARRAY_SIZE(i2c); i++) { |
| i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i); |
| } |
| |
| /* &i2c0 */ |
| /* i2c-mux@71 (PCA9546) on i2c0 */ |
| i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71); |
| |
| /* i2c-mux@72 (PCA9546) on i2c0 */ |
| i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72); |
| |
| /* i2c0mux1ch1 */ |
| /* io_expander7 - pca9535@20 */ |
| i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), |
| TYPE_PCA9552, 0x20); |
| /* eeprom@50 */ |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); |
| |
| /* i2c-mux@73 (PCA9546) on i2c0 */ |
| i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73); |
| |
| /* i2c-mux@75 (PCA9546) on i2c0 */ |
| i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75); |
| |
| /* i2c-mux@76 (PCA9546) on i2c0 */ |
| i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76); |
| |
| /* i2c0mux4ch1 */ |
| /* io_expander8 - pca9535@21 */ |
| i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1), |
| TYPE_PCA9552, 0x21); |
| /* eeprom@50 */ |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB); |
| |
| /* i2c-mux@77 (PCA9546) on i2c0 */ |
| i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77); |
| |
| |
| /* &i2c1 */ |
| /* i2c-mux@70 (PCA9548) on i2c1 */ |
| i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70); |
| /* i2c1mux0ch0 */ |
| /* ina238@41 - no model */ |
| /* ina238@42 - no model */ |
| /* ina238@44 - no model */ |
| /* i2c1mux0ch1 */ |
| /* ina238@41 - no model */ |
| /* ina238@43 - no model */ |
| /* i2c1mux0ch4 */ |
| /* ltc4287@42 - no model */ |
| /* ltc4287@43 - no model */ |
| |
| /* i2c1mux0ch5 */ |
| /* eeprom@54 */ |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB); |
| /* tpm75@4f */ |
| i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f); |
| |
| /* i2c1mux0ch6 */ |
| /* io_expander5 - pca9554@27 */ |
| i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), |
| TYPE_PCA9554, 0x27); |
| /* io_expander6 - pca9555@25 */ |
| i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6), |
| TYPE_PCA9552, 0x25); |
| /* eeprom@51 */ |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB); |
| |
| /* i2c1mux0ch7 */ |
| /* eeprom@53 */ |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB); |
| /* temperature-sensor@4b - tmp75 */ |
| i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b); |
| |
| /* &i2c2 */ |
| /* io_expander0 - pca9555@20 */ |
| i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20); |
| /* io_expander0 - pca9555@21 */ |
| i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21); |
| /* io_expander0 - pca9555@27 */ |
| i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27); |
| /* eeprom@50 */ |
| at24c_eeprom_init(i2c[2], 0x50, 8 * KiB); |
| /* eeprom@51 */ |
| at24c_eeprom_init(i2c[2], 0x51, 8 * KiB); |
| |
| /* &i2c5 */ |
| /* i2c-mux@70 (PCA9548) on i2c5 */ |
| i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70); |
| /* i2c5mux0ch6 */ |
| /* eeprom@52 */ |
| at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB); |
| /* i2c5mux0ch7 */ |
| /* ina230@40 - no model */ |
| /* ina230@41 - no model */ |
| /* ina230@44 - no model */ |
| /* ina230@45 - no model */ |
| |
| /* &i2c6 */ |
| /* io_expander3 - pca9555@21 */ |
| i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21); |
| /* rtc@6f - nct3018y */ |
| i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f); |
| |
| /* &i2c9 */ |
| /* io_expander4 - pca9555@4f */ |
| i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f); |
| /* temperature-sensor@4b - tpm75 */ |
| i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b); |
| /* eeprom@50 */ |
| at24c_eeprom_init(i2c[9], 0x50, 8 * KiB); |
| /* eeprom@56 */ |
| at24c_eeprom_init(i2c[9], 0x56, 8 * KiB); |
| |
| /* &i2c10 */ |
| /* temperature-sensor@1f - tpm421 */ |
| i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f); |
| /* eeprom@50 */ |
| at24c_eeprom_init(i2c[10], 0x50, 8 * KiB); |
| |
| /* &i2c11 */ |
| /* ssif-bmc@10 - no model */ |
| |
| /* &i2c12 */ |
| /* eeprom@50 */ |
| at24c_eeprom_init(i2c[12], 0x50, 8 * KiB); |
| |
| /* &i2c13 */ |
| /* eeprom@50 */ |
| at24c_eeprom_init(i2c[13], 0x50, 8 * KiB); |
| /* eeprom@54 */ |
| at24c_eeprom_init(i2c[13], 0x54, 256); |
| /* eeprom@55 */ |
| at24c_eeprom_init(i2c[13], 0x55, 256); |
| /* eeprom@57 */ |
| at24c_eeprom_init(i2c[13], 0x57, 256); |
| |
| /* &i2c14 */ |
| /* io_expander9 - pca9555@10 */ |
| i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10); |
| /* io_expander10 - pca9555@11 */ |
| i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11); |
| /* io_expander11 - pca9555@12 */ |
| i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12); |
| /* io_expander12 - pca9555@13 */ |
| i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13); |
| /* io_expander13 - pca9555@14 */ |
| i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14); |
| /* io_expander14 - pca9555@15 */ |
| i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15); |
| |
| /* &i2c15 */ |
| /* temperature-sensor@1f - tmp421 */ |
| i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f); |
| /* eeprom@52 */ |
| at24c_eeprom_init(i2c[15], 0x52, 8 * KiB); |
| } |
| |
| static bool aspeed_get_mmio_exec(Object *obj, Error **errp) |
| { |
| return ASPEED_MACHINE(obj)->mmio_exec; |
| } |
| |
| static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) |
| { |
| ASPEED_MACHINE(obj)->mmio_exec = value; |
| } |
| |
| static void aspeed_machine_instance_init(Object *obj) |
| { |
| AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(obj); |
| |
| ASPEED_MACHINE(obj)->mmio_exec = false; |
| ASPEED_MACHINE(obj)->hw_strap1 = amc->hw_strap1; |
| } |
| |
| static char *aspeed_get_fmc_model(Object *obj, Error **errp) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| return g_strdup(bmc->fmc_model); |
| } |
| |
| static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| |
| g_free(bmc->fmc_model); |
| bmc->fmc_model = g_strdup(value); |
| } |
| |
| static char *aspeed_get_spi_model(Object *obj, Error **errp) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| return g_strdup(bmc->spi_model); |
| } |
| |
| static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| |
| g_free(bmc->spi_model); |
| bmc->spi_model = g_strdup(value); |
| } |
| |
| static char *aspeed_get_bmc_console(Object *obj, Error **errp) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); |
| int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default; |
| |
| return g_strdup_printf("uart%d", aspeed_uart_index(uart_chosen)); |
| } |
| |
| static void aspeed_set_bmc_console(Object *obj, const char *value, Error **errp) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); |
| AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); |
| int val; |
| int uart_first = aspeed_uart_first(sc->uarts_base); |
| int uart_last = aspeed_uart_last(sc->uarts_base, sc->uarts_num); |
| |
| if (sscanf(value, "uart%u", &val) != 1) { |
| error_setg(errp, "Bad value for \"uart\" property"); |
| return; |
| } |
| |
| /* The number of UART depends on the SoC */ |
| if (val < uart_first || val > uart_last) { |
| error_setg(errp, "\"uart\" should be in range [%d - %d]", |
| uart_first, uart_last); |
| return; |
| } |
| bmc->uart_chosen = val + ASPEED_DEV_UART0; |
| } |
| |
| static void aspeed_machine_class_props_init(ObjectClass *oc) |
| { |
| object_class_property_add_bool(oc, "execute-in-place", |
| aspeed_get_mmio_exec, |
| aspeed_set_mmio_exec); |
| object_class_property_set_description(oc, "execute-in-place", |
| "boot directly from CE0 flash device"); |
| |
| object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_console, |
| aspeed_set_bmc_console); |
| object_class_property_set_description(oc, "bmc-console", |
| "Change the default UART to \"uartX\""); |
| |
| object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, |
| aspeed_set_fmc_model); |
| object_class_property_set_description(oc, "fmc-model", |
| "Change the FMC Flash model"); |
| object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model, |
| aspeed_set_spi_model); |
| object_class_property_set_description(oc, "spi-model", |
| "Change the SPI Flash model"); |
| } |
| |
| void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) |
| { |
| AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); |
| AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); |
| |
| mc->default_cpus = sc->num_cpus; |
| mc->min_cpus = sc->num_cpus; |
| mc->max_cpus = sc->num_cpus; |
| mc->valid_cpu_types = sc->valid_cpu_types; |
| } |
| |
| static bool aspeed_machine_ast2600_get_boot_from_emmc(Object *obj, Error **errp) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| |
| return !!(bmc->hw_strap1 & SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC); |
| } |
| |
| static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value, |
| Error **errp) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(obj); |
| |
| if (value) { |
| bmc->hw_strap1 |= SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; |
| } else { |
| bmc->hw_strap1 &= ~SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC; |
| } |
| } |
| |
| void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc) |
| { |
| object_class_property_add_bool(oc, "boot-emmc", |
| aspeed_machine_ast2600_get_boot_from_emmc, |
| aspeed_machine_ast2600_set_boot_from_emmc); |
| object_class_property_set_description(oc, "boot-emmc", |
| "Set or unset boot from EMMC"); |
| } |
| |
| static void aspeed_machine_class_init(ObjectClass *oc, const void *data) |
| { |
| MachineClass *mc = MACHINE_CLASS(oc); |
| AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
| |
| mc->init = aspeed_machine_init; |
| mc->no_floppy = 1; |
| mc->no_cdrom = 1; |
| mc->no_parallel = 1; |
| mc->default_ram_id = "ram"; |
| amc->macs_mask = ASPEED_MAC0_ON; |
| amc->uart_default = ASPEED_DEV_UART5; |
| |
| aspeed_machine_class_props_init(oc); |
| } |
| |
| static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, |
| const void *data) |
| { |
| MachineClass *mc = MACHINE_CLASS(oc); |
| AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
| |
| mc->desc = "Aspeed AST2600 EVB (Cortex-A7)"; |
| amc->soc_name = "ast2600-a3"; |
| amc->hw_strap1 = AST2600_EVB_HW_STRAP1; |
| amc->hw_strap2 = AST2600_EVB_HW_STRAP2; |
| amc->fmc_model = "w25q512jv"; |
| amc->spi_model = "w25q512jv"; |
| amc->num_cs = 1; |
| amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON | |
| ASPEED_MAC3_ON; |
| amc->sdhci_wp_inverted = true; |
| amc->i2c_init = ast2600_evb_i2c_init; |
| mc->default_ram_size = 1 * GiB; |
| aspeed_machine_class_init_cpus_defaults(mc); |
| aspeed_machine_ast2600_class_emmc_init(oc); |
| }; |
| |
| static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data) |
| { |
| MachineClass *mc = MACHINE_CLASS(oc); |
| AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
| |
| mc->desc = "IBM Rainier BMC (Cortex-A7)"; |
| amc->soc_name = "ast2600-a3"; |
| amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; |
| amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; |
| amc->fmc_model = "mx66l1g45g"; |
| amc->spi_model = "mx66l1g45g"; |
| amc->num_cs = 2; |
| amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; |
| amc->i2c_init = rainier_bmc_i2c_init; |
| mc->default_ram_size = 1 * GiB; |
| aspeed_machine_class_init_cpus_defaults(mc); |
| aspeed_machine_ast2600_class_emmc_init(oc); |
| }; |
| |
| static void aspeed_machine_catalina_class_init(ObjectClass *oc, |
| const void *data) |
| { |
| MachineClass *mc = MACHINE_CLASS(oc); |
| AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
| |
| mc->desc = "Facebook Catalina BMC (Cortex-A7)"; |
| amc->soc_name = "ast2600-a3"; |
| amc->hw_strap1 = CATALINA_BMC_HW_STRAP1; |
| amc->hw_strap2 = CATALINA_BMC_HW_STRAP2; |
| amc->fmc_model = "w25q01jvq"; |
| amc->spi_model = NULL; |
| amc->num_cs = 2; |
| amc->macs_mask = ASPEED_MAC2_ON; |
| amc->i2c_init = catalina_bmc_i2c_init; |
| mc->default_ram_size = CATALINA_BMC_RAM_SIZE; |
| aspeed_machine_class_init_cpus_defaults(mc); |
| aspeed_machine_ast2600_class_emmc_init(oc); |
| } |
| |
| #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) |
| /* Main SYSCLK frequency in Hz (200MHz) */ |
| #define SYSCLK_FRQ 200000000ULL |
| |
| static void aspeed_minibmc_machine_init(MachineState *machine) |
| { |
| AspeedMachineState *bmc = ASPEED_MACHINE(machine); |
| AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); |
| Clock *sysclk; |
| |
| sysclk = clock_new(OBJECT(machine), "SYSCLK"); |
| clock_set_hz(sysclk, SYSCLK_FRQ); |
| |
| bmc->soc = ASPEED_SOC(object_new(amc->soc_name)); |
| object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc)); |
| object_unref(OBJECT(bmc->soc)); |
| qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk); |
| |
| object_property_set_link(OBJECT(bmc->soc), "memory", |
| OBJECT(get_system_memory()), &error_abort); |
| connect_serial_hds_to_uarts(bmc); |
| qdev_realize(DEVICE(bmc->soc), NULL, &error_abort); |
| |
| if (defaults_enabled()) { |
| aspeed_board_init_flashes(&bmc->soc->fmc, |
| bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, |
| amc->num_cs, |
| 0); |
| |
| aspeed_board_init_flashes(&bmc->soc->spi[0], |
| bmc->spi_model ? bmc->spi_model : amc->spi_model, |
| amc->num_cs, amc->num_cs); |
| |
| aspeed_board_init_flashes(&bmc->soc->spi[1], |
| bmc->spi_model ? bmc->spi_model : amc->spi_model, |
| amc->num_cs, (amc->num_cs * 2)); |
| } |
| |
| if (amc->i2c_init) { |
| amc->i2c_init(bmc); |
| } |
| |
| armv7m_load_kernel(ARM_CPU(first_cpu), |
| machine->kernel_filename, |
| 0, |
| AST1030_INTERNAL_FLASH_SIZE); |
| } |
| |
| static void ast1030_evb_i2c_init(AspeedMachineState *bmc) |
| { |
| AspeedSoCState *soc = bmc->soc; |
| |
| /* U10 24C08 connects to SDA/SCL Group 1 by default */ |
| uint8_t *eeprom_buf = g_malloc0(32 * 1024); |
| smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf); |
| |
| /* U11 LM75 connects to SDA/SCL Group 2 by default */ |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d); |
| } |
| |
| static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, |
| const void *data) |
| { |
| MachineClass *mc = MACHINE_CLASS(oc); |
| AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
| |
| mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)"; |
| amc->soc_name = "ast1030-a1"; |
| amc->hw_strap1 = 0; |
| amc->hw_strap2 = 0; |
| mc->init = aspeed_minibmc_machine_init; |
| amc->i2c_init = ast1030_evb_i2c_init; |
| mc->default_ram_size = 0; |
| amc->fmc_model = "w25q80bl"; |
| amc->spi_model = "w25q256"; |
| amc->num_cs = 2; |
| amc->macs_mask = 0; |
| aspeed_machine_class_init_cpus_defaults(mc); |
| } |
| |
| #ifdef TARGET_AARCH64 |
| static void ast2700_evb_i2c_init(AspeedMachineState *bmc) |
| { |
| AspeedSoCState *soc = bmc->soc; |
| |
| /* LM75 is compatible with TMP105 driver */ |
| i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), |
| TYPE_TMP105, 0x4d); |
| } |
| |
| static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc, |
| const void *data) |
| { |
| MachineClass *mc = MACHINE_CLASS(oc); |
| AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
| |
| mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)"; |
| amc->soc_name = "ast2700-a0"; |
| amc->hw_strap1 = AST2700_EVB_HW_STRAP1; |
| amc->hw_strap2 = AST2700_EVB_HW_STRAP2; |
| amc->fmc_model = "w25q01jvq"; |
| amc->spi_model = "w25q512jv"; |
| amc->num_cs = 2; |
| amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; |
| amc->uart_default = ASPEED_DEV_UART12; |
| amc->i2c_init = ast2700_evb_i2c_init; |
| amc->vbootrom = true; |
| mc->default_ram_size = 1 * GiB; |
| aspeed_machine_class_init_cpus_defaults(mc); |
| } |
| |
| static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, |
| const void *data) |
| { |
| MachineClass *mc = MACHINE_CLASS(oc); |
| AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
| |
| mc->alias = "ast2700-evb"; |
| mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)"; |
| amc->soc_name = "ast2700-a1"; |
| amc->hw_strap1 = AST2700_EVB_HW_STRAP1; |
| amc->hw_strap2 = AST2700_EVB_HW_STRAP2; |
| amc->fmc_model = "w25q01jvq"; |
| amc->spi_model = "w25q512jv"; |
| amc->num_cs = 2; |
| amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON; |
| amc->uart_default = ASPEED_DEV_UART12; |
| amc->i2c_init = ast2700_evb_i2c_init; |
| amc->vbootrom = true; |
| mc->default_ram_size = 1 * GiB; |
| aspeed_machine_class_init_cpus_defaults(mc); |
| } |
| #endif |
| |
| static const TypeInfo aspeed_machine_types[] = { |
| { |
| .name = MACHINE_TYPE_NAME("ast2600-evb"), |
| .parent = TYPE_ASPEED_MACHINE, |
| .class_init = aspeed_machine_ast2600_evb_class_init, |
| .interfaces = arm_machine_interfaces, |
| }, { |
| .name = MACHINE_TYPE_NAME("rainier-bmc"), |
| .parent = TYPE_ASPEED_MACHINE, |
| .class_init = aspeed_machine_rainier_class_init, |
| .interfaces = arm_machine_interfaces, |
| }, { |
| .name = MACHINE_TYPE_NAME("catalina-bmc"), |
| .parent = TYPE_ASPEED_MACHINE, |
| .class_init = aspeed_machine_catalina_class_init, |
| .interfaces = arm_machine_interfaces, |
| }, { |
| .name = MACHINE_TYPE_NAME("ast1030-evb"), |
| .parent = TYPE_ASPEED_MACHINE, |
| .class_init = aspeed_minibmc_machine_ast1030_evb_class_init, |
| .interfaces = arm_machine_interfaces, |
| #ifdef TARGET_AARCH64 |
| }, { |
| .name = MACHINE_TYPE_NAME("ast2700a0-evb"), |
| .parent = TYPE_ASPEED_MACHINE, |
| .class_init = aspeed_machine_ast2700a0_evb_class_init, |
| .interfaces = aarch64_machine_interfaces, |
| }, { |
| .name = MACHINE_TYPE_NAME("ast2700a1-evb"), |
| .parent = TYPE_ASPEED_MACHINE, |
| .class_init = aspeed_machine_ast2700a1_evb_class_init, |
| .interfaces = aarch64_machine_interfaces, |
| #endif |
| }, { |
| .name = TYPE_ASPEED_MACHINE, |
| .parent = TYPE_MACHINE, |
| .instance_size = sizeof(AspeedMachineState), |
| .instance_init = aspeed_machine_instance_init, |
| .class_size = sizeof(AspeedMachineClass), |
| .class_init = aspeed_machine_class_init, |
| .abstract = true, |
| } |
| }; |
| |
| DEFINE_TYPES(aspeed_machine_types) |
