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Anup Patel9e8ff052018-12-11 19:24:06 +05301/*
Anup patel20990ee2019-01-24 11:41:10 +05302 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Western Digital Corporation or its affiliates.
Anup Patel9e8ff052018-12-11 19:24:06 +05305 *
6 * Authors:
7 * Anup Patel <anup.patel@wdc.com>
Anup Patel9e8ff052018-12-11 19:24:06 +05308 */
9
10#ifndef __RISCV_BARRIER_H__
11#define __RISCV_BARRIER_H__
12
Olof Johanssonfbf986a2019-04-10 17:41:46 -070013/* clang-format off */
14
Anup Patel9e8ff052018-12-11 19:24:06 +053015#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n"
16#define RISCV_RELEASE_BARRIER "\tfence rw, w\n"
17
18#define RISCV_FENCE(p, s) \
19 __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
20
Guo Ren49e422c2021-04-17 16:26:17 +000021#define RISCV_FENCE_I \
22 __asm__ __volatile__ ("fence.i" : : : "memory")
23
Anup Patel9e8ff052018-12-11 19:24:06 +053024/* Read & Write Memory barrier */
25#define mb() RISCV_FENCE(iorw,iorw)
26
27/* Read Memory barrier */
28#define rmb() RISCV_FENCE(ir,ir)
29
30/* Write Memory barrier */
31#define wmb() RISCV_FENCE(ow,ow)
32
33/* SMP Read & Write Memory barrier */
34#define smp_mb() RISCV_FENCE(rw,rw)
35
36/* SMP Read Memory barrier */
37#define smp_rmb() RISCV_FENCE(r,r)
38
39/* SMP Write Memory barrier */
40#define smp_wmb() RISCV_FENCE(w,w)
41
42/* CPU relax for busy loop */
43#define cpu_relax() asm volatile ("" : : : "memory")
44
Olof Johanssonfbf986a2019-04-10 17:41:46 -070045/* clang-format on */
46
Olof Johansson10baa642019-04-10 17:41:52 -070047#define __smp_store_release(p, v) \
48 do { \
49 RISCV_FENCE(rw, w); \
50 *(p) = (v); \
51 } while (0)
Anup Patel9e8ff052018-12-11 19:24:06 +053052
Olof Johansson10baa642019-04-10 17:41:52 -070053#define __smp_load_acquire(p) \
54 ({ \
55 typeof(*p) ___p1 = *(p); \
56 RISCV_FENCE(r, rw); \
57 ___p1; \
58 })
Anup Patel9e8ff052018-12-11 19:24:06 +053059
60#endif