[build] Fix technically undefined left shifts in disreputable code Fix the technically undefined constant left shifts into the sign bit in ancient, messy, and third-party code. Signed-off-by: Michael Brown <mcb30@ipxe.org>
diff --git a/src/drivers/infiniband/CIB_PRM.h b/src/drivers/infiniband/CIB_PRM.h index d578f9b..5afbac5 100755 --- a/src/drivers/infiniband/CIB_PRM.h +++ b/src/drivers/infiniband/CIB_PRM.h
@@ -726,7 +726,7 @@ /* Memory key structures */ #define GOLAN_IB_ACCESS_LOCAL_READ (1 << 2) #define GOLAN_IB_ACCESS_LOCAL_WRITE (1 << 3) -#define GOLAN_MKEY_LEN64 (1 << 31) +#define GOLAN_MKEY_LEN64 (1U << 31) #define GOLAN_CREATE_MKEY_SEG_QPN_BIT 8 struct golan_mkey_seg { @@ -967,7 +967,7 @@ enum { GOLAN_QP_LAT_SENSITIVE = 1 << 28, - GOLAN_QP_ENABLE_SIG = 1 << 31 + GOLAN_QP_ENABLE_SIG = 1U << 31 };
diff --git a/src/drivers/infiniband/golan.c b/src/drivers/infiniband/golan.c index ffa78fa..53b452b 100755 --- a/src/drivers/infiniband/golan.c +++ b/src/drivers/infiniband/golan.c
@@ -874,7 +874,7 @@ in->seg.flags = GOLAN_IB_ACCESS_LOCAL_WRITE | GOLAN_IB_ACCESS_LOCAL_READ; in->seg.flags_pd = cpu_to_be32(golan->pdn | GOLAN_MKEY_LEN64); - in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << GOLAN_CREATE_MKEY_SEG_QPN_BIT); + in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffffU << GOLAN_CREATE_MKEY_SEG_QPN_BIT); rc = send_command_and_wait(golan, DEF_CMD_IDX, GEN_MBOX, NO_MBOX, __FUNCTION__); GOLAN_CHECK_RC_AND_CMD_STATUS( err_create_mkey_cmd ); @@ -1495,7 +1495,7 @@ datagram = &wqe->datagram; datagram->key.qkey.qkey = cpu_to_be32(av->qkey); - datagram->dqp_dct = cpu_to_be32((1 << 31) | av->qpn); + datagram->dqp_dct = cpu_to_be32((1U << 31) | av->qpn); datagram->stat_rate_sl = ((golan_rate(av->rate) << 4) | av->sl); datagram->fl_mlid = (ibdev->lid & 0x007f); /* take only the 7 low bits of the LID */ datagram->rlid = cpu_to_be16(av->lid);
diff --git a/src/drivers/infiniband/mlx_utils/src/public/mlx_icmd.c b/src/drivers/infiniband/mlx_utils/src/public/mlx_icmd.c index e4ab5f0..ee5dfa8 100644 --- a/src/drivers/infiniband/mlx_utils/src/public/mlx_icmd.c +++ b/src/drivers/infiniband/mlx_utils/src/public/mlx_icmd.c
@@ -149,7 +149,7 @@ MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd ctrl"); #define MLX_ICMD_OPCODE_ALIGN 16 -#define MLX_ICMD_OPCODE_MASK 0xffff +#define MLX_ICMD_OPCODE_MASK 0xffffU buffer = buffer & ~(MLX_ICMD_OPCODE_MASK << MLX_ICMD_OPCODE_ALIGN); buffer = buffer | (opcode << MLX_ICMD_OPCODE_ALIGN);
diff --git a/src/drivers/net/3c90x.h b/src/drivers/net/3c90x.h index 8bffa37..4a9f6cd 100644 --- a/src/drivers/net/3c90x.h +++ b/src/drivers/net/3c90x.h
@@ -206,8 +206,8 @@ }; enum UpDownDesc { - upLastFrag = (1 << 31), - downLastFrag = (1 << 31), + upLastFrag = (1U << 31), + downLastFrag = (1U << 31), }; enum UpPktStatus {
diff --git a/src/drivers/net/amd8111e.h b/src/drivers/net/amd8111e.h index 8ecd159..69e65e9 100644 --- a/src/drivers/net/amd8111e.h +++ b/src/drivers/net/amd8111e.h
@@ -163,7 +163,7 @@ /* INT0 0x38, 32bit register */ typedef enum { - INTR = (1 << 31), + INTR = (1U << 31), PCSINT = (1 << 28), LCINT = (1 << 27), APINT5 = (1 << 26), @@ -192,7 +192,7 @@ typedef enum { - VAL3 = (1 << 31), /* VAL bit for byte 3 */ + VAL3 = (1U << 31), /* VAL bit for byte 3 */ VAL2 = (1 << 23), /* VAL bit for byte 2 */ VAL1 = (1 << 15), /* VAL bit for byte 1 */ VAL0 = (1 << 7), /* VAL bit for byte 0 */ @@ -417,7 +417,7 @@ /* AP_VALUE 0x98, 32bit ragister */ typedef enum { - AP_VAL_ACTIVE = (1 << 31), + AP_VAL_ACTIVE = (1U << 31), AP_VAL_RD_CMD = ( 1 << 29), AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */ AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) | @@ -427,7 +427,7 @@ typedef enum { - DLY_INT_A_R3 = (1 << 31), + DLY_INT_A_R3 = (1U << 31), DLY_INT_A_R2 = (1 << 30), DLY_INT_A_R1 = (1 << 29), DLY_INT_A_R0 = (1 << 28), @@ -443,7 +443,7 @@ typedef enum { - DLY_INT_B_R3 = (1 << 31), + DLY_INT_B_R3 = (1U << 31), DLY_INT_B_R2 = (1 << 30), DLY_INT_B_R1 = (1 << 29), DLY_INT_B_R0 = (1 << 28), @@ -474,7 +474,7 @@ /* PHY_ ACCESS 0xD0, 32bit register */ typedef enum { - PHY_CMD_ACTIVE = (1 << 31), + PHY_CMD_ACTIVE = (1U << 31), PHY_WR_CMD = (1 << 30), PHY_RD_CMD = (1 << 29), PHY_RD_ERR = (1 << 28), @@ -490,7 +490,7 @@ /* PMAT0 0x190, 32bit register */ typedef enum { - PMR_ACTIVE = (1 << 31), + PMR_ACTIVE = (1U << 31), PMR_WR_CMD = (1 << 30), PMR_RD_CMD = (1 << 29), PMR_BANK = (1 <<28), @@ -502,7 +502,7 @@ /* PMAT1 0x194, 32bit register */ typedef enum { - PMR_B3 = (0xF << 24) | (0xF <<28),/* 31:24 */ + PMR_B3 = (0xF << 24) | (0xFU <<28),/* 31:24 */ PMR_B2 = (0xF << 16) |(0xF << 20),/* 23:16 */ PMR_B1 = (0xF << 8) | (0xF <<12), /* 15:8 */ PMR_B0 = (0xF << 0)|(0xF << 4),/* 7:0 */
diff --git a/src/drivers/net/ath/ath9k/ath9k_ar9003_eeprom.c b/src/drivers/net/ath/ath9k/ath9k_ar9003_eeprom.c index 96aa9ef..d101909 100644 --- a/src/drivers/net/ath/ath9k/ath9k_ar9003_eeprom.c +++ b/src/drivers/net/ath/ath9k/ath9k_ar9003_eeprom.c
@@ -3597,7 +3597,7 @@ reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); reg &= ~0xffffffe0; - reg |= 0x5 << 29; + reg |= 0x5U << 29; reg |= 0x5 << 26; reg |= 0x5 << 23; reg |= 0x5 << 20; @@ -3610,7 +3610,7 @@ reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); reg &= ~0xff800000; - reg |= 0x5 << 29; + reg |= 0x5U << 29; reg |= 0x5 << 26; reg |= 0x5 << 23; REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
diff --git a/src/drivers/net/ath/ath9k/hw.h b/src/drivers/net/ath/ath9k/hw.h index 02e9fc3..d1fbcd2 100644 --- a/src/drivers/net/ath/ath9k/hw.h +++ b/src/drivers/net/ath/ath9k/hw.h
@@ -102,7 +102,7 @@ #define SM(_v, _f) (((_v) << _f##_S) & _f) #define MS(_v, _f) (((_v) & _f) >> _f##_S) #define REG_RMW_FIELD(_a, _r, _f, _v) \ - REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) + REG_RMW(_a, _r, ((((unsigned)(_v)) << _f##_S) & _f), (_f)) #define REG_READ_FIELD(_a, _r, _f) \ (((REG_READ(_a, _r) & _f) >> _f##_S)) #define REG_SET_BIT(_a, _r, _f) \
diff --git a/src/drivers/net/bnx2.h b/src/drivers/net/bnx2.h index 9267868..2ac5dcf 100644 --- a/src/drivers/net/bnx2.h +++ b/src/drivers/net/bnx2.h
@@ -217,7 +217,7 @@ #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) - #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) + #define STATUS_ATTN_BITS_PARITY_ERROR (1UL<<31) u32 status_attn_bits_ack; #if __BYTE_ORDER == __BIG_ENDIAN @@ -383,7 +383,7 @@ #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) - #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) + #define L2_FHDR_ERRORS_UDP_XSUM (1U<<31) u32 l2_fhdr_hash; #if __BYTE_ORDER == __BIG_ENDIAN @@ -602,7 +602,7 @@ #define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26) #define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27) #define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30) -#define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31) +#define BNX2_PCI_CONFIG_3_PCI_POWER (1UL<<31) #define BNX2_PCI_PM_DATA_A 0x00000410 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) @@ -620,7 +620,7 @@ #define BNX2_PCI_SWAP_DIAG1 0x0000041c #define BNX2_PCI_EXP_ROM_ADDR 0x00000420 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) -#define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31) +#define BNX2_PCI_EXP_ROM_ADDR_REQ (1UL<<31) #define BNX2_PCI_EXP_ROM_DATA 0x00000424 #define BNX2_PCI_VPD_INTF 0x00000428 @@ -991,7 +991,7 @@ #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) -#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) +#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1UL<<31) #define BNX2_MISC_SMB_IN 0x00000884 #define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0) @@ -1080,7 +1080,7 @@ #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) -#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) +#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1UL<<31) #define BNX2_MISC_PERR_ENA1 0x000008a8 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) @@ -1114,7 +1114,7 @@ #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) #define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) -#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) +#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1UL<<31) #define BNX2_MISC_PERR_ENA2 0x000008ac #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0) @@ -1205,7 +1205,7 @@ #define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) #define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24) #define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25) -#define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31) +#define BNX2_NVM_CFG1_COMPAT_BYPASSS (1UL<<31) #define BNX2_NVM_CFG2 0x00006418 #define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0) @@ -1309,7 +1309,7 @@ #define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) #define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) #define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) -#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) +#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1UL<<31) #define BNX2_DMA_WCHAN_STAT 0x00000c34 #define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) @@ -1327,7 +1327,7 @@ #define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) #define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) #define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) -#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) +#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1UL<<31) #define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38 #define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) @@ -1494,7 +1494,7 @@ #define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) #define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27) #define BNX2_CTX_LOCK_STATUS (1L<<30) -#define BNX2_CTX_LOCK_REQ (1L<<31) +#define BNX2_CTX_LOCK_REQ (1UL<<31) #define BNX2_CTX_ACCESS_STATUS 0x00001040 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) @@ -1551,7 +1551,7 @@ #define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22) #define BNX2_EMAC_STATUS_MI_INT (1L<<23) #define BNX2_EMAC_STATUS_AP_ERROR (1L<<24) -#define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) +#define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1UL<<31) #define BNX2_EMAC_ATTENTION_ENA 0x00001408 #define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11) @@ -1572,7 +1572,7 @@ #define BNX2_EMAC_LED_10MB (1L<<9) #define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10) #define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19) -#define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31) +#define BNX2_EMAC_LED_BLNK_RATE_ENA (1UL<<31) #define BNX2_EMAC_MAC_MATCH0 0x00001410 #define BNX2_EMAC_MAC_MATCH1 0x00001414 @@ -1611,7 +1611,7 @@ #define BNX2_EMAC_RX_MTU_SIZE 0x0000149c #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) -#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) +#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1UL<<31) #define BNX2_EMAC_SERDES_CNTL 0x000014a4 #define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0) @@ -1931,7 +1931,7 @@ #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) -#define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) +#define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1UL<<31) #define BNX2_EMAC_TXMAC_DEBUG3 0x00001664 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) @@ -1990,7 +1990,7 @@ #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) -#define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31) +#define BNX2_EMAC_TXMAC_DEBUG4_GO (1UL<<31) #define BNX2_EMAC_TX_STAT_AC0 0x00001680 #define BNX2_EMAC_TX_STAT_AC1 0x00001684 @@ -2035,7 +2035,7 @@ #define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2) #define BNX2_RPM_CONFIG_MP_KEEP (1L<<3) #define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) -#define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31) +#define BNX2_RPM_CONFIG_IGNORE_VLAN (1UL<<31) #define BNX2_RPM_VLAN_MATCH0 0x00001810 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) @@ -2057,7 +2057,7 @@ #define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19) #define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20) #define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24) -#define BNX2_RPM_SORT_USER0_ENA (1L<<31) +#define BNX2_RPM_SORT_USER0_ENA (1UL<<31) #define BNX2_RPM_SORT_USER1 0x00001824 #define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0) @@ -2067,7 +2067,7 @@ #define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19) #define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20) #define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24) -#define BNX2_RPM_SORT_USER1_ENA (1L<<31) +#define BNX2_RPM_SORT_USER1_ENA (1UL<<31) #define BNX2_RPM_SORT_USER2 0x00001828 #define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0) @@ -2077,7 +2077,7 @@ #define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19) #define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20) #define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24) -#define BNX2_RPM_SORT_USER2_ENA (1L<<31) +#define BNX2_RPM_SORT_USER2_ENA (1UL<<31) #define BNX2_RPM_SORT_USER3 0x0000182c #define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0) @@ -2087,7 +2087,7 @@ #define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19) #define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20) #define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24) -#define BNX2_RPM_SORT_USER3_ENA (1L<<31) +#define BNX2_RPM_SORT_USER3_ENA (1UL<<31) #define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 @@ -2223,7 +2223,7 @@ #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) #define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28) -#define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) +#define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1UL<<31) #define BNX2_RPM_DEBUG1 0x00001988 #define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) @@ -2247,7 +2247,7 @@ #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) -#define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) +#define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1UL<<31) #define BNX2_RPM_DEBUG2 0x0000198c #define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) @@ -2259,7 +2259,7 @@ #define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) #define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29) #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) -#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) +#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1UL<<31) #define BNX2_RPM_DEBUG3 0x00001990 #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) @@ -2293,13 +2293,13 @@ #define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30) #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) -#define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) +#define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1UL<<31) #define BNX2_RPM_DEBUG4 0x00001994 #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) #define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) -#define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) +#define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1UL<<31) #define BNX2_RPM_DEBUG5 0x00001998 #define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) @@ -2317,7 +2317,7 @@ #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) -#define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31) +#define BNX2_RPM_DEBUG5_HOLDREG_RD (1UL<<31) #define BNX2_RPM_DEBUG6 0x0000199c #define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) @@ -2361,7 +2361,7 @@ #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) -#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) +#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1UL<<31) #define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0 #define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4 @@ -2504,11 +2504,11 @@ #define BNX2_RV2P_INSTR_LOW 0x00002834 #define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) -#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) +#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1UL<<31) #define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c #define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) -#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) +#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1UL<<31) #define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840 #define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844 @@ -2533,7 +2533,7 @@ #define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_RV2P_PFTQ_CMD_POP (1L<<30) -#define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31) +#define BNX2_RV2P_PFTQ_CMD_BUSY (1UL<<31) #define BNX2_RV2P_PFTQ_CTL 0x00002b7c #define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0) @@ -2554,7 +2554,7 @@ #define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_RV2P_TFTQ_CMD_POP (1L<<30) -#define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31) +#define BNX2_RV2P_TFTQ_CMD_BUSY (1UL<<31) #define BNX2_RV2P_TFTQ_CTL 0x00002bbc #define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0) @@ -2575,7 +2575,7 @@ #define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_RV2P_MFTQ_CMD_POP (1L<<30) -#define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31) +#define BNX2_RV2P_MFTQ_CMD_BUSY (1UL<<31) #define BNX2_RV2P_MFTQ_CTL 0x00002bfc #define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0) @@ -2732,7 +2732,7 @@ #define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_TBDR_FTQ_CMD_POP (1L<<30) -#define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31) +#define BNX2_TBDR_FTQ_CMD_BUSY (1UL<<31) #define BNX2_TBDR_FTQ_CTL 0x000053fc #define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0) @@ -2823,7 +2823,7 @@ #define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_TDMA_FTQ_CMD_POP (1L<<30) -#define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31) +#define BNX2_TDMA_FTQ_CMD_BUSY (1UL<<31) #define BNX2_TDMA_FTQ_CTL 0x00005ffc #define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0) @@ -3197,7 +3197,7 @@ #define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12) #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) -#define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31) +#define BNX2_TXP_CPU_STATE_BLOCKED_READ (1UL<<31) #define BNX2_TXP_CPU_EVENT_MASK 0x00045008 #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) @@ -3249,7 +3249,7 @@ #define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_TXP_FTQ_CMD_POP (1L<<30) -#define BNX2_TXP_FTQ_CMD_BUSY (1L<<31) +#define BNX2_TXP_FTQ_CMD_BUSY (1UL<<31) #define BNX2_TXP_FTQ_CTL 0x000453fc #define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0) @@ -3292,7 +3292,7 @@ #define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12) #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) -#define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) +#define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1UL<<31) #define BNX2_TPAT_CPU_EVENT_MASK 0x00085008 #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) @@ -3344,7 +3344,7 @@ #define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_TPAT_FTQ_CMD_POP (1L<<30) -#define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31) +#define BNX2_TPAT_FTQ_CMD_BUSY (1UL<<31) #define BNX2_TPAT_FTQ_CTL 0x000853fc #define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0) @@ -3387,7 +3387,7 @@ #define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12) #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) -#define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31) +#define BNX2_RXP_CPU_STATE_BLOCKED_READ (1UL<<31) #define BNX2_RXP_CPU_EVENT_MASK 0x000c5008 #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) @@ -3439,7 +3439,7 @@ #define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28) #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_RXP_CFTQ_CMD_POP (1L<<30) -#define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31) +#define BNX2_RXP_CFTQ_CMD_BUSY (1UL<<31) #define BNX2_RXP_CFTQ_CTL 0x000c53bc #define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0) @@ -3460,7 +3460,7 @@ #define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_RXP_FTQ_CMD_POP (1L<<30) -#define BNX2_RXP_FTQ_CMD_BUSY (1L<<31) +#define BNX2_RXP_FTQ_CMD_BUSY (1UL<<31) #define BNX2_RXP_FTQ_CTL 0x000c53fc #define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0) @@ -3503,7 +3503,7 @@ #define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12) #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) -#define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31) +#define BNX2_COM_CPU_STATE_BLOCKED_READ (1UL<<31) #define BNX2_COM_CPU_EVENT_MASK 0x00105008 #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) @@ -3555,7 +3555,7 @@ #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30) -#define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) +#define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1UL<<31) #define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) @@ -3576,7 +3576,7 @@ #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30) -#define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) +#define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1UL<<31) #define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) @@ -3597,7 +3597,7 @@ #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30) -#define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31) +#define BNX2_COM_COMQ_FTQ_CMD_BUSY (1UL<<31) #define BNX2_COM_COMQ_FTQ_CTL 0x001053fc #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) @@ -3640,7 +3640,7 @@ #define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12) #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) -#define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31) +#define BNX2_CP_CPU_STATE_BLOCKED_READ (1UL<<31) #define BNX2_CP_CPU_EVENT_MASK 0x00185008 #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) @@ -3692,7 +3692,7 @@ #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30) -#define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31) +#define BNX2_CP_CPQ_FTQ_CMD_BUSY (1UL<<31) #define BNX2_CP_CPQ_FTQ_CTL 0x001853fc #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) @@ -3735,7 +3735,7 @@ #define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12) #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) -#define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31) +#define BNX2_MCP_CPU_STATE_BLOCKED_READ (1UL<<31) #define BNX2_MCP_CPU_EVENT_MASK 0x00145008 #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) @@ -3787,7 +3787,7 @@ #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) #define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30) -#define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) +#define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1UL<<31) #define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
diff --git a/src/drivers/net/forcedeth.h b/src/drivers/net/forcedeth.h index 3a372dc..d42e069 100644 --- a/src/drivers/net/forcedeth.h +++ b/src/drivers/net/forcedeth.h
@@ -211,7 +211,7 @@ #define NV_TX_LATECOLLISION (1<<28) #define NV_TX_UNDERFLOW (1<<29) #define NV_TX_ERROR (1<<30) -#define NV_TX_VALID (1<<31) +#define NV_TX_VALID (1U<<31) #define NV_TX2_LASTPACKET (1<<29) #define NV_TX2_RETRYERROR (1<<18) @@ -223,7 +223,7 @@ #define NV_TX2_UNDERFLOW (1<<28) /* error and valid are the same for both */ #define NV_TX2_ERROR (1<<30) -#define NV_TX2_VALID (1<<31) +#define NV_TX2_VALID (1U<<31) #define NV_TX2_TSO (1<<28) #define NV_TX2_TSO_SHIFT 14 #define NV_TX2_TSO_MAX_SHIFT 14 @@ -244,7 +244,7 @@ #define NV_RX_OVERFLOW (1<<28) #define NV_RX_FRAMINGERR (1<<29) #define NV_RX_ERROR (1<<30) -#define NV_RX_AVAIL (1<<31) +#define NV_RX_AVAIL (1U<<31) #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR) #define NV_RX2_CHECKSUMMASK (0x1C000000) @@ -262,7 +262,7 @@ #define NV_RX2_FRAMINGERR (1<<24) /* error and avail are the same for both */ #define NV_RX2_ERROR (1<<30) -#define NV_RX2_AVAIL (1<<31) +#define NV_RX2_AVAIL (1U<<31) #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR) #define NV_RX3_VLAN_TAG_PRESENT (1<<16) @@ -457,7 +457,7 @@ #define NVREG_LINKSPEED_1000 50 #define NVREG_LINKSPEED_MASK (0xFFF) NvRegUnknownSetupReg5 = 0x130, -#define NVREG_UNKSETUP5_BIT31 (1<<31) +#define NVREG_UNKSETUP5_BIT31 (1U<<31) NvRegTxWatermark = 0x13c, #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
diff --git a/src/drivers/net/myri10ge_mcp.h b/src/drivers/net/myri10ge_mcp.h index 6c82b3c..cb2b1dd 100644 --- a/src/drivers/net/myri10ge_mcp.h +++ b/src/drivers/net/myri10ge_mcp.h
@@ -219,7 +219,7 @@ a power of 2 number of entries. */ MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ -#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) +#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1U << 31) /* command to bring ethernet interface up. Above parameters (plus mtu & mac address) must have been exchanged prior
diff --git a/src/drivers/net/phantom/nxhal_nic_interface.h b/src/drivers/net/phantom/nxhal_nic_interface.h index f487624..f1b4260 100644 --- a/src/drivers/net/phantom/nxhal_nic_interface.h +++ b/src/drivers/net/phantom/nxhal_nic_interface.h
@@ -88,7 +88,7 @@ #define NX_CDRP_SIGNATURE_MAKE(pcifn,version) \ ( ((pcifn) & 0xff) | \ (((version) & 0xff) << 8) | \ - (0xcafe << 16) ) + (0xcafeU << 16) ) #define NX_CDRP_CLEAR 0x00000000 #define NX_CDRP_CMD_BIT 0x80000000
diff --git a/src/drivers/net/rhine.h b/src/drivers/net/rhine.h index eef49ec..54e66df 100644 --- a/src/drivers/net/rhine.h +++ b/src/drivers/net/rhine.h
@@ -23,7 +23,7 @@ uint32_t next; } __attribute__ (( packed )); -#define RHINE_DES0_OWN (1 << 31) /*< Owned descriptor */ +#define RHINE_DES0_OWN (1U << 31) /*< Owned descriptor */ #define RHINE_DES1_IC (1 << 23) /*< Generate interrupt */ #define RHINE_TDES1_EDP (1 << 22) /*< End of packet */ #define RHINE_TDES1_STP (1 << 21) /*< Start of packet */
diff --git a/src/drivers/net/rtl818x/rtl818x.h b/src/drivers/net/rtl818x/rtl818x.h index f8d1960..79607b2 100644 --- a/src/drivers/net/rtl818x/rtl818x.h +++ b/src/drivers/net/rtl818x/rtl818x.h
@@ -81,7 +81,7 @@ #define RTL818X_TX_CONF_DISREQQSIZE (1 << 28) #define RTL818X_TX_CONF_PROBE_DTS (1 << 29) #define RTL818X_TX_CONF_HW_SEQNUM (1 << 30) -#define RTL818X_TX_CONF_CW_MIN (1 << 31) +#define RTL818X_TX_CONF_CW_MIN (1U << 31) u32 RX_CONF; #define RTL818X_RX_CONF_MONITOR (1 << 0) #define RTL818X_RX_CONF_NICMAC (1 << 1) @@ -97,7 +97,7 @@ #define RTL818X_RX_CONF_RX_AUTORESETPHY (1 << 28) #define RTL818X_RX_CONF_CSDM1 (1 << 29) #define RTL818X_RX_CONF_CSDM2 (1 << 30) -#define RTL818X_RX_CONF_ONLYERLPKT (1 << 31) +#define RTL818X_RX_CONF_ONLYERLPKT (1U << 31) u32 INT_TIMEOUT; u32 TBDA; u8 EEPROM_CMD; @@ -233,7 +233,7 @@ RTL818X_TX_DESC_FLAG_LS = (1 << 28), RTL818X_TX_DESC_FLAG_FS = (1 << 29), RTL818X_TX_DESC_FLAG_DMA = (1 << 30), - RTL818X_TX_DESC_FLAG_OWN = (1 << 31) + RTL818X_TX_DESC_FLAG_OWN = (1U << 31) }; struct rtl818x_tx_desc { @@ -266,7 +266,7 @@ RTL818X_RX_DESC_FLAG_LS = (1 << 28), RTL818X_RX_DESC_FLAG_FS = (1 << 29), RTL818X_RX_DESC_FLAG_EOR = (1 << 30), - RTL818X_RX_DESC_FLAG_OWN = (1 << 31) + RTL818X_RX_DESC_FLAG_OWN = (1U << 31) }; struct rtl818x_rx_desc {
diff --git a/src/drivers/net/skge.h b/src/drivers/net/skge.h index b13013b..ba7760d 100755 --- a/src/drivers/net/skge.h +++ b/src/drivers/net/skge.h
@@ -222,7 +222,7 @@ /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ enum { IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */ - IS_HW_ERR = 1<<31, /* Interrupt HW Error */ + IS_HW_ERR = 1U<<31, /* Interrupt HW Error */ /* Bit 30: reserved */ IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */ IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */ @@ -373,7 +373,7 @@ /* TxCtrl Transmit Buffer Control Field */ /* RxCtrl Receive Buffer Control Field */ enum { - BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */ + BMU_OWN = 1U<<31, /* OWN bit: 0=host/1=BMU */ BMU_STF = 1<<30, /* Start of Frame */ BMU_EOF = 1<<29, /* End of Frame */ BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */ @@ -950,7 +950,7 @@ * Receive Frame Status Encoding */ enum { - XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */ + XMR_FS_LEN = 0x3fffU<<18, /* Bit 31..18: Rx Frame Length */ XMR_FS_LEN_SHIFT = 18, XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/ XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/ @@ -1877,7 +1877,7 @@ /* Receive Frame Status Encoding */ enum { - GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */ + GMR_FS_LEN = 0xffffU<<16, /* Bit 31..16: Rx Frame Length */ GMR_FS_LEN_SHIFT = 16, GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */ GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */ @@ -2351,7 +2351,7 @@ /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */ /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */ enum { - XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/ + XMR_MAX_SZ_OV = 1U<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/ XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/ XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/ XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
diff --git a/src/drivers/net/sky2.h b/src/drivers/net/sky2.h index 9c33131..405ed7f 100644 --- a/src/drivers/net/sky2.h +++ b/src/drivers/net/sky2.h
@@ -54,7 +54,7 @@ /* Yukon-2 */ enum pci_dev_reg_1 { - PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ + PCI_Y2_PIG_ENA = 1U<<31, /* Enable Plug-in-Go (YUKON-2) */ PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */ PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ @@ -70,7 +70,7 @@ }; enum pci_dev_reg_2 { - PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */ + PCI_VPD_WR_THR = 0xffUL<<24, /* Bit 31..24: VPD Write Threshold */ PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */ PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */ @@ -85,7 +85,7 @@ /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ enum pci_dev_reg_4 { /* (Link Training & Status State Machine) */ - P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */ + P_PEX_LTSSM_STAT_MSK = 0x7fUL<<25, /* Bit 31..25: PEX LTSSM Mask */ #define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK) P_PEX_LTSSM_L1_STAT = 0x34, P_PEX_LTSSM_DET_STAT = 0x01, @@ -108,7 +108,7 @@ /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ enum pci_dev_reg_5 { /* Bit 31..27: for A3 & later */ - P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */ + P_CTL_DIV_CORE_CLK_ENA = 1U<<31, /* Divide Core Clock Enable */ P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */ P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */ P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */ @@ -343,7 +343,7 @@ /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ enum { - Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */ + Y2_IS_HW_ERR = 1U<<31, /* Interrupt HW Error */ Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */ Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */ @@ -446,7 +446,7 @@ /* B2_GPIO */ enum { - GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */ + GLB_GPIO_CLK_DEB_ENA = 1U<<31, /* Clock Debug Enable */ GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */ GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */ @@ -650,7 +650,7 @@ /* Q_TEST 32 bit Test Register */ enum { /* Transmit */ - F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */ + F_TX_CHK_AUTO_OFF = 1U<<31, /* Tx checksum auto calc off (Yukon EX) */ F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */ /* Receive */ @@ -757,7 +757,7 @@ /* Rx BMU Control / Status Registers (Yukon-2) */ enum { - BMU_IDLE = 1<<31, /* BMU Idle State */ + BMU_IDLE = 1U<<31, /* BMU Idle State */ BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */ BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */ @@ -1760,7 +1760,7 @@ /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ enum { - TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */ + TX_STFW_DIS = 1U<<31,/* Disable Store & Forward (Yukon-EC Ultra) */ TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */ TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
diff --git a/src/drivers/net/velocity.h b/src/drivers/net/velocity.h index 84817d1..98fd0a9 100644 --- a/src/drivers/net/velocity.h +++ b/src/drivers/net/velocity.h
@@ -36,7 +36,7 @@ } __attribute__ ((packed)); #define VELOCITY_DES0_RMBC(_n) (((_n) >> 16) & 0x1fff) -#define VELOCITY_DES0_OWN (1 << 31) +#define VELOCITY_DES0_OWN (1U << 31) #define VELOCITY_DES0_TERR (1 << 15) #define VELOCITY_DES0_RXOK (1 << 15) #define VELOCITY_DES0_FDX (1 << 14) @@ -74,7 +74,7 @@ #define VELOCITY_DES1_JMBO (1 << 17) #define VELOCITY_DES1_CRC (1 << 16) -#define VELOCITY_DES2_IC (1 << 31) +#define VELOCITY_DES2_IC (1U << 31) #define VELOCITY_DES2_SIZE(_n) (((_n) & 0x1fff) << 16) /** Number of receive descriptors
diff --git a/src/net/tcp/oncrpc.c b/src/net/tcp/oncrpc.c index e5ddc28..8a397e2 100644 --- a/src/net/tcp/oncrpc.c +++ b/src/net/tcp/oncrpc.c
@@ -48,8 +48,8 @@ FILE_SECBOOT ( FORBIDDEN ); /** Set most significant bit to 1. */ -#define SET_LAST_FRAME( x ) ( (x) | 1 << 31 ) -#define GET_FRAME_SIZE( x ) ( (x) & ~( 1 << 31 ) ) +#define SET_LAST_FRAME( x ) ( (x) | ( 1U << 31 ) ) +#define GET_FRAME_SIZE( x ) ( (x) & ~( 1U << 31 ) ) #define ONCRPC_CALL 0 #define ONCRPC_REPLY 1