| commit | ad5030d73171d9aae30ee74c4b2cd41686b93bcd | [log] [tgz] |
|---|---|---|
| author | Kedar Athawale <kedara@qti.qualcomm.com> | Tue Nov 25 21:38:58 2025 -0800 |
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | Wed Nov 26 06:37:30 2025 +0000 |
| tree | b00f074b445d8bbb85a89156f920277a19dad742 | |
| parent | 30e72bc7c796ccf715f76ed1423e566641a16500 [diff] |
ArmPkg/ArmPsciMpServices: Prevent SIMD traps on secondary cores On AArch64, PrePi/SEC configures the primary core to avoid trapping VFP/SIMD exceptions.However, when ArmPsciMpServicesDxe enables secondary cores, FP/SIMD access is not configured, causing traps on SIMD instructions. Set FPEN bits 21:20[1] in CPACR_EL1 for secondary cores to allow FP/SIMD instructions at EL1 and prevent VFP exceptions from being trapped. Signed-off-by: Kedar Athawale <kedara@qti.qualcomm.com>