Google Git
Sign in
qemu / edk2 / refs/heads/dependabot/pip/edk2-pytool-library-0.20.0 / . / MdePkg / Include / Library / S3PciSegmentLib.h
blob: 5067d4fcbbe06ed407fdbd2978872320d96417e9 [file] [log] [blame]
/** @file
The multiple segments PCI configuration Library Services that carry out
PCI configuration and enable the PCI operations to be replayed during an
S3 resume. This library class maps directly on top of the PciSegmentLib class.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __S3_PCI_SEGMENT_LIB__
#define __S3_PCI_SEGMENT_LIB__
/**
Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
and PCI Register to an address that can be passed to the S3 PCI Segment Library functions.
Computes an address that is compatible with the PCI Segment Library functions.
The unused upper bits of Segment, Bus, Device, Function,
and Register are stripped prior to the generation of the address.
@param Segment PCI Segment number. Range 0..65535.
@param Bus PCI Bus number. Range 0..255.
@param Device PCI Device number. Range 0..31.
@param Function PCI Function number. Range 0..7.
@param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
@return The address that is compatible with the PCI Segment Library functions.
**/
#define S3_PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \
((Segment != 0) ? \
( ((Register) & 0xfff) | \
(((Function) & 0x07) << 12) | \
(((Device) & 0x1f) << 15) | \
(((Bus) & 0xff) << 20) | \
(LShiftU64 ((Segment) & 0xffff, 32)) \
) : \
( ((Register) & 0xfff) | \
(((Function) & 0x07) << 12) | \
(((Device) & 0x1f) << 15) | \
(((Bus) & 0xff) << 20) \
) \
)
/**
Reads an 8-bit PCI configuration register, and saves the value in the S3 script to
be replayed on S3 resume.
Reads and returns the 8-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 8-bit PCI configuration register specified by Address.
**/
UINT8
EFIAPI
S3PciSegmentRead8 (
IN UINT64 Address
);
/**
Writes an 8-bit PCI configuration register, and saves the value in the S3 script to
be replayed on S3 resume.
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
**/
UINT8
EFIAPI
S3PciSegmentWrite8 (
IN UINT64 Address,
IN UINT8 Value
);
/**
Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves
the value in the S3 script to be replayed on S3 resume.
Reads the 8-bit PCI configuration register specified by Address,
performs a bitwise OR between the read result and the value specified by OrData,
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
**/
UINT8
EFIAPI
S3PciSegmentOr8 (
IN UINT64 Address,
IN UINT8 OrData
);
/**
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and
saves the value in the S3 script to be replayed on S3 resume.
Reads the 8-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
**/
UINT8
EFIAPI
S3PciSegmentAnd8 (
IN UINT64 Address,
IN UINT8 AndData
);
/**
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to
be replayed on S3 resume.
Reads the 8-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 8-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
**/
UINT8
EFIAPI
S3PciSegmentAndThenOr8 (
IN UINT64 Address,
IN UINT8 AndData,
IN UINT8 OrData
);
/**
Reads a bit field of a PCI configuration register, and saves the value in the
S3 script to be replayed on S3 resume.
Reads the bit field in an 8-bit PCI configuration register. The bit field is
specified by the StartBit and the EndBit. The value of the bit field is
returned.
If any reserved bits in Address are set, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@return The value of the bit field read from the PCI configuration register.
**/
UINT8
EFIAPI
S3PciSegmentBitFieldRead8 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit
);
/**
Writes a bit field to a PCI configuration register, and saves the value in
the S3 script to be replayed on S3 resume.
Writes Value to the bit field of the PCI configuration register. The bit
field is specified by the StartBit and the EndBit. All other bits in the
destination PCI configuration register are preserved. The new value of the
8-bit register is returned.
If any reserved bits in Address are set, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@param Value New value of the bit field.
@return The value written back to the PCI configuration register.
**/
UINT8
EFIAPI
S3PciSegmentBitFieldWrite8 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT8 Value
);
/**
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes
the result back to the bit field in the 8-bit port, and saves the value in the
S3 script to be replayed on S3 resume.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise OR between the read result and the value specified by
OrData, and writes the result to the 8-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT8
EFIAPI
S3PciSegmentBitFieldOr8 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT8 OrData
);
/**
Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
AND, writes the result back to the bit field in the 8-bit register, and
saves the value in the S3 script to be replayed on S3 resume.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise AND between the read result and the value specified by AndData, and
writes the result to the 8-bit PCI configuration register specified by
Address. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are
serialized. Extra left bits in AndData are stripped.
If any reserved bits in Address are set, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@param AndData The value to AND with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT8
EFIAPI
S3PciSegmentBitFieldAnd8 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT8 AndData
);
/**
Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
bitwise OR, writes the result back to the bit field in the 8-bit port,
and saves the value in the S3 script to be replayed on S3 resume.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise OR between the read result and
the value specified by AndData, and writes the result to the 8-bit PCI
configuration register specified by Address. The value written to the PCI
configuration register is returned. This function must guarantee that all PCI
read and write operations are serialized. Extra left bits in both AndData and
OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register.
**/
UINT8
EFIAPI
S3PciSegmentBitFieldAndThenOr8 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT8 AndData,
IN UINT8 OrData
);
/**
Reads a 16-bit PCI configuration register, and saves the value in the S3 script
to be replayed on S3 resume.
Reads and returns the 16-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 16-bit PCI configuration register specified by Address.
**/
UINT16
EFIAPI
S3PciSegmentRead16 (
IN UINT64 Address
);
/**
Writes a 16-bit PCI configuration register, and saves the value in the S3 script to
be replayed on S3 resume.
Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The parameter of Value.
**/
UINT16
EFIAPI
S3PciSegmentWrite16 (
IN UINT64 Address,
IN UINT16 Value
);
/**
Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit
value, and saves the value in the S3 script to be replayed on S3 resume.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise OR between the read result and the value specified by OrData, and
writes the result to the 16-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned. This function
must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function and
Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
S3PciSegmentOr16 (
IN UINT64 Address,
IN UINT16 OrData
);
/**
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and
saves the value in the S3 script to be replayed on S3 resume.
Reads the 16-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
and writes the result to the 16-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
**/
UINT16
EFIAPI
S3PciSegmentAnd16 (
IN UINT64 Address,
IN UINT16 AndData
);
/**
Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to
be replayed on S3 resume.
Reads the 16-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 16-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
**/
UINT16
EFIAPI
S3PciSegmentAndThenOr16 (
IN UINT64 Address,
IN UINT16 AndData,
IN UINT16 OrData
);
/**
Reads a bit field of a PCI configuration register, and saves the value in the
S3 script to be replayed on S3 resume.
Reads the bit field in a 16-bit PCI configuration register. The bit field is
specified by the StartBit and the EndBit. The value of the bit field is
returned.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@return The value of the bit field read from the PCI configuration register.
**/
UINT16
EFIAPI
S3PciSegmentBitFieldRead16 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit
);
/**
Writes a bit field to a PCI configuration register, and saves the value in
the S3 script to be replayed on S3 resume.
Writes Value to the bit field of the PCI configuration register. The bit
field is specified by the StartBit and the EndBit. All other bits in the
destination PCI configuration register are preserved. The new value of the
16-bit register is returned.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param Value New value of the bit field.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
S3PciSegmentBitFieldWrite16 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 Value
);
/**
Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
the result back to the bit field in the 16-bit port, and saves the value in the
S3 script to be replayed on S3 resume.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise OR between the read result and the value specified by
OrData, and writes the result to the 16-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
S3PciSegmentBitFieldOr16 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 OrData
);
/**
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
AND, writes the result back to the bit field in the 16-bit register, and
saves the value in the S3 script to be replayed on S3 resume.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise AND between the read result and the value specified by AndData, and
writes the result to the 16-bit PCI configuration register specified by
Address. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are
serialized. Extra left bits in AndData are stripped.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param AndData The value to AND with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
S3PciSegmentBitFieldAnd16 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 AndData
);
/**
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
bitwise OR, writes the result back to the bit field in the 16-bit port,
and saves the value in the S3 script to be replayed on S3 resume.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise OR between the read result and
the value specified by AndData, and writes the result to the 16-bit PCI
configuration register specified by Address. The value written to the PCI
configuration register is returned. This function must guarantee that all PCI
read and write operations are serialized. Extra left bits in both AndData and
OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
S3PciSegmentBitFieldAndThenOr16 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 AndData,
IN UINT16 OrData
);
/**
Reads a 32-bit PCI configuration register, and saves the value in the S3 script
to be replayed on S3 resume.
Reads and returns the 32-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@return The 32-bit PCI configuration register specified by Address.
**/
UINT32
EFIAPI
S3PciSegmentRead32 (
IN UINT64 Address
);
/**
Writes a 32-bit PCI configuration register, and saves the value in the S3 script to
be replayed on S3 resume.
Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@return The parameter of Value.
**/
UINT32
EFIAPI
S3PciSegmentWrite32 (
IN UINT64 Address,
IN UINT32 Value
);
/**
Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit
value, and saves the value in the S3 script to be replayed on S3 resume.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise OR between the read result and the value specified by OrData, and
writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned. This function
must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and
Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT32
EFIAPI
S3PciSegmentOr32 (
IN UINT64 Address,
IN UINT32 OrData
);
/**
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and
saves the value in the S3 script to be replayed on S3 resume.
Reads the 32-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written to the PCI configuration register.
**/
UINT32
EFIAPI
S3PciSegmentAnd32 (
IN UINT64 Address,
IN UINT32 AndData
);
/**
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to
be replayed on S3 resume.
Reads the 32-bit PCI configuration register specified by Address,
performs a bitwise AND between the read result and the value specified by AndData,
performs a bitwise OR between the result of the AND operation and the value specified by OrData,
and writes the result to the 32-bit PCI configuration register specified by Address.
The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are serialized.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the PCI configuration register.
@return The value written to the PCI configuration register.
**/
UINT32
EFIAPI
S3PciSegmentAndThenOr32 (
IN UINT64 Address,
IN UINT32 AndData,
IN UINT32 OrData
);
/**
Reads a bit field of a PCI configuration register, and saves the value in the
S3 script to be replayed on S3 resume.
Reads the bit field in a 32-bit PCI configuration register. The bit field is
specified by the StartBit and the EndBit. The value of the bit field is
returned.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@return The value of the bit field read from the PCI configuration register.
**/
UINT32
EFIAPI
S3PciSegmentBitFieldRead32 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit
);
/**
Writes a bit field to a PCI configuration register, and saves the value in
the S3 script to be replayed on S3 resume.
Writes Value to the bit field of the PCI configuration register. The bit
field is specified by the StartBit and the EndBit. All other bits in the
destination PCI configuration register are preserved. The new value of the
32-bit register is returned.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param Value New value of the bit field.
@return The value written back to the PCI configuration register.
**/
UINT32
EFIAPI
S3PciSegmentBitFieldWrite32 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 Value
);
/**
Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes
the result back to the bit field in the 32-bit port, and saves the value in the
S3 script to be replayed on S3 resume.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise OR between the read result and the value specified by
OrData, and writes the result to the 32-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized. Extra left bits in OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT32
EFIAPI
S3PciSegmentBitFieldOr32 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 OrData
);
/**
Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
AND, and writes the result back to the bit field in the 32-bit register, and
saves the value in the S3 script to be replayed on S3 resume.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise AND between the read result and the value specified by AndData, and
writes the result to the 32-bit PCI configuration register specified by
Address. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are
serialized. Extra left bits in AndData are stripped.
If any reserved bits in Address are set, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param AndData The value to AND with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT32
EFIAPI
S3PciSegmentBitFieldAnd32 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 AndData
);
/**
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
bitwise OR, writes the result back to the bit field in the 32-bit port,
and saves the value in the S3 script to be replayed on S3 resume.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise OR between the read result and
the value specified by AndData, and writes the result to the 32-bit PCI
configuration register specified by Address. The value written to the PCI
configuration register is returned. This function must guarantee that all PCI
read and write operations are serialized. Extra left bits in both AndData and
OrData are stripped.
If any reserved bits in Address are set, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register.
**/
UINT32
EFIAPI
S3PciSegmentBitFieldAndThenOr32 (
IN UINT64 Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 AndData,
IN UINT32 OrData
);
/**
Reads a range of PCI configuration registers into a caller supplied buffer,
and saves the value in the S3 script to be replayed on S3 resume.
Reads the range of PCI configuration registers specified by StartAddress and
Size into the buffer specified by Buffer. This function only allows the PCI
configuration registers from a single PCI function to be read. Size is
returned. When possible 32-bit PCI configuration read cycles are used to read
from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
and 16-bit PCI configuration read cycles may be used at the beginning and the
end of the range.
If any reserved bits in StartAddress are set, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
Function and Register.
@param Size Size in bytes of the transfer.
@param Buffer Pointer to a buffer receiving the data read.
@return Size
**/
UINTN
EFIAPI
S3PciSegmentReadBuffer (
IN UINT64 StartAddress,
IN UINTN Size,
OUT VOID *Buffer
);
/**
Copies the data in a caller supplied buffer to a specified range of PCI
configuration space, and saves the value in the S3 script to be replayed on S3
resume.
Writes the range of PCI configuration registers specified by StartAddress and
Size from the buffer specified by Buffer. This function only allows the PCI
configuration registers from a single PCI function to be written. Size is
returned. When possible 32-bit PCI configuration write cycles are used to
write from StartAdress to StartAddress + Size. Due to alignment restrictions,
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
and the end of the range.
If any reserved bits in StartAddress are set, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
@param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
Function and Register.
@param Size Size in bytes of the transfer.
@param Buffer Pointer to a buffer containing the data to write.
@return The parameter of Size.
**/
UINTN
EFIAPI
S3PciSegmentWriteBuffer (
IN UINT64 StartAddress,
IN UINTN Size,
IN VOID *Buffer
);
#endif